JPS62154932A - Data transmission system among plural equipments - Google Patents

Abstract

PURPOSE:To shorten the overall length of a transmission line greatly as compared with a conventional star type system and to a half as long as that of a loop type system by connecting plural devices to a transmission line for both transmission and reception. CONSTITUTION:(n) sets of devices are connected with each other on a two-wire multidrop basis and two transmission lines which connect the (n) sets of devices are used for both transmission and reception. The (n) sets of devices are each equipped with a line interface I/F and have a communication with one another through those line I/Fs. All the line I/F except the line I/F of the device 1 which has a function for sending out a synchronizing signal S are of the same constitution. Consequently, the need for a main controller is eliminated unlike before and the overall length of the transmission line can be shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION Summary of the Invention A plurality of devices are connected by a transmitting/receiving transmission line, and synchronization signals are provided at regular intervals. Each device creates a plurality of time slots within a certain period based on this synchronization signal. One of these time slots is for synchronization signals, the other is for control signal transmission and reception, and the remaining time slots are for data signal transmission and reception assigned to each device. In the time slot for control signal transmission and reception.

Connections between arbitrary devices are attempted. The connected device is
Data signals are mutually transmitted and received in time slots for transmitting and receiving data signals.

Table of contents (1) Background of the invention (1, 1) Technical field (1, 2) Prior art (2) Overview of the invention (2, 1) Purpose of the invention (2, 2) Structure and effects of the invention (3) Implementation Example explanation (3, 1) Overview of overall system configuration and operation (3,
2) Device configuration (3, 3) Synchronization establishment processing (initial processing) (3, 4) Message format (3, 5) Connection and communication processing (3, 8) Collision detection (1) Background of the invention (1, 1) ) Technical field This invention relates to a data transmission system between a plurality of devices, and more specifically, to a system for mutually transmitting and receiving digital data including voice data between a plurality of terminals in a local telephone exchange system or other local network. Regarding the system for

(1,2) Conventional technology For data transmission systems between multiple devices.

Typical examples include star network systems and loop network systems.

However, all of these conventional systems require a main controller for connection and communication, and multiple terminals connected to the main controller transmit data to each other via the main controller. . Even when the number of terminals is extremely small, the installation of a main control device is unavoidable, which poses a problem of increased equipment investment costs.

In addition, in these conventional systems, it is necessary to provide the main controller with communication interfaces equal to the number of terminals, so the configuration of the main controller becomes complicated and expensive. .

Furthermore, in a star system, all terminals are connected to the main controller by separate transmission lines, resulting in a very long total transmission line length.

A transmit line and a receive line are also required in a loop type system.

(2) Summary of the invention (2, 1,) Purpose of the invention This invention provides data transmission between multiple devices that does not require a conventional main control device and can shorten the total transmission line length. The purpose is to provide a system.

(2, 2) Structure and effect of the invention A data transmission system between a plurality of devices according to the present invention is composed of a plurality of devices connected by a transmission line for both transmission and reception, and means for transmitting a synchronization signal at a constant cycle. has been done. Each device is provided with means for creating a plurality of time slots divided by a number greater than the number of devices within the above-mentioned fixed period based on the synchronization signal. Each time slot includes a time length for signal transmission and reception and a maximum inter-device propagation delay time of the signal.

Also, one of these time slots is used for synchronization signals, the other time slot is used for transmitting and receiving control signals, and the remaining time slots are used for transmitting and receiving data. Furthermore, each device
A first gate that is opened in synchronization with a time slot for synchronization signals, a second gate that is opened in synchronization with a time slot for transmitting and receiving control signals, and a second gate that is opened in synchronization with a time slot for transmitting and receiving data that corresponds to the device. It includes a third gate that is opened and means for transmitting and receiving necessary signals when each gate is opened.

Preferably, one device includes means for transmitting a synchronization signal. In this case, the time slot creation means of one device creates a time slot based on the synchronization signal to be transmitted. The time slot creation means of the other device receives the synchronization signal transmitted from the one device and creates a time slot based on the received synchronization signal.

According to this invention, since multiple devices are connected by a transmission line that is used for both transmitting and receiving purposes, the total transmission length is extremely short compared to a conventional star type system, and is only half that length compared to a loop type system. Become.

Further, the present invention does not require a main control device having exchange or connection functions as in the prior art, and it is sufficient to simply provide a means for generating a synchronizing signal of a constant period. Synchronization signal generation means can also be integrated into at least one of the devices.

Each device has its own connection function.

It is possible to construct a system with at least three devices without providing a main control device, and the number of connected devices can be increased sequentially as necessary.

Further, according to the present invention, devices can communicate with each other in each period in which a synchronization signal is generated, so real-time data transmission and reception is ensured, and communication between arbitrary devices is possible.

(3) Description of Embodiments (3, 1) Overview of overall system configuration and operation FIG. 1 schematically shows the overall configuration of a data transmission system according to the present invention.

In FIG. 1(A), n devices are interconnected by a two-wire multi-drop method.

The two transmission lines connecting the n devices are used for both transmission and reception. These devices are, for example, telephones.

It is a terminal device controlled by another computer, and for convenience, 1, 2. ..., i, ..., ni, ....

It is numbered n.

Each of the n devices has a line interface (1/
F) and communicate with each other via this line I/F. All line I/Fs except the line I/F of device 1 have the function of sending out the synchronization signal S.
have exactly the same configuration.

The fact that device 1 generates the synchronization signal S does not mean that device 1 has the initiative in communication. By completely separating only this synchronizing signal generation function from the device 1,
The synchronizing signal generator 10 may be connected to the line as shown in FIG. By doing this, it is possible to position the n devices as having exactly the same functions regarding mutual communication and being completely equal in one communication system.

In the following description, for convenience, it is assumed that the device 1 has a function of generating the synchronization signal S.

FIG. 2 shows the timing relationships for the entire system. The device 1 sends out a synchronizing signal S on the line at intervals of a fixed time T, and divides two periods T into (n+2) pieces, so that consecutive (n
→−2) time slots ST (x is s, c,
1+ 2.・=+M, pa', -1,...lc,...+n). Other device 2
~n receives the synchronization signal S transmitted from the device 1.

Based on the received synchronization signal S, (n+2) consecutive time slots ST having the same time length are created in each device in the same way. As described below, the synchronization signal S has a specific bit pattern so that each device 2-n can detect this signal S. The series of time slots TS in each device 2 to n are delayed in phase by the signal propagation time with respect to that in device 1.

The first time slot TS is n units (7)
For establishing synchronization of the amount of bacteria loaded (synchronization channel), two series of synchronization signals S are transmitted and received in this time φ slot TS.

The second time slot TS interconnects at least two devices in the n installations.

or is for disconnecting (control channel)
. At this time or slot TS.

For example, if one device addresses another device and issues a connection request, and the other device responds with a connection completion to the corresponding device in a subsequent time slot of period T, then The two devices are connected to each other and are ready to communicate. The same procedure will be used to disconnect two connected devices, as will be described in detail later. The signal transmitted and received in this time slot TSc is called a control signal D.

Other times and slots T S 1 to TSn are used for transmitting and receiving data (data channels). The time φ slot TS is a time period during which the device 1 transmits data. At this time, the device connected to device 1 receives this sent data. For example, when a device i and a device are connected to communicate with each other, device i sends out a data signal in time slot TSi, device k receives it, and device k sends a data signal in time slot TSk. The signal D1 (is sent out and is received by the device i. As a result, full-duplex data communication and simultaneous two-way voice communication are realized.

Each of the above signals S, D, D −D is c
1' n Consists of the same number of bits, for example 10 bits as described later. Let the time length of these signals be τ.

As mentioned above, the phases of the time slots in each device 1-n are mutually offset by the propagation time. Further, the signals sent from each device 1 to n are on the same line. A guard time τ is provided in each time slot in order to prevent the signals sent out from each device 1 to n from overlapping each other on the transmission line -1- due to delays due to propagation time. Let the propagation time in the two devices with the longest transmission distance be the maximum propagation delay time τ. The condition for preventing signals sent from different devices during different time slots from overlapping with each other is given by a quadratic equation, where the time length of the time slot is rTs.

[TS　　　　　-τb172 〉2−τd+τb　　　　　　　　　　　　　　　　　　　...(1) From this.

-11-Uta2・τd×τ2 . . . (2>).It can be seen that it is sufficient to provide a guard time τ of a length that satisfies the condition of equation (2).

FIG. 3 shows the timing of signal transmission and reception between two devices and the bit configuration of each signal. Here, the state in which a data signal is transmitted from device i to device k is illustrated in an enlarged scale. The transmitting device i sends out a data signal D in synchronization with the time slot TS (synchronized with the start of the time slot TS). Indeed, since the propagation delay time varies depending on the distance between the communicating devices, the signal arrives at the receiving device within the time slot TS, but the phase of the reception timing is time slot TS,
change within. In other words, it becomes asynchronous. Therefore, in order to cope with the case where the reception timing is asynchronous, a start bit ST is added before the bit string d1 to d8 of the signal.
A start-stop synchronization method is adopted in which a stop-pill SP and a stop-pill are added later. Therefore, the data
Assuming that the bit consists of 8 bits, the signal length is 1
It becomes 0 bit.

Signals other than the data signal, ie, the synchronization signal S and the control signal D, also have an asynchronous bit structure.

FIG. 4 shows an example of the structure of the synchronizing signal S. All data bits d ``”' d g are 1,
There are a start bit ST and a stop bit SP before and after this bit string. Thus, the synchronization signal S has a specific bit pattern.

(3, 2) Device Configuration FIG. 5 shows an example of the configuration of two series of devices 1 to n. Since the hardware configuration of all devices is exactly the same, FIG. 5 shows only one device. This device is suitable for transmitting and receiving digital data.

Processing such as creation of time slots, connection control, creation of transmission data, decoding of received data, and communication with the CPU is performed by the CPU 20, preferably a microprocessor. This CPU 20 includes a ROM 2+ that stores the program, a RAM 22 that stores data necessary for control, such as the number of the device, data to be transmitted, received data, etc., a time slot gate signal generation circuit 23, and a host CPU. Interface with 2G, control signal.

The transmission and reception buffers 34 and 33 of the data signal Di and the transmission and reception buffers 3G and 35 of the data signal Di are connected via various buses.

The time slot gate signal generation circuit 23 is.

Under the control of the CPU 20, gate control signals 01 to G6 are generated at timings to be described later.

The synchronizing signal detecting circuit 31 detects the above-mentioned specific bi-soto pattern (FIG. 4), and includes an AND circuit inputting, for example, eight bit data d'=ds. The synchronization signal generation circuit 32 generates a synchronization signal S having the same specific bit pattern as described above.

Synchronous signal generation circuit 32. Control signal transmission buffer 34 and data transmission buffer 3B are bus-connected to parallel-to-serial conversion circuit 24 via gates 2.4 and 6, respectively, and further connected to a transmission line via this circuit 24. Similarly, the synchronization signal detection circuit 31. Control signal reception buffer 3
3 and data reception buffer 35 are respectively connected to gate 1
．． It is bus-connected to a direct-curve conversion circuit 25 via circuits 3 and 5, and further connected to a transmission line via this circuit 25.

FIG. 6 shows an example of a device suitable for communicating analog data, in which a device capable of transmitting and receiving voice is shown. A telephone 29, which is an acoustic/electrical converter, is used to transmit and receive voice. A codec (CODEC, A-D/DA interface or code/decoder circuit) for encoding or digitizing (e.g. PCM encoding) the analog signal from the telephone 29 and converting the digital signal into an analog voice signal. 27. and subscriber circuit 2 with functions such as sending out dial signals and amplifying voice current.
There are 8. Copeic 27 sends data.

If it is connected to the receive buffer 38 and 35 by bus =
15 = both connected to circuit 28; The subscriber circuit 28 is CP
Bus connected to U20. The telephone 29 is connected to this circuit 2
It is connected to the copier 27 via 8.

The rest of the configuration is the same as that shown in FIG. 5, except that the interface 26 with the host CPU is not provided, so the same components are given the same reference numerals.

FIG. 7 shows the time slot gate signal generation circuit 23.
An example of a specific configuration is shown. Synchronous signal detection circuit 3
The synchronization signal detection signal outputted from 1 (in the case of devices 2 to n) or the synchronization signal generation command signal given from the CPU 20 to the synchronization signal generation circuit 32 is given as a start signal to the counter 59 via the OR circuit 49. As a result, the counter 59 starts counting from zero. The relationship between the synchronization signal generation command signal or the detection signal and the counting output of the counter 59 is shown in FIG. The counter 59 calculates the number of time slots (TS, TS, TS, TSs,
c 1' 2 = 16 - . . . ).

This counting output is given to matching circuits 51-5B, respectively.

On the other hand, set value registers 41 to 46 are provided in the matching circuits 51 to 56, respectively. These registers are preset by the CPU 20 with values corresponding to count values representing the number of time slots in which the corresponding gates are to be opened. The outputs of registers 41-46 are sent to corresponding matching circuits 51-56, respectively.

Therefore, in a time slot where the count output of the counter 59 and the set value of the register match, the gate control signal (Gl~
G6) occurs. For example, as shown in Figure @8, when a set value of 1010 is set in the register 46, the gate control signal G6 is generated in the time slot TS4.

Time◆The slot gate signal generation circuit 23 further includes decoders 47 and 48 for gates 1 and 2 to forcefully and permanently close these gates.
is provided. When a command to forcibly close gate 1 is given by the CPU 20, the decoder 47 decodes this and generates a low level signal, setting one input terminal of the AND circuit 57 to a low level. Also, the gate control signal G1 is not sent out. In the same way,
When a forced closing command for the gate 2 is given by the CPU 20, the decoder 48 decodes it and outputs the AND circuit 58.
is closed, and the output of gate control signal G2 is prohibited.

(a, a) Synchronization establishment processing (initial processing) As described above, the device 1 has the function of creating and sending out the synchronization signal S in order to synchronize the entire system. This device 1 does not need to receive the synchronization signal S. Hence the operation in device 1.

In particular, the processing procedure of the CPU 20 is shown in FIG.

When the power is turned on, initial processing of the device 1 itself is first performed (step 101). And the synchronization signal S
Since there is no need to receive the signal, a forced closing command is given to the decoder 47 to close the gate 1, so the gate circuit 57 is always closed.

Gate control signal G1 is never output (step 102). This state persists forever.

Also, the CPU 20 sets the register 42 to the set value 000.
0 (corresponding to time slot TS) is preset, and a synchronization signal generation command is generated from the CPU 20 and given to the synchronization signal generation circuit 32 and the counter 59. As a result, the counter 59 starts counting operation,
Generates a count output corresponding to the time slot sequence. When the set value of the register 42 and the count value of the counter 59 match, the match circuit 52 outputs the gate control signal G2.
is output, thereby opening gate 2. In response to the synchronization signal generation command, the synchronization signal generation circuit 32 generates a synchronization signal S, which is sent from the parallel to serial conversion circuit 24 to the transmission line through the gate 2, which is open at that time (step 1).
03).

When a predetermined period T has elapsed from this point (step 104), gate 2 is similarly opened and synchronization signal S is sent out (step 103).

If counter 59 is made into a ring counter.

The above-mentioned operation is repeated every cycle T by the CPU 20 simply giving an initial operation command (synchronization signal generation command) and this counter runs on its own. When the count value of the counter 59 reaches oooo, the synchronization signal generation circuit 32 is triggered to generate the synchronization signal S by the rise (or fall) of the count output of the counter.

The other devices 2 to n other than device 1 do not send out the synchronization signal S, but receive the synchronization signal S from device 1 and create time slot sequences synchronized therewith. Therefore, the operations in the other devices 2 to n are as shown in FIG.

Initial processing of the device itself is first performed (step 111). This initial processing places the counter 59 in a reset state, and its count output represents 0000. By setting the set value 0000 in the register 41, the gate control signal G1 is generated from the matching circuit 51,
Since the signal is sent out via the AND circuit 57 (at this time, the output of the decoder 47 is at a high level), the gate 1 is kept open. Further, since the CPU 20 gives the decoder 48 a forced closing command for the gate 2, the output of the decoder 48 becomes low level and the gate circuit 58 is closed, so that the gate control signal G2 is not output and the gate 2 is closed. is permanently closed (step 112).

In this state, it is sent out from the device 1, and is sent to the transmission line, the direct curve conversion circuit 25. and synchronization signal S input via gate 1
wait. When the detection circuit 31 detects the synchronization signal S (step 113), the counter 59 starts counting. Time synchronized with the detected synchronization signal S
Count values representing the slot sequence are sequentially output from the counter 59. Detection of the first synchronization signal S is CP
When provided to U20, CPU 20 provides register 41 with a set value corresponding to the last time-slot TS of the time-slot sequence. When the count value of the counter 59 matches this set value, the gate control signal G1
is output, gate 1 opens and prepares for input of the primary synchronization signal S. When the next synchronizing signal S is detected, the counter 59 starts counting again from zero. In this way, in devices 2 to n, gate 1 is opened every cycle T, and each time a synchronization signal S sent from device 1 is received, a time or slot sequence synchronized with the synchronization signal S is created. (
Step 114). In addition, in the devices 2 to n, the CPU 20
Forward protection and backward protection processing of the synchronization signal S is also performed (step 115).

(3, 4) Message Format Various formats can be adopted as the format of the control message and data signal sent and received by the control signal D, and the data message sent and received by (i-1 to n). , - As an example, a case where a format called HDLC (High Level Data Control) is used will be briefly explained.

The frame format of this HDLC is shown in FIG. 9(A), which consists of two start flag (P) fields (8 bits), two address (A) fields (8 bits).

Control (control 20) field (8 bits), information (1) field (arbitrary number of bits), inspection (frame φ check sequence, FCS) field (16 bits), and termination flag (F) field (8 bits)
It consists of

The start flag field and end flag field are for identifying the beginning and end of a frame. Furthermore, the start flag starts checking for transmission errors using the C:RC (cyclic redundancy ψ check) method, and the end flag ends this checking.

The address field is used to specify the address of the communicating station. For example, when device l attempts to communicate with device k, the address field of the control message sent from device i to device k is device (communication partner station) k.
When device k responds to device i in response to this control message, the address of device i is set in the address field of the response control message.

When data telegrams are sent and received between devices i and k after the connection between device i and device k is completed, the address field of the data telegram follows the rules of the HLDC procedure.

Data telegrams do not necessarily require address data. Because after the connection is completed, the data channel formed by a particular time slot is
This is because the two devices are connected in a 1=1 relationship.

The control field is used to distinguish between a call from the own station to the other station, and a response to a call from the other station to the own station. In the HDLC regulations, this is Hall (P),
Final (F), etc.

The information field takes on different aspects in the control message and the data message.

In a control message, the information field always consists of 16 bits, and each bit has a specific meaning, as shown in FIG. 11(B). That is, the first 8 bits b1 to b18 represent the address of the own station. Of the following 8 bits, the first bit b2□ is a connection request, and the second bit b22 is a release request (a connection disconnection request).
, the fifth bit b25 indicates connection completion, and the sixth bit b26
indicates completion of release, and the seventh bit b27 indicates busy (communicating with another station). In the information field, enter your own station (
Since the address of the sending station (transmitting station) is included, the other station (receiving station) can know the position (number) of the time slot to receive data in accordance with the sending station's empty address.

Such a control message is U I (Unnumbered
d ln-formatlon) frame, it will hereinafter be simply referred to as an Ul command or UI response.

In a data telegram, the information field contains the data to be transmitted. Therefore, the number of bits in this field varies depending on the length of the data.

The check field is set with the result of arithmetic calculation by the transmitting side of the numerical values represented by all the binary bits in the frame using the CRC method for error checking. On the receiving side, the same calculation is performed on the own station and compared with the value of the sent inspection field to check whether a transmission error or the like has occurred.

” The control signal D is 10 bits (actually 8 bits) including the start pit and stop bit.
Consists of bits). On the other hand, the control message is the 11th
As can be seen from the figure, it is composed of 64 bits. 1st
Since the time slot sequence is repeated with a period T as shown in Figure 2, the control telegram consists of eight control signals. 1 to Dc8, and by continuously transmitting these over 8 cycles, one control message is transmitted and received. That is, the first control signal. 1
is formed by adding a start bit ST and a stop bit SP after the 8-bit data of the start flag field. At time slot TS of the next cycle, the 8-bit address data of the address field and bits ST and SP are control signals. 2
Sent as . From here on, do the same thing, and do the steps 3 to 8.
The control signal sent in the time slot TS of the th period. 3 to Dc8, various data in the control message are edited in 8-bit units.

In exactly the same way, a data telegram consists of 6 or more consecutive data signals, (i-1 to n, j=1 to m, m≧J 6 ) is divided into 8 bits each and transmitted. Since the number of bits of the information field is determined according to the data length to be transmitted, the number of data signals D1j also changes accordingly.

(3,5) Connection and Communication Processing In FIG. 5 or 6, gates 3 and 4 are connected to gate control signals G for interconnection of two communicating devices.
3 and G4, respectively. These gates 3 and 4 are controlled in the same way in all devices.

In order to receive the Ul command - standard No. 27 - transmitted from any other device, the gate 3 synchronizes with the time slot TS in each period.
It is only open during This means that the time and slot TS are stored in the register 43 in FIG.

The setting value corresponding to the count value of the counter 59 representing CP
This is realized by presetting by U20. UI commands (a series of control signals D
), it is stored in the receive buffer 33 through the straight-curve conversion circuit 25 and the open gate 3.

The CPU 20 receives the Ul stored in this reception buffer 33.
After decoding the command, if the command is addressed to your own station, the necessary UI response (a series of control signals D
) is sent. UI for your station to call other devices
When sending commands or responding to received UI commands with Ul responses, edit these commands or responses in the sending buffer 34,
Gate 4 at the same timing as time slot TS
is opened and a control signal D constituting a two-edited message is sent every cycle. This signal is converted into a serial signal by the parallel-to-serial conversion circuit 24 and appears on the transmission line. The opening of gate 4 is also carried out in the same manner as in the double series.

The time slot TS is a control signal D sent from two or more devices for common use by all devices 1 to n.
may overlap (collide). For this,
Collision detection is performed as described below, and measures are taken in the event of a collision.

When two devices are connected to each other by communicating UI commands and UI responses thereto.

Move on to sending and receiving data. At this time, gate control signal G5. G6 controls the opening and closing of gates 5 and 6. The opening and closing control operations of the gates 5, 6 are carried out in exactly the same way in all devices 1-n. That is, this is realized by setting predetermined set values to the registers 45 (not shown) and 46.

As mentioned above, in the transmission and reception of data between device i, time slot TS.

and TSk are fixed. When device i transmits data to device k, the CPU 20 of device i uses the transmission buffer 3
6, the edited transmission data telegram is stored, and the gate controller is opened only during this time slot TS in synchronization with time slot TS.

The data signals constituting the data telegram edited for each cycle are sent out to the line via the parallel-to-serial conversion circuit 24. In device k, the gate 5 is also opened in synchronization with the time roller TS, and the data signal sent from device i on the transmission line is taken into the receiving buffer 35 via the direct curve conversion path 25.

The connection process and data transmission/reception process will be generally described with reference to FIGS. 13 and 14.

FIG. 13 shows the flow of the operation of the device on the sending side (referred to as device i), and FIG. 14 shows the procedure of the operation of the device on the receiving side (referred to as device k).

Assuming that device i has data to send to device k (step 121), device i sets the address for the device in the address field and the first 8 in the information field.
The address of own station i is written in the first bit of the following 8 bits.
Edit the UI command in which "connection request" (set to 1) is set in bit b21, and send this as a control signal D at the timing of time slot TS (step 122).

All other devices are watching control signal D with gate 3 open in time slot TS. A control signal D in which device k includes the address of its own station (device k) in the address field and has a "connection request" bit.
When the mobile station receives (step 141), it checks whether the local station is currently communicating with another device (busy) (step 142). If it is not busy, enter the address of the other station i in the middle address field and the address of your own station in the first 8 bits of the information field.

5th bit b25 of the following 8 bits indicates “Connection Complete”
(set to 1) are edited and sent out at the timing of time slot TS (step 143). If busy, the 7th
A UN response with bit b27 set to 1 is sent (step 147).

After sending the above-mentioned UI command, device i opens gate 3 in synchronization with time thrower l-T S and waits for an Ul response from device k. When device l receives an Ul response in which the address of device i is set in the address field, device l decodes the response and writes the address of the other station in the first 8 bits of the information field and the 5th of the following 8 bits. It is determined whether the bit b25 is set to 1 or the seventh bit is set to 1 (steps 124 and 125).

When the Ul response from device k indicates "connection complete," gate 6 is opened in synchronization with the time slot TS assigned to the own station, that is, device i, and necessary data is transmitted.

The device that sent the UIl response "Connection Complete" opens the gate 5 in synchronization with time slot TS in preparation for communication with device i, and waits for the arrival of a data message from device i.

In this way, the transmission of data from device i to device takes place in time slot TS (steps 128, 144).

At this time, if there is data to be sent from device k to device i, this data can be transmitted using time slot T S k after connection processing is performed using the control signal.

When device i finishes sending all the data to device k (step 127), device i sends the device address (address field), the address of own station i, and the "release request" (second The Ul command with bits b, ) (information field) set is sent at the timing of time slot TS (step 128).

When the device receives this "release request JUI command (
Step 145), r release complete” (6th bit b
At step 14El), the process is completed. In device i, device k
Upon receiving this UIl response from (step 12
9), the process ends in the same way.

When device i receives a "busy JUI response" from device k (step 124), it proceeds to the other party busy process (step 130). At this time.

At this point, device i cannot communicate with the device.

In the case of data communication, the other party's busy processing refers to the process of issuing a connection request again after a certain period of time.In a two-telephone system, the other party's busy processing refers to the process of issuing a connection request again after a certain period of time. Refers to the process of issuing.

When the system according to the present invention is applied to a local telephone switching system, the PCM
Coded audio data is sent and received between devices. In telephone switching systems, it is impossible to retain voice data in buffers or the like for long periods of time, so rapid communication is necessary.

For example, if one period T is set to 125 μs and each time slot is set to 10.417 μs, this system can be applied to 10 telephones.

Audio is sampled every 8KHz.

1/8000=125 μs, and it is sufficient to send and receive one sampling of data every 125 μs. Of course, since audio can be sent from device i to device in time-slot TSi and from device k to device i in time-slot TSk.

Needless to say, two-way communication is possible.

-1- In the embodiment described above, all of the 0 devices have a synchronization signal generation function, so even if the device that is generating the synchronization signal goes down, another device will generate the synchronization signal in its place. communication in the system can continue.

Furthermore, in the system according to the present invention, it is also possible for one device to send data to multiple devices simultaneously. For example, if a global address in HDLC is set in the address field, one device can connect to all other devices. When one device connects to an arbitrary number of devices, the one device only needs to issue a connection request to each device.

(3,6) Collision detection FIG. 15 shows an example of a collision detection circuit. The signal sent from the device is converted into a serial signal by the parallel-to-serial conversion circuit 24, and then sent to the transmission line via the line driver 61. The signal on the transmission line is received by line receiver 82 and then input to straight-curve conversion circuit 25 .

The input side of the line driver 61 (point A) and the output side of the line receiver 62 (point B) are exclusive OR circuit EORB.
Connected to 3. The output side CC point of the EOR 63 is connected to a differentiating circuit 64 and also to a data input terminal of a DT flip-flop 66. The differentiating circuit 64 detects the rising edge of the input signal, and the counter 65 is reset by the detection signal. counter 65
is, for example, a decimal counter, and starts counting from zero in response to a reset signal. A signal that exceeds the count output of the counter 65 (count value C, for example 5) is sent to the timing input terminal T of the DT flip-flop 66. It is assumed that the clock pulse given to the counter 65 has a speed ten times the one bit length of the signal. The output signal Q of the DT flip-flop 06 becomes the collision detection signal.

FIG. 16 shows the operation of this collision detection circuit.
A) shows a case where no collision occurs, and (B) shows a case where a signal collision occurs.

Referring to FIG. 16(A), the signals sent from the device to the transmission line via line driver 61 are as follows.

Also input to line receiver 62. therefore.

Signals with substantially the same waveform appear at points A and B, but these signals are out of phase by the delay time td of the line driver 61 and line receiver 62. This phase shift is detected by the EOR 63, and the rising edge of the detection signal detected by the differentiating circuit 64 resets the counter 65, so that the counter 65 starts counting. When the count value of the counter θ5 reaches CN, a pulse is applied to the timing input terminal T of the DT flip-flop 66. However, at this point, the 0 point signal (data input D) is at low level, so the DT flip-flop 66 is not set.

In FIG. 16(B), the signal (A
When signals transmitted from other devices are propagating on the transmission line in addition to the point signal), a signal appears on the transmission line in the form of a heavy electric current of these signals, and a signal that is slightly delayed from this appears on the transmission line. A signal waveform appears at point B. Therefore, a wide signal may appear in the FOR operation result (0 point) between the signal at point A and the signal at point B. If the output of the counter 65 is applied to the DT flip-flop 66 while the 0 point signal is at high level, the DT flip-flop 66 is set, so that a signal collision is detected.

Detecting a collision in this way means that another device is transmitting, so that device waits until the channel is empty.

[Brief explanation of drawings]

FIGS. 1A and 1B are block diagrams each schematically showing an example of the overall configuration of a data transmission system in an embodiment of the present invention. FIG. 2 is a time chart showing the timing relationship of the entire system. FIG. 3 shows the timing of signal transmission and reception between two devices and the bit structure of each signal. FIG. 4 shows the bit structure of the synchronization signal. FIG. 5 and FIG. 6 are block diagrams showing examples of the hardware configuration of the device, respectively. FIG. 7 is a block diagram showing an example of a specific configuration of the time slot gate signal generation circuit, and FIG. 8 is a time chart showing its operation. 9 and 10 are flow charts showing the synchronization establishment process, with FIG. 9 showing the operation of the device that sends the synchronization signal, and FIG. 10 showing the operation of the other devices, respectively. FIGS. 11(A) and 11(B) i;1 HDLc message format. FIG. 12 shows how messages are sent and received over a plurality of cycles. Fig. 13 and Fig. 14 show the connection and communication processing between two devices, and Fig. 13 shows the operation of the calling side.
FIG. 14 shows the operations on the receiving side. FIG. 15 is a block diagram showing an example of a specific configuration of the collision detection circuit, and FIGS. 16(A) and (B) are waveform diagrams showing its operation. 20...CPU. 23...Time slot gate signal generation circuit. that's all

Claims (2)

[Claims] (1) Consisting of a plurality of devices connected by a transmitting/receiving transmission line and a means for transmitting a synchronization signal at a fixed cycle, each device transmits the number of devices within the above fixed cycle based on the synchronization signal. A plurality of time slots divided by a number greater than means for creating such time slots, one of the slots for synchronization signals, the other for control signal transmission and reception, and the remaining time slots for data transmission and reception, synchronized with the synchronization signal time slots; a first gate that is opened in synchronization with a time slot for transmitting and receiving control signals; a third gate that is opened in synchronization with a time slot for transmitting and receiving data that corresponds to the device; A data transmission system between a plurality of devices, comprising means for transmitting and receiving the necessary signals when the gate is opened. (2) The means for transmitting the synchronization signal is included in one device, and the time slot creation means of the one device creates a time slot based on the synchronization signal to be transmitted; The device's time slot creation means are:
The method according to claim (1), wherein a time slot is created based on the received synchronization signal by receiving a synchronization signal transmitted from one device. data transmission system.