JPS62152221A - 'and' circuit - Google Patents

'and' circuit

Info

Publication number
JPS62152221A
JPS62152221A JP60292095A JP29209585A JPS62152221A JP S62152221 A JPS62152221 A JP S62152221A JP 60292095 A JP60292095 A JP 60292095A JP 29209585 A JP29209585 A JP 29209585A JP S62152221 A JPS62152221 A JP S62152221A
Authority
JP
Japan
Prior art keywords
transistor
light
light emitting
receiving element
emitting element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60292095A
Other languages
Japanese (ja)
Inventor
Takashi Enomoto
榎本 高
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyosan Electric Manufacturing Co Ltd
Original Assignee
Kyosan Electric Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyosan Electric Manufacturing Co Ltd filed Critical Kyosan Electric Manufacturing Co Ltd
Priority to JP60292095A priority Critical patent/JPS62152221A/en
Publication of JPS62152221A publication Critical patent/JPS62152221A/en
Pending legal-status Critical Current

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  • Logic Circuits (AREA)

Abstract

PURPOSE:To obtain an 'and' circuit where the mutual division between inputs is separated in a direct current way by turning on and off respective transistors in accordance with a clock pulse and by extracting this with a linking means only when the first and second logical input signals are respectively and simultaneously impressed. CONSTITUTION:To an input IN, a clock pulse CK of the frequency sufficiently higher than the changing period of respective logical input signals is given, the light emitting diode of a photocoupler 1 used as the first light emitting element and light receiving element is driven by the clock pulse CK and emits the light intermittently in accordance with this. When an input terminal A1 is a positive pole, the same terminal G1 is a negative pole and as the electric power source to these, the first logical input signal is impressed, a transistor Q1 is turned on and off. To the collector of the transistor Q1, a PC2 is inserted as the second light emitting element and light receiving element, to the division between input terminals A2 and G2, the second logical input signal is impressed, a transistor Q2 at the next stage is turned on and off. In the same way, (n) stages are connected and from the optional output, an 'and' output signal is obtained.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、障害音生じた場合、出力償号が必ず特足状態
となるフェールセーフ性を備えた論理積回路に関するも
のである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an AND circuit having a fail-safe property in which the output signal is always in a special state when an interference sound occurs.

[従来の技術〕 交通用制御装置等においてに、高侶頓性と共に安全性全
要求されており、障害音生じた場合には、出力イキ号が
必ず%足状塵となるフェールセーフ性金備え友論理回路
が用いられ、従来は、第2図および第3図に示すものが
論理積回路として採用きれている。
[Prior art] In traffic control devices, etc., safety as well as high stability are required, and in the event of an interference noise, a fail-safe feature is provided in which the output signal will always become a foot-like dust. Conventionally, the logic circuits shown in FIGS. 2 and 3 have been used as AND circuits.

すなわち、第2図は、システリシス特性を有する変成器
Tsを用いる場合でめり、入力巻線nl。
That is, FIG. 2 shows a case where a transformer Ts having systeresis characteristics is used, and the input winding nl.

n!へ論理入力信号を与え、出力巻線n。から論理積出
力信号を得ている。
n! provides a logic input signal to the output winding n. The AND output signal is obtained from

でた、第3図においては、抵抗器R1〜R4、コンデン
サC1、C2お工びトランジスタQa1Qbに、l:り
自走マルチバイブレータ全構成し、電源F!:1、C2
として各々へ論理人力信号全印加し、電源”’I 、E
zの同時印力口による発振出力EOを取り出し、これを
論理演出力信号として用いるものとなっている。
In Fig. 3, a free-running multivibrator is constructed with resistors R1 to R4, capacitors C1 and C2, and transistors Qa1Qb, and a power supply F! :1, C2
Apply all logical human power signals to each as power supply ``I, E
The oscillation output EO from the simultaneous input port of z is taken out and used as a logical performance signal.

〔発明が解決しよりとする問題点〕[Problems that the invention helps solve]

しかし、第2図お工び第3図においては、論理入力数の
増加かいず扛も困難でるり、特に第2因のものは高価と
なる一方、第3図のものは、各論理入力信号間を直流的
に分離できず、回路設計上の制約を生ずると共に、論理
条件に応じて発振開始′IItEj:が不安定になる等
の問題を生じている。
However, in the case of Fig. 2 and Fig. 3, it is difficult to increase or eliminate the number of logic inputs, and the second factor is especially expensive, while the one in Fig. It is not possible to separate the two in terms of direct current, which creates constraints on circuit design, and also causes problems such as the oscillation start 'IItEj: becoming unstable depending on logic conditions.

c問題点?解決するための+段〕 前述の問題全解決するため、本発明はりぎの手段に工f
)構成するものとなっている。
c Problem? + step to solve] In order to solve all the above-mentioned problems, the method of the present invention is improved.
).

すなわち、論理入力信号の変化周期よりも十分高い周波
数のクロックパルスにニク駆動される第1の発光素子と
、この第1の発光素子からの発光を受光する第1の受光
素子と、この第1の受光素子に工9オン、オフが制御さ
れかつ電源として第1の論理入力信号が印加される第1
のトランジスタと、この第1のトランジスタのコレクタ
・エミッタ間へ通ずる電流により駆動される第2の発光
素子と、この第2の発光素子からの発光を受光する第2
の受光素子と、この第2の受光素子に、l:9オン、オ
フが制御されかつ電源として第2の論理入力信号が印加
される第2のトランジスタと、この第2のトランジスタ
のコレクターエミッタ間へ通ずる電流の変化を論理積信
号として送出する結合手段とを少くとも備えたものでる
る。
That is, a first light-emitting element driven by a clock pulse having a frequency sufficiently higher than the change period of the logic input signal, a first light-receiving element that receives light emitted from this first light-emitting element, and a first light-receiving element that receives light emitted from this first light-emitting element. The first logic input signal is applied as a power source to the light receiving element of
a second light emitting element driven by a current flowing between the collector and emitter of the first transistor, and a second light emitting element that receives light emitted from the second light emitting element.
between the light-receiving element of the second light-receiving element, a second transistor whose l:9 on/off is controlled and a second logic input signal is applied as a power supply to the second light-receiving element, and the collector-emitter of the second transistor. and coupling means for transmitting changes in the current flowing through the circuit as an AND signal.

〔作用〕[Effect]

したがって、第1お工び第2の各トランジスタに対し、
第1おLび第2の各論理入力信号が同時に印加されてい
るときにのみ、クロックパルスに応じて各トランジスタ
かオン、オフを行なう友め、第2のトランジスタのコレ
クタ・エミッタ間へ通ずる電流がクロックパルスと同一
の変化全土するものとなり、これを結合手段により抽W
丁れば論理積信号が得られる。
Therefore, for each of the first and second transistors,
Current flows between the collector and emitter of the second transistor, which turns each transistor on and off in response to a clock pulse only when the first and second logic input signals are applied simultaneously. has the same change as the clock pulse, and this can be extracted by the coupling means.
If you divide them, you will get an AND signal.

〔実施例〕〔Example〕

以下、実施例を示す第1図の回路図によって本発明の詳
細な説明する。
Hereinafter, the present invention will be explained in detail with reference to the circuit diagram of FIG. 1 showing an embodiment.

同図においては、入力INに対し、各論理入力信号の変
化周期工9も十分に高い周波数のクロックパルスCKが
与えられており、第1の発光素子および受光素子として
用いるフォトカブラ(以下、PC) 1  の発光ダイ
オードがクロックパルスCKに1り駆動され、これに応
じ1Wr続的に発光すると、この発光vi−PC1の受
光トランジスタが受光してオン、オフ全行なうものとな
り、入力端子A1全正極、開端子Gl金負極とし、これ
らへ電源として第1の論理入力信号を印加すれば、抵抗
器R++’を介する第1のトランジスタQ1への順方向
パイアスカpci  の受光トランジスタにより断続し
て制御され、トランジスタQ、がオン、オフを行ない、
これにし友がって抵抗器RI2 k介しトランンスタQ
1のコレクタ・エミッタ間電流が通ずるものとなる。
In the figure, a clock pulse CK of a sufficiently high frequency is also given to the input IN to the change periodic circuit 9 of each logic input signal, and a photocoupler (hereinafter referred to as PC) used as the first light emitting element and light receiving element ) 1 is driven by the clock pulse CK and emits light of 1 Wr continuously in response to this, the light receiving transistor of the light emitting vi-PC1 receives the light and turns on and off, and all positive terminals of the input terminal A1 , the open terminal Gl is the gold negative electrode, and if the first logic input signal is applied as a power supply to these, the light receiving transistor of the forward direction bias scan pci to the first transistor Q1 via the resistor R++' is intermittently controlled, Transistor Q turns on and off,
Accordingly, the transistor Q is connected through the resistor RI2k.
1 collector-emitter current flows.

i*、rう/ジスタQ!のコレクタにぼ、第2の発光素
子お工び受光素子として用いるPC20発光ダイオード
が順方向として挿入されており、これがトランジスタQ
+ のコレクタta々通に応りが受光してオン、オフを
行なう窺め、入力端子At 、G2間へ前述と同様に第
2の論理入力信号を印加すれば、抵抗器Rzt t”介
する第2のトランジスタQ1への順方向バイアスがPC
2の受光トランジスタにより断続して制御され、トラン
ジスタQ2がオン、オフを行ない、これVChじてコレ
クタ・エミッタ間電流が通じ、抵抗器Rtx k介する
コレクタを流によ!JPC30発光ダイオードが駆動さ
れるものとなり、PCB  の受光トランジスタにエリ
、抵抗器Rslを介するトランジスタQs。
i*,ru/Jista Q! A PC20 light emitting diode used as a second light emitting element and a light receiving element is inserted into the collector of the transistor Q.
+ The collector ta receives light and turns on and off.If the second logic input signal is applied between the input terminals At and G2 in the same way as described above, the first The forward bias to transistor Q1 of 2 is PC
The transistor Q2 is intermittently controlled by the light-receiving transistor No. 2, and the transistor Q2 turns on and off, and a collector-emitter current flows through the collector through the resistor Rtxk. The JPC30 light emitting diode is driven by a light receiving transistor on the PCB and a transistor Qs via a resistor Rsl.

順方向バイアスが制御され、トランジスタQsもオン、
オフ全行ない、入力画子A3、Gs間へ上述と同様に第
3の論理入力信号を印加子れば、トランジスタQ3のコ
レクタ・エミッタ間電流が通ずる。
Forward bias is controlled, transistor Qs is also turned on,
When the transistor Q3 is completely turned off and the third logic input signal is applied between the input picture elements A3 and Gs in the same manner as described above, a current flows between the collector and emitter of the transistor Q3.

以下、同様に第nのトランジスタQnfでか構成されて
おり、入力端子An、GnK’!で各論理入力信号が同
時に印加されている条件において、トランジスタQnヘ
コレクタ・エミッタ間電流がるものとなるため、この変
化を抵抗器Rn2を介するトランジスタQnのコレクタ
から結合手段としてのコンデンサCoにより抽出し、出
力OU、へ送出すると、これが各論理入力(i号の論理
積信号となる、。
Similarly, the n-th transistor Qnf is configured below, and the input terminals An, GnK'! Under the condition that each logic input signal is applied simultaneously, a current flows between the collector and emitter of the transistor Qn, so this change is extracted from the collector of the transistor Qn via the resistor Rn2 by the capacitor Co serving as a coupling means. , output OU, this becomes the AND signal of each logical input (i).

1之、更に同様の回路を縦続接続する場合等には、トラ
ンジスタQ のコレクタへ挿入しりPC・mkta合手
段として用い、これの受光トランジスタから出力OU2
へ断続出力を送出するものとなっている。
1. When further cascading similar circuits, etc., insert it into the collector of the transistor Q and use it as a PC/mkta combining means, and output the output OU2 from the light-receiving transistor.
It is designed to send intermittent output to.

したがって、出力OUIの信号を整流すれば直流の論理
積信号が得られると共に、入力IN 乃至出力OU+−
fたはOU2  のいずれかに障害を生ずnば、必ず出
力OU、の信号が/P!!滅すると共に、出力OU、 
がオンまたはオフの非断続状態となり、障害の発生時に
出力信号の状態が不特定とならず、確実なフエールセ〜
)性が実現する。
Therefore, by rectifying the output OUI signal, a DC AND signal can be obtained, and the input signal from the input IN to the output OU+-
If a fault occurs in either f or OU2, the signal at output OU will always be /P! ! At the same time, the output OU,
is in a non-intermittent state of on or off, and the state of the output signal does not become unspecified when a fault occurs, ensuring reliable failsafe control.
) sex is realized.

−17j、PCI  およびトランジスタQ1による構
成全基本とし、必要段数を縦続接続することにより、任
意な入力数の論理積回路が得られると共に、各入力端子
AI 、G I〜AyIXGn間が直流的に分離されて
おり、回路設計上の自由度が増大する。
-17j, PCI and transistor Q1 are all basic configurations, and by cascading the required number of stages, an AND circuit with an arbitrary number of inputs can be obtained, and each input terminal AI, GI~AyIXGn can be separated in terms of direct current. This increases the degree of freedom in circuit design.

なお、第1図の場合に1名段が交互にオン、オフ全行な
い、丁べてが同時にオン状態とならないため、各入力端
子AIXGI〜Afi、GHへ同相の雑音が印加されて
も、出力OU、 、OU2へ刀口算きれて送出されない
と共に、不要な発振等音生ずるおそれが完全に排除され
る。
In addition, in the case of Fig. 1, one stage is alternately turned on and off, and all rows are not turned on at the same time, so even if in-phase noise is applied to each input terminal AIXGI to Afi, GH, the output Not only is the signal not sent out to OU, , OU2, but also the possibility of unnecessary oscillations being generated is completely eliminated.

fCソし、PCI〜mの代りに、他の発7IC素子と受
光素子との組み合せ全屈いてもよく、受光素子の挿入部
位は、トランジスタのオン、オフを制御できる部位でめ
れば工く、発光素子の挿入部位全トランジスタのエミッ
タ側としても[司様でるり、結合手段としては、変成器
等を用いることも任意でるると共に、最少限の構成とじ
てに、PCI、2、トランジスタQ+、Qz  および
結合手段かめれば工い等、程々の変形が自任である。
fC, instead of PCI~m, a combination of other emitter 7 IC elements and a light receiving element may be used, and the insertion site of the light receiving element can be installed at a location where the on/off of the transistor can be controlled. , as the emitter side of all the transistors at the insertion site of the light emitting element [Ruri Tsukasa, it is optional to use a transformer etc. as a coupling means, and as a minimum configuration, PCI, 2, transistor Q+ , Qz, and the construction of the coupling means, etc., may be modified to a certain degree.

〔発明の効果〕〔Effect of the invention〕

以上の説明にニジ明らかなとお9本発明に工れば、簡単
かつ安価な構成に19、完全なフェールセーフ性および
高信頼性を有し、かつ、任意な入力数が得られると共に
、入力相互間が直流的に分離された論理積回路が実現し
、集積回路化も容易でめる几め、各種の高信頼性および
フェールセーフ性を要する用途において顕著な効果が得
られる。
As is clear from the above description, if the present invention is implemented, it will be possible to have a simple and inexpensive configuration, complete fail-safe performance and high reliability, obtain an arbitrary number of inputs, and have mutual input interaction. The present invention realizes an AND circuit in which the circuits are separated in terms of direct current, and can be easily integrated into an integrated circuit, providing remarkable effects in various applications requiring high reliability and fail-safe performance.

【図面の簡単な説明】[Brief explanation of drawings]

第1図に本発明の実施例を示す回路図、第2図および第
3図に従来例の回路図でるる。 1〜3.m+1=Pc(フォトカプラ)、CK・・・・
クロックパルス、Q1〜Qn  ・・・・トランジスタ
、A、−Afi、G、〜Gn ・・・拳入力端子、Co
  ・・・・コンデンサ。
FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIGS. 2 and 3 are circuit diagrams of a conventional example. 1-3. m+1=Pc (photocoupler), CK...
Clock pulse, Q1~Qn...Transistor, A, -Afi, G, ~Gn...Fist input terminal, Co
...Capacitor.

Claims (1)

【特許請求の範囲】[Claims] 論理入力信号の変化周期よりも十分高い周波数のクロッ
クパルスにより駆動される第1の発光素子と、該第1の
発光素子からの発光を受光する第1の受光素子と、該第
1の受光素子によりオン、オフが制御されかつ電源とし
て第1の論理入力信号が印加される第1のトランジスタ
と、該第1のトランジスタのコレクタ・エミッタ間へ通
ずる電流により駆動される第2の発光素子と、該第2の
発光素子からの発光を受光する第2の受光素子と、該第
2の受光素子によりオン、オフが制御されかつ電源とし
て第2の論理入力信号が印加される第2のトランジスタ
と、該第2のトランジスタのコレクタ・エミッタ間へ通
ずる電流の変化を論理積信号として送出する結合手段と
を少くとも備えたことを特徴とする論理積回路。
A first light emitting element driven by a clock pulse having a frequency sufficiently higher than a change period of a logic input signal, a first light receiving element that receives light emission from the first light emitting element, and the first light receiving element. a first transistor whose ON/OFF state is controlled by a transistor and to which a first logic input signal is applied as a power supply; a second light emitting element driven by a current flowing between the collector and emitter of the first transistor; a second light-receiving element that receives light emitted from the second light-emitting element; a second transistor that is turned on and off by the second light-receiving element and to which a second logic input signal is applied as a power source; , and coupling means for transmitting a change in the current flowing between the collector and emitter of the second transistor as an AND signal.
JP60292095A 1985-12-26 1985-12-26 'and' circuit Pending JPS62152221A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60292095A JPS62152221A (en) 1985-12-26 1985-12-26 'and' circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60292095A JPS62152221A (en) 1985-12-26 1985-12-26 'and' circuit

Publications (1)

Publication Number Publication Date
JPS62152221A true JPS62152221A (en) 1987-07-07

Family

ID=17777478

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60292095A Pending JPS62152221A (en) 1985-12-26 1985-12-26 'and' circuit

Country Status (1)

Country Link
JP (1) JPS62152221A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5428536A (en) * 1977-08-04 1979-03-03 Mitsubishi Electric Corp Interface circuit
JPS5516501A (en) * 1978-06-14 1980-02-05 Nippon Signal Co Ltd:The Fail-safe logic circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5428536A (en) * 1977-08-04 1979-03-03 Mitsubishi Electric Corp Interface circuit
JPS5516501A (en) * 1978-06-14 1980-02-05 Nippon Signal Co Ltd:The Fail-safe logic circuit

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