JPS62152169A - Vertical type semiconductor device - Google Patents

Vertical type semiconductor device

Info

Publication number
JPS62152169A
JPS62152169A JP60291855A JP29185585A JPS62152169A JP S62152169 A JPS62152169 A JP S62152169A JP 60291855 A JP60291855 A JP 60291855A JP 29185585 A JP29185585 A JP 29185585A JP S62152169 A JPS62152169 A JP S62152169A
Authority
JP
Japan
Prior art keywords
film
semiconductor
bonding pad
gate
source
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60291855A
Other languages
Japanese (ja)
Inventor
Yoshitaka Sasaki
芳高 佐々木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TDK Corp
Original Assignee
TDK Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by TDK Corp filed Critical TDK Corp
Priority to JP60291855A priority Critical patent/JPS62152169A/en
Publication of JPS62152169A publication Critical patent/JPS62152169A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0856—Source regions
    • H01L29/0869—Shape
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To increase channel width while lowering ON resistance by forming an independent insular semiconductor or conductor film pattern on the lower side of a bonding pad. CONSTITUTION:In a source bonding pad section, a source bonding pad 12 is shaped integrally with an Al electrode film 9, and a lead wire 13 for a source electrode is fused onto the bonding pad 12. A cell is also shaped to the lower side of the pad 12 in the same manner as other sections. On the other hand, the film 9 is ohmic-connected to semiconductor layers 4 and 8 through insulating films 5d and source-electrode leading-out opening sections in the cells formed in a CVD-SiO2 film. Accordingly, active regions are also formed on the lower side of the pad 12, thus lengthening channel width, then acquiring large currents while lowering ON resistance.

Description

【発明の詳細な説明】 （産業上の利用分野） 本発明はスイッチングあるいは増幅を目的とした縦形半
導体装置に関するものであり、特に微細化および高性能
化の技術に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a vertical semiconductor device for the purpose of switching or amplification, and particularly relates to techniques for miniaturization and high performance.

（従来の技術） ＭＩＳ型半導体装置のうち、特にＭＯＳ　ＦＥＴは低耐
圧、低電力デバイスと従来考えられていたが、最近の半
導体製造技術あるいは回路設計技術等の発展に伴い、高
耐圧、大電力設計が可能となり、現在ではパワーデバイ
スとしてその地位を確保するに至っている。(Prior art) Among MIS type semiconductor devices, MOS FETs in particular were traditionally thought to be low voltage and low power devices, but with recent developments in semiconductor manufacturing technology and circuit design technology, they have become It has become possible to design it, and it has now secured its place as a power device.

かかる高耐圧パワーＭＯＳ　ＦＥＴの代表的なものとし
て■オフセットゲート構造、■Ｖ−Ｇｒｏｏｖｅあるい
はＵ−Ｇｒｏｏｖｅ構造、■ＤＳＡ（Ｄｉｆｆｕｓｉｏ
ｎ　５ｅｌｆ−Ａ’ｌｉｇｎｍｅｎｔ）構造等が知られ
ているが、このうち製造技術、高性能化の点で有利な従
来のＤＳＡ　ｈｌ造のパワー曳、（Ｏ５ＦＥＴ　　（以
下Ｏ３Ａ　ＭＯＳ　ＦＥＴと称する）の電極形成後の平
面図と、この平面図におけるＡ−Ａ線方向の断面構造図
を第５図（ａ）および（ｂ）に示す。ただし、第５図（
ａ）ではソース電極は省いである。Typical examples of such high-voltage power MOS FETs include: ■offset gate structure, ■V-Groove or U-Groove structure, and ■DSA (Diffusio
n5elf-A'lignment) structure etc. are known, but among these, the conventional DSA HL structure power puller (O5FET (hereinafter referred to as O3A MOS FET) structure, which is advantageous in terms of manufacturing technology and high performance) is known. A plan view after formation and a cross-sectional structural view taken along line A-A in this plan view are shown in FIGS. 5(a) and 5(b).
In a), the source electrode is omitted.

ＤＳ八へＪＯ５ＦＥＴは二重拡散によりチャンネルを形
成するもので、ゲート酸化膜５ａを介して形成された格
子状のゲート多結晶シリコン膜６に囲まれた同一の拡散
窓を介してチャンネル領域を形成するための不純物拡散
（ｐ型半導体層４）と、ソース領域を形成するための不
純物拡散（ｎ”型半導体層８）とを行っているのが特徴
である。チャンネル長さはｐ型半導体層４とｎ°型型溝
導体層８の拡散深さの差で決まるので数ミクロン以下と
極めて短く形成できる。絶縁膜５ｄ上に形成したソース
電極９はソース領域を形成するｎ゛型型溝導体層８チャ
ンネル領域を形成するｐ型半導体層４（あるいはｐ゛型
型溝導体層３との両方にオーミック接触している。ゲー
ト電極形状は多くの島領域を集合した格子状のマルチゲ
ートタイプと、メツシュ状に形成されているメツシュゲ
ートタイプとが−ＩｉｌＱ的であるが、ここてはマルチ
ゲートタイプのものを示す。ｎ゛゛半導体基板１がドレ
イン領域であり、その上にｎ型エピクキシャル成長層２
を堆積させたｎオンｎ＋構造となっている。ドレイン電
極は図示していないがチップ裏面に形成されており、ゲ
ート・ソース間に正の電圧を加えてチャンネルをオンさ
せると電流は基板１より縦方向に流れ、チャンネル領域
４を通ってソース領域８に流れ込む。なお、第５図（ａ
）における破線は各セルを構成する多結晶シリコン膜パ
ターン６の開口の輪郭を示すものである。DS8JO5FET forms a channel by double diffusion, and the channel region is formed through the same diffusion window surrounded by a lattice-shaped gate polycrystalline silicon film 6 formed through a gate oxide film 5a. It is characterized by performing impurity diffusion (p-type semiconductor layer 4) to form a source region and impurity diffusion (n'' type semiconductor layer 8) to form a source region. The source electrode 9 formed on the insulating film 5d is determined by the difference between the diffusion depth of the n° type trench conductor layer 8 and the n° type trench conductor layer 8, so it can be formed extremely short, several microns or less. Layer 8 It is in ohmic contact with both the p-type semiconductor layer 4 (or the p-type groove conductor layer 3) forming the channel region.The gate electrode shape is a multi-gate type in the form of a lattice made up of many island regions. , the mesh gate type formed in a mesh shape is -IilQ, but here a multi-gate type is shown. layer 2
It has an n-on n+ structure. A drain electrode (not shown) is formed on the back surface of the chip, and when a positive voltage is applied between the gate and source to turn on the channel, current flows vertically from the substrate 1, passing through the channel region 4 and reaching the source region. Flows into 8. In addition, Fig. 5 (a
) indicates the outline of the opening in the polycrystalline silicon film pattern 6 constituting each cell.

一般的にＭＯＳ　ＦＢＴは少数キャリヤの蓄積がないた
め高速スイッチングが可能でドレイン電流が負の温度計
数を持つため熱的安定性が高い等大電力用素子として長
所を持っている反面、バイポーラ型トランジスタと比較
した場合多数キャリア素子であるため高耐圧化の相反関
係が著しく、高耐圧化に必要な基板抵抗層がそのまま飽
和電圧の上昇に結びつき、同一チップ面積ではオン抵抗
が太きくなるという欠点があった。かかる問題を解決す
るためにはＦＥＴの電力通路の抵抗、特にドレイン抵抗
の低減を図ることが必要である。換言すれば、いかにド
レインの面積効率を挙げるかということであり、このた
めには微細加工技術を駆使して最良パターン設計を行わ
なければならない。これらを満足させる構造として一般
的にはＤＳＡ　ＭＯＳ　ＦＥＴが採用されている。In general, MOS FBTs have the advantage of high-speed switching because there is no accumulation of minority carriers, and high thermal stability because the drain current has a negative temperature coefficient. When compared with the majority carrier element, there is a significant trade-off between increasing the withstand voltage, and the substrate resistance layer necessary for increasing the withstand voltage directly leads to an increase in the saturation voltage, resulting in a higher on-resistance for the same chip area. there were. In order to solve this problem, it is necessary to reduce the resistance of the power path of the FET, especially the drain resistance. In other words, the question is how to increase the area efficiency of the drain, and for this purpose, it is necessary to design the best pattern by making full use of microfabrication technology. A DSA MOS FET is generally employed as a structure that satisfies these requirements.

しかしながら従来のＤＳＡ　ＭＯＳ　ＦＥＴの構造は必
ずしも最適なものとはなっていない。限られたシリコン
・チップ面積内に電流通路の幅、つまりチャンネルの周
縁長であるチャンネル幅を長くとれるような多結晶シリ
コン膜パターンやチャンネル領域の形状について種々の
工夫が必要である。チャンネル幅を長くすることによっ
てドレイン電流を大きくすることが可能で、しかも大電
流領域での相互コンダクタンスｇ１も大きなものが得ら
れる。However, the structure of conventional DSA MOS FETs is not necessarily optimal. Various measures must be taken regarding the polycrystalline silicon film pattern and the shape of the channel region so that the width of the current path, that is, the channel width, which is the peripheral length of the channel, can be increased within the limited area of the silicon chip. By increasing the channel width, it is possible to increase the drain current and also obtain a large mutual conductance g1 in the large current region.

これがひいてはオン抵抗の低減化を可能にする最大の要
因であるため、いかにして限られた面積内でチャンネル
幅を長くするかが、最大の課題であった。Since this is the biggest factor in reducing on-resistance, the biggest challenge was how to increase the channel width within a limited area.

（発明が解決しようとする問題点） 従来のＤＳＡ　ＭＯＳ　ＦＥＴにおいては、半導体チッ
プ内に多数のセルを構成してチャンネル幅を長くするよ
うにしているが、第６図に示すように半導体チップ２１
にはソース電極取出し用のパッド２２と、ゲート電極取
出し用のパッド２３とを形成し、これらのパッドに直径
が１５０〜３５０　μｍのリードワイヤ２４および２５
を超音波ボンディングにより接続している。すなわち、
ボンディングパッド２２は半導体チップ２１のほぼ前面
に形成されたソースコンタクトホール２６を介してソー
ス領域に接続されたアルミニウム電極膜に接続され、ボ
ンディングパッド２３はその周辺に形成されたゲートコ
ンタクトホー／し２７を介してゲート多結晶シリコン膜
６に接続されたゲート金属電極に接続されている。この
ボンディングパッド２２および２３は、一般的には縦７
００〜１３００μｍ１横５００〜８００　μｍといった
大きな寸法を有している。従来、このボンディングパッ
ド２２および２３の下側は不活性領域となっており、セ
ルは形成されていない。したがって半導体チップの面積
効率はその分だけ低くなり、最良のパターン設計とはな
っていない。(Problems to be Solved by the Invention) In the conventional DSA MOS FET, a large number of cells are configured in a semiconductor chip to increase the channel width, but as shown in FIG.
A pad 22 for taking out the source electrode and a pad 23 for taking out the gate electrode are formed, and lead wires 24 and 25 with a diameter of 150 to 350 μm are connected to these pads.
are connected by ultrasonic bonding. That is,
The bonding pad 22 is connected to an aluminum electrode film connected to the source region via a source contact hole 26 formed almost on the front surface of the semiconductor chip 21, and the bonding pad 23 is connected to a gate contact hole 27 formed around the source region. The gate metal electrode is connected to the gate metal electrode connected to the gate polycrystalline silicon film 6 through the gate polycrystalline silicon film 6. These bonding pads 22 and 23 are generally arranged in a vertical direction.
It has large dimensions of 00 to 1300 μm and 500 to 800 μm in width. Conventionally, the lower side of bonding pads 22 and 23 has been an inactive region, and no cells have been formed therein. Therefore, the area efficiency of the semiconductor chip is correspondingly lowered, and the pattern design is not the best.

本発明は上述した点に鑑みて為されたものであり、リー
ドワイヤを接続するためのボンディングパッドの下側に
も活性領域を構成することによってチャンネル幅を長く
し、その結果としてオン抵抗を低くし、相互コンダクタ
ンスｇ、を大きくし、スイッチング・スピードを高速と
することができ、チップ面積の縮小化を図り、生産性の
向上を可能とするとともに特にゲートボンディングパッ
ドの部分のシート抵抗を下げ、大きなドレイン電流を流
すことができるように構成された縦形半導体装置を提供
しようとするものである。The present invention has been made in view of the above points, and by configuring an active region also under the bonding pad for connecting lead wires, the channel width is lengthened, and as a result, the on-resistance is lowered. This makes it possible to increase the mutual conductance g, increase the switching speed, reduce the chip area, improve productivity, and lower the sheet resistance, especially in the gate bonding pad area. The present invention aims to provide a vertical semiconductor device configured to allow a large drain current to flow.

（問題点を解決するための手段） 本発明の縦形半導体装置は、半導体基体表面上に少な（
とも２つの電極用リードワイヤをボンディングした縦形
半導体装置において、一方のＩＪ　−ドワイヤが接続さ
れるボンディングパッドの下側に独立した島状の半導体
または導電体膜パターンを形成したことを特徴とするも
のである。(Means for Solving the Problems) The vertical semiconductor device of the present invention has a small amount of
A vertical semiconductor device in which two electrode lead wires are bonded, characterized in that an independent island-shaped semiconductor or conductive film pattern is formed below the bonding pad to which one of the IJ-wires is connected. It is.

（作　用） 上述した本発明の縦形半導体装置においては、ボンディ
ングパッドの下側にも活性領域を構成することができ、
それだけチャンネル幅を太きことができ、オン抵抗を下
げることができる。また、ゲートボンディングパッドの
下側にマルチゲートを設けたためソース領域がメツシュ
状に形成され、しかも一部分が深く形成されているため
この部分のシート抵抗が減少し、多くのドレイン電流を
流すことができるようになる。(Function) In the vertical semiconductor device of the present invention described above, an active region can also be formed below the bonding pad,
The channel width can be increased accordingly, and the on-resistance can be lowered. In addition, because a multi-gate is provided below the gate bonding pad, the source region is formed in a mesh shape, and one part is formed deeply, which reduces the sheet resistance in this part and allows a large amount of drain current to flow. It becomes like this.

さらに本発明による半導体装置は通常の半導体装置の製
造技術を用いて高信頼度でかつ容易に製造することがで
きる。Further, the semiconductor device according to the present invention can be easily manufactured with high reliability using ordinary semiconductor device manufacturing techniques.

（実施例） 以下本発明を実施例により具体的に説明する。(Example) The present invention will be specifically explained below using examples.

第１図は本発明の一実施例であるＵＳＡ　ＭＯＳ　ＦＩ
ＥＴの断面図である。Figure 1 shows a USA MOS FI, which is an embodiment of the present invention.
It is a sectional view of ET.

この装置は、ｎ＋型半導体基板１上にｎ型エピタキシャ
ル成長層２が設けられ、このエピタキシャル層２の主面
にはゲート絶縁酸化膜（第１絶縁膜）５ａを介してｎ型
不純物を多量に添加した多結晶シリコン膜（半導体膜ま
たは導電体膜）パターン６が設けられ、このパターンの
開口内のエピタキシャル層２中には逆導電型の不純物を
高濃度でドープしたｐ゛型型溝導体層３設けられている
。In this device, an n-type epitaxial growth layer 2 is provided on an n+-type semiconductor substrate 1, and a large amount of n-type impurity is added to the main surface of the epitaxial layer 2 via a gate insulating oxide film (first insulating film) 5a. A polycrystalline silicon film (semiconductor film or conductor film) pattern 6 is provided, and in the epitaxial layer 2 within the opening of this pattern is a p-type trench conductor layer 3 doped with impurities of the opposite conductivity type at a high concentration. It is provided.

さらにエピタキシャル層２中には、前記第１絶縁膜５ａ
を介して前記多結晶シリコン膜パターン６の一部と部分
的に重なる位置に逆導電型の不純物を低い濃度にドープ
したｐ型の半導体層（第１半導体層）４が浅く設けられ
、このｐ型半導体層４の内部には前記第１絶縁膜５ａを
介して前記導電体膜パターン６の一部と部分的に重なる
位置にｎ゛゛半導体層（第２半導体層）８が形成され、
前記多結晶シリコン膜パターン６を被覆するように絶縁
酸化膜（第２絶縁膜＞５６が形成され、この絶縁膜上に
高抵抗のＣＶＤ　５１０２膜１１が形成され、さらにそ
の上にソースＡ１電極膜（金属電極膜）９が形成されて
いる。ソースＡ１電極膜９は、絶縁膜５ｄおよびＣＶＤ
−３ｈ０２膜１１に形成したセル内のソース電極取り出
し開口部１０ａを経て第１および第２半導体層４および
８にオ゛−ミック接続されている。Further, in the epitaxial layer 2, the first insulating film 5a
A p-type semiconductor layer (first semiconductor layer) 4 doped with impurities of the opposite conductivity type at a low concentration is shallowly provided at a position partially overlapping with a part of the polycrystalline silicon film pattern 6 via the p-type semiconductor layer 4. An n゛゛ semiconductor layer (second semiconductor layer) 8 is formed inside the type semiconductor layer 4 at a position partially overlapping with a part of the conductive film pattern 6 via the first insulating film 5a,
An insulating oxide film (second insulating film>56) is formed to cover the polycrystalline silicon film pattern 6, a high-resistance CVD 5102 film 11 is formed on this insulating film, and a source A1 electrode film is further formed on it. (Metal electrode film) 9 is formed.The source A1 electrode film 9 is made of an insulating film 5d and a CVD film.
It is ohmically connected to the first and second semiconductor layers 4 and 8 through a source electrode extraction opening 10a formed in the -3h02 film 11 in the cell.

このように半導体チップのボンディングパッド以外の部
分の構成は第５図に示した従来の構成とほぼ同様である
。本発明においては、第１図の右側に示すように、ソー
スボンディングパッド部ニおいてはアルミニウム電極膜
９と一体にソースボンディングパッド１２を形成し、そ
の上にソース電極用のリードワイヤ１３が超音波゛ボン
ディングにより融着されている。このボンディングパッ
ド１２の下側にも他の部分と同様にセルが形成されてい
る。As described above, the structure of the semiconductor chip other than the bonding pads is almost the same as the conventional structure shown in FIG. In the present invention, as shown on the right side of FIG. 1, a source bonding pad 12 is formed integrally with the aluminum electrode film 9 in the source bonding pad portion 2, and a lead wire 13 for the source electrode is superimposed on the source bonding pad 12. It is fused by sonic bonding. Cells are formed under this bonding pad 12 as well as in other parts.

本実施例においてはボンディングパッド１２と第２絶縁
膜５ｄとの間にＣＶＤ−３ｉＯ□膜１１を介在させたた
め、このＣＶＤ−３ｉ０２はリードワイヤ１３をボンデ
ィングする際の超音波振動を吸収し、その下側の第２絶
縁膜５ｄ、多結晶シリコン膜６および第１絶縁膜５ａが
破壊されることはない。したがって、ボンディングパッ
ド１２の下側にも多数のセルを形成することができ、し
たがってチャンネル幅を長くすることができ、したがっ
てオン抵抗を低くし、スイッチングスピードを向上する
ことができる。さらにＣＶＤ−５ｉ０２膜１１は良好な
パッシベーション膜としても作用するので素子特性が安
定化し、歩留りが向上する効果もある。In this embodiment, since the CVD-3iO□ film 11 is interposed between the bonding pad 12 and the second insulating film 5d, this CVD-3i02 absorbs the ultrasonic vibration when bonding the lead wire 13, and The lower second insulating film 5d, polycrystalline silicon film 6, and first insulating film 5a are not destroyed. Therefore, a large number of cells can be formed under the bonding pad 12, and therefore the channel width can be increased, and therefore the on-resistance can be lowered and the switching speed can be improved. Furthermore, since the CVD-5i02 film 11 also acts as a good passivation film, the device characteristics are stabilized and the yield is improved.

第１図の左側はゲート部におけるボンディングパッドの
構成を示すものである。このゲートボンディングパッド
部においては、ｎ−オンーｎ゛構造の半導体基体の表面
にｐ＋型型溝導体層３３よびｎ゛型型溝導体層３８深く
形成されており、このｐ゛型型溝導体層３３浅く形成さ
れたチャンネル領域形成用のｐ型半導体層３４に隣接し
て形成されている。The left side of FIG. 1 shows the configuration of bonding pads in the gate section. In this gate bonding pad portion, a p+ type groove conductor layer 33 and an n type groove conductor layer 38 are deeply formed on the surface of the semiconductor substrate having an n-on-n structure. 33 is formed adjacent to a shallowly formed p-type semiconductor layer 34 for forming a channel region.

また、ソース領域を構成するｎ゛型型溝導体層３８周縁
はこのｐ型半導体層３４と同様に横方向に拡がっており
、これらｐ型半導体層３４およびｎ”型半導体層３８は
ゲート絶縁膜５ａを介してゲート多結晶シリコン膜６ａ
と部分的に重なってチャンネルを構成している。ゲート
絶縁膜５ａの上には第２絶縁膜５ｄを介してＣＶＤ−３
ｉｎ□膜１１が形成され、その上にアルミニウムのゲー
トボンディングパッド４０が形成され、このボンディン
グパッドにはゲートリードワイヤ４１がボンディングさ
れている。ゲートボンディングパッド１１０はＣＶＤ−
３ｉ０２膜１１および第２絶縁膜５ｄにあけた孔を介し
てゲート多結晶シリコン膜６に接続されている。Further, the periphery of the n-type trench conductor layer 38 constituting the source region extends laterally in the same manner as the p-type semiconductor layer 34, and these p-type semiconductor layer 34 and n''-type semiconductor layer 38 are connected to the gate insulating layer 38. Gate polycrystalline silicon film 6a via 5a
They partially overlap to form a channel. CVD-3 is deposited on the gate insulating film 5a via a second insulating film 5d.
An in□ film 11 is formed, and an aluminum gate bonding pad 40 is formed thereon, and a gate lead wire 41 is bonded to this bonding pad. Gate bonding pad 110 is CVD-
It is connected to the gate polycrystalline silicon film 6 through a hole formed in the 3i02 film 11 and the second insulating film 5d.

第２図は、本実施例の線図的平面図を示すものであり、
ソースおよびゲートのリードワイヤＹ３および１４は破
線で示しである。ソースボンディングパッド１２の下側
には他の部分と同様にセルが形成されており、ゲートボ
ンディングパッド４０の下側には島状のゲート多結晶シ
リコン膜６ａがマトリ・；・クス状に形成され、これら
の多結晶シリコン膜は第２　絶縁膜５ｄオヨびＣＶＤ　
５１０２膜１１ニ形成した孔１０ｂを介してボンディン
グパッド４０に接続されている。FIG. 2 shows a diagrammatic plan view of this embodiment,
Source and gate lead wires Y3 and 14 are shown in dashed lines. A cell is formed under the source bonding pad 12 like the other parts, and an island-shaped gate polycrystalline silicon film 6a is formed in a matrix shape under the gate bonding pad 40. , these polycrystalline silicon films are the second insulating film 5d and CVD
It is connected to the bonding pad 40 through the hole 10b formed in the 5102 film 11.

第２図に示すようにボンディングパッド４０の周囲には
ゲートコンタクトホール４２が形成され、これらを介し
てゲート多結晶シリコン膜６に接続されている。また、
Ｎ゛型型溝導体層３８ソース領域を構成し、これはボン
ディングパッドの周縁において、ソース電極膜９に接続
されている。また、Ｐ”型半導体層３３は同じくボンデ
ィングパッドの周縁においてフィールドプレートに接続
されている。As shown in FIG. 2, a gate contact hole 42 is formed around the bonding pad 40, and is connected to the gate polycrystalline silicon film 6 through these. Also,
The N-type trench conductor layer 38 constitutes a source region, which is connected to the source electrode film 9 at the periphery of the bonding pad. Further, the P'' type semiconductor layer 33 is also connected to the field plate at the periphery of the bonding pad.

本発明においては、リードワイヤのボンディングパッド
の下側にもセルが構成されているためチャンネル幅は著
しく長くなり、オン抵抗を下げることができる。特にゲ
ート電極用のボンディングパッドの下側はマルチゲート
構造としたため、ｎ＋型型溝導体層３８り成るソース領
域が、島状のゲート多結晶シリコン膜６ａを囲むように
メツシュ状に形成されており、しかもこのソース領域は
一部深く形成されているため、その部分のシート抵抗が
減少し、ドレイン電流が多く流れ易い構造となっている
。In the present invention, since cells are also formed under the bonding pads of the lead wires, the channel width becomes significantly longer and the on-resistance can be lowered. In particular, since the lower side of the bonding pad for the gate electrode has a multi-gate structure, the source region consisting of the n+ type groove conductor layer 38 is formed in a mesh shape so as to surround the island-shaped gate polycrystalline silicon film 6a. Moreover, since this source region is partially formed deep, the sheet resistance of that portion is reduced, resulting in a structure in which a large amount of drain current flows easily.

次に第３図（ａ）〜（ｄ）を参照して本発明の半導体装
置の一実施例であるＵＳＡ　ＭＯＳ　ＦＥＴを製造する
方法について説明するが、主としてゲートボンディング
パッド部の製造方法を説明する。Next, a method for manufacturing a USA MOS FET, which is an embodiment of the semiconductor device of the present invention, will be explained with reference to FIGS. .

先ず、ｎ型不純物を高濃度で含むｎ゛゛半導体基板１上
にそれよりも低いｎ型不純物濃度を有する比抵抗が、例
えば１０〜２０Ω−ｃｍのｎ型エピタイシャル層２を３
５〜４５μｍの厚さに堆積形成し、このエピタキシャル
層の主面に５ｌＯ７膜５ｅを選択的に形成しその開口部
からｎ型不純物を多量に拡散し、約８〜１０μｍの深さ
のｐ゛型型溝導体層３３形成する。次に同じ開口部から
ｎ型不純物を多量に拡散し、約３〜４μｍの深さのｎ″
型型半体体層３８形成した様子を第３図（ａ）に示す。First, an n-type epitaxial layer 2 having a resistivity of, for example, 10 to 20 Ω-cm and having a lower n-type impurity concentration is formed on an n-type semiconductor substrate 1 containing a high concentration of n-type impurities.
A 5lO7 film 5e is selectively formed on the main surface of this epitaxial layer, and a large amount of n-type impurity is diffused from the opening of the epitaxial layer to a depth of about 8 to 10 μm. A mold groove conductor layer 33 is formed. Next, a large amount of n-type impurity is diffused from the same opening to a depth of approximately 3 to 4 μm.
FIG. 3(a) shows how the mold half body layer 38 is formed.

次に５ｉｎ２膜５ｅをエツチングにより除去した後、ゲ
ート酸化膜５ａを構成するＳｌＯ□膜を約１０００への
厚さに形成し、その上にゲート多結晶シリコン膜６ａを
約６０００人の厚さに選択的に形成した様子を第３図（
ｂ）に示す。Next, after removing the 5in2 film 5e by etching, a SlO□ film constituting the gate oxide film 5a is formed to a thickness of about 1000 nm, and a gate polycrystalline silicon film 6a is formed on it to a thickness of about 6000 nm. Figure 3 shows the state of selective formation (
Shown in b).

続いてゲート多結晶シリコン膜６ａをマスクとしてｎ型
不純物をイオン注入し、熱処理を施してチャンネル領域
を構成するｐ型半導体層３４を形成した様子を第３図（
Ｃ）に示す。Next, using the gate polycrystalline silicon film 6a as a mask, n-type impurity ions were implanted and heat treatment was performed to form a p-type semiconductor layer 34 constituting a channel region.
Shown in C).

次に、再びゲート多結晶シリコン膜６ａをマスクとして
ｎ型不純物をイオン注入し、第２絶縁酸化膜５１よびＣ
ＶＤ　５Ｉ０２膜１１を約５０００への厚さに形成した
後、熱処理を行い、ソースｎ゛型半導体層３８の張出部
を形成し、ｐ型半導体＠３４と相俟ってチヤンネル領域
を構成する。この第２絶縁膜５ｄおよび口ＶＤ　５１０
２膜１１にコンタクトホールｌＯｂを形成した後、アル
ミニウム電極膜を選択的に形成してゲートボンディング
パッド４０を形成し、ここにゲート電極用の直径約３０
０　μｍのリードワイヤ４１をボンディングした様子を
第３図（ｄ）に示す。Next, using the gate polycrystalline silicon film 6a as a mask, n-type impurity ions are implanted again, and the second insulating oxide film 51 and C
After forming the VD 5I02 film 11 to a thickness of about 5,000 μm, heat treatment is performed to form an overhang of the source n-type semiconductor layer 38, which together with the p-type semiconductor @34 constitutes a channel region. . This second insulating film 5d and the opening VD 510
After forming a contact hole lOb in the second film 11, an aluminum electrode film is selectively formed to form a gate bonding pad 40.
FIG. 3(d) shows how the lead wire 41 of 0 μm is bonded.

本発明は上述した実施例に限定されるものではなく幾多
の変更を加えることができる。The present invention is not limited to the embodiments described above, but can be modified in many ways.

例えば上述した実施例ではゲートボンディングパッドの
下側には複数の島状のゲート多結晶シリコン膜を形成し
たが、第４図に示すように櫛形の１個のゲート多結晶シ
リコン膜６ｂを形成することもできる。For example, in the above embodiment, a plurality of island-shaped gate polycrystalline silicon films were formed under the gate bonding pad, but as shown in FIG. 4, one comb-shaped gate polycrystalline silicon film 6b is formed. You can also do that.

また、ゲート電極材料は必ずしも多結晶シリコンとする
必要はなく、他の半導体材料や、Ｍｏ、Ｎｉ。Further, the gate electrode material does not necessarily need to be polycrystalline silicon, but may be other semiconductor materials, Mo, or Ni.

Ｔｉ、Ｃｒ等の高融点金属や、モリブデンシリサイド、
ニッケルシリサイド、白金シリサイド等とすることもで
きる。また、ｎ型半導体領域とｎ型半導体領域の導電型
は反対としてもよい。さらに、上述した実施例では縦形
半導体装置の内、Ｏ３Ａ　ＭＯＳ　ＦＢＴを示したが、
ゲートをベースとし、ソースをエミッタとするバイポー
ラトランジスタや、Ｖ−溝またはＵ−溝を有する他のＭ
［ｌＳ　ＦＥＴにも適用することができる。High melting point metals such as Ti and Cr, molybdenum silicide,
Nickel silicide, platinum silicide, etc. can also be used. Further, the conductivity types of the n-type semiconductor region and the n-type semiconductor region may be opposite. Furthermore, in the above-mentioned embodiment, an O3A MOS FBT was shown among the vertical semiconductor devices, but
Bipolar transistors with gate as base and source as emitter and other M transistors with V-groove or U-groove
[Can also be applied to lS FETs.

さらに、上述した例では第２絶縁膜の上にＣＶＤ−３ｉ
Ｏ２膜を形成し、さらにその上にボンディングパッドを
形成したが、これらを一体のＣＶＤ−３ｉｎ２膜、ＰＳ
Ｇ膜、さらにこれらの上に高抵抗半導体膜やポリイミド
膜を形成することもできる。Furthermore, in the above example, CVD-3i is applied on the second insulating film.
An O2 film was formed and bonding pads were formed on it, but these were combined into an integrated CVD-3in2 film and PS
It is also possible to form a high resistance semiconductor film or a polyimide film on the G film, and further on these.

（発明の効果） 上述した本発明によれば、ボンディングパッドの下側に
も活性領域を形成することができ、チャンネル幅を長く
することができ、大きな電流が得られるとともにオン抵
抗が低くなり、相互コンダクタンスｇ１が大きくなりス
イッチング・スピードが高速となる。またゲートボンデ
ィングパッドの部分にはゲート多結晶シリコン膜を囲む
メツシュ状のソース領域が深く形成されているため、ソ
ース領域のシート抵抗は低くなり、大きなドレイン電流
を流すことができる。(Effects of the Invention) According to the present invention described above, an active region can be formed also under the bonding pad, the channel width can be increased, a large current can be obtained, and the on-resistance can be reduced. The mutual conductance g1 increases and the switching speed increases. Furthermore, since the mesh-like source region surrounding the gate polycrystalline silicon film is deeply formed in the gate bonding pad portion, the sheet resistance of the source region is low, and a large drain current can flow.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明による縦形半導体装置の一実施例の構成
を示す断面図、 第２図は同じくそのチップ全体の構成を線図的に示す平
面図、 第３図（ａ）〜（ｄ）は本発明の製造方法により縦形電
界効果トランジスタを製造する順次の工程を示す断面図
、 第４図はゲートボンディングパッド部の下側に形成した
島状の多結晶シリコン膜の他の形状を示す平面図、 第５図（ａ）および（ｂ）は従来の縦形電界効果トラン
ジスタの構成を示す平面図および断面図、第６図は同じ
くそのチップの全体の構成を線図的に示す平面図である
。 ■・・・ｎ゛型半導体基板 ２・・・ｎ型エピタキシマル層 ３．３３・・・ｐ−＝型半導体層 ４．３４・・・ｐ型半導体層 ５ａ・・・ゲート継母酸化膜 ５ｂ・・・酸化膜　　　　　５ｄ・・・第２絶縁膜６、
５ａ、　５ｂ・・・多結晶シリコン膜８．３８・・・ｎ
゛型半導体層 ９・・・電極金属膜　　　１１・・・ＣＶＤ−３ｉｎ。 膜１２、４０・・・ボンディングパッド １３．４１　・・・リードワイヤ 特許出願人　　　ティーディーケイ株式会社第２図 第３図 （ｄ） 第４図FIG. 1 is a sectional view showing the structure of an embodiment of a vertical semiconductor device according to the present invention, FIG. 2 is a plan view diagrammatically showing the overall structure of the chip, and FIGS. 3(a) to (d) 4 is a cross-sectional view showing the sequential steps of manufacturing a vertical field effect transistor by the manufacturing method of the present invention. FIG. 4 is a plan view showing another shape of the island-shaped polycrystalline silicon film formed under the gate bonding pad part 5(a) and 5(b) are a plan view and a sectional view showing the structure of a conventional vertical field effect transistor, and FIG. 6 is a plan view diagrammatically showing the overall structure of the chip. . ■...n-type semiconductor substrate 2...n-type epitaxial layer 3.33...p-= type semiconductor layer 4.34...p-type semiconductor layer 5a...gate stepmother oxide film 5b... ...Oxide film 5d...Second insulating film 6,
5a, 5b...polycrystalline silicon film 8.38...n
゛-type semiconductor layer 9...electrode metal film 11...CVD-3in. Membranes 12, 40... Bonding pads 13, 41... Lead wire Patent applicant TDC Co., Ltd. Figure 2 Figure 3 (d) Figure 4

Claims (1)

【特許請求の範囲】 １、半導体基体表面上に少なくとも２つの電極用リード
ワイヤをボンディングした縦形半導体装置において、一
方のリードワイヤが接続されるボンディングパッドの下
側に独立した島状の半導体または導電体膜パターンを形
成したことを特徴とする縦形半導体装置。 ２、前記島状の半導体または導電体膜パターンの周辺に
沿って、半導体本体とは反対導電型の第１半導体層と、
この第１半導体層の内部に形成され、半導体基体と同じ
導電型を有する第２半導体層とを以ってチャンネル領域
を形成したことを特徴とする特許請求の範囲１記載の縦
形半導体装置。 ３、前記島状の半導体または導電体膜パターンの間およ
びその全体の外周を囲むように、前記第１半導体層と同
じ導電型を有し、第１半導体層よりも深く形成された第
３半導体層と、前記第２半導体層と同じ導電型を有し、
第２半導体層よりも深く形成された第４半導体層とを具
えることを特徴とする特許請求の範囲２記載の縦形半導
体装置。[Claims] 1. In a vertical semiconductor device in which at least two lead wires for electrodes are bonded on the surface of a semiconductor substrate, an independent island-shaped semiconductor or conductor is provided below the bonding pad to which one of the lead wires is connected. A vertical semiconductor device characterized by forming a body film pattern. 2. along the periphery of the island-shaped semiconductor or conductor film pattern, a first semiconductor layer of a conductivity type opposite to that of the semiconductor body;
2. The vertical semiconductor device according to claim 1, wherein a channel region is formed by a second semiconductor layer formed inside the first semiconductor layer and having the same conductivity type as the semiconductor substrate. 3. A third semiconductor having the same conductivity type as the first semiconductor layer and formed deeper than the first semiconductor layer between the island-shaped semiconductor or conductor film patterns and surrounding the entire outer periphery thereof. layer, and having the same conductivity type as the second semiconductor layer,
3. The vertical semiconductor device according to claim 2, further comprising a fourth semiconductor layer formed deeper than the second semiconductor layer.
JP60291855A 1985-12-26 1985-12-26 Vertical type semiconductor device Pending JPS62152169A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60291855A JPS62152169A (en) 1985-12-26 1985-12-26 Vertical type semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60291855A JPS62152169A (en) 1985-12-26 1985-12-26 Vertical type semiconductor device

Publications (1)

Publication Number Publication Date
JPS62152169A true JPS62152169A (en) 1987-07-07

Family

ID=17774291

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60291855A Pending JPS62152169A (en) 1985-12-26 1985-12-26 Vertical type semiconductor device

Country Status (1)

Country Link
JP (1) JPS62152169A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5089864A (en) * 1989-09-08 1992-02-18 Fuji Electric Co., Ltd. Insulated gate type semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5089864A (en) * 1989-09-08 1992-02-18 Fuji Electric Co., Ltd. Insulated gate type semiconductor device

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