JPS62152082A - Raster scan type graphic display device - Google Patents

Abstract

PURPOSE:To display a pattern with high resolution with low cost by applying plural shift clocks with different phase to plural parallel/serial converters and switching the output sequentially. CONSTITUTION:A serial output of points SD0, SD1 of frame memories 52-1, 52-2 and 52-3 is enabled through an output enable line a1 in case of the first scan line display, the serial output data is sent to a parallel/serial converter 71 for the initial line display. When the 2nd scan line display is started, the serial output of points SD2, SD3 of the frame memories 52-4, 52-5 and 52-3 is enabled through an output enable line a2 and its serial output data is sent to the parallel/serial converter 71 and displayed. The operations above are repeated for the display operation, then a 2-port DRAM is constituted by using devices with a low speed serial output buffer response.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a raster scan type graphic display device used in a computer graphic information processing system.

2. Description of the Related Art In recent years, computer
ter Aided Design /Compute
r Aided Manufacturing (hereinafter referred to as C
Graphical information processing systems such as AD/CAM (abbreviated as AD/CAM) that utilize the high-speed, large-capacity information processing capabilities of computers are becoming increasingly popular.

FIG. 3 shows an example of equipment constituting a graphical information processing system. In FIG. 3, B is a computer that performs numerical processing of graphical information and data transfer between other computer systems. b and C are auxiliary storage devices that store various data such as graphic information. e is a plotter for hard copying graphic information and the like. f is a raster scan type graphic display device that displays graphic information on a raster scan type cathode ray tube (hereinafter referred to as CRT).

g is a character terminal device for giving graphic processing commands and the like to the computer main body a and displaying processing results from the computer main body a. h is a digitizer for inputting graphic information.

Due to the complexity of the graphic information handled and the increase in the amount of information, users of these graphic information processing systems receive graphic information from the computer main unit a and use it by displaying it on the CR7 screen. Expanding the number of display pixels for raster scan type graphic display devices that provide visual information to users.

Improving Display Speed 9 There is a strong demand for improved performance in terms of increasing the number of display colors. In addition, in recent years, the environment in which computer systems are used has been reviewed from an ergonomic standpoint, and display devices that use raster scan type CRTs are now being developed to reduce flicker and reduce user fatigue. It's being sought after.

In response to such demands from users, recent raster scan graphics display devices have increased memory capacity for screen display to increase the number of display pixels, and increased frame frequency to reduce flicker. Improvements in functionality are progressing by increasing the number of devices.

Hereinafter, a conventional raster scan type graphic display device will be described with reference to the drawings.

FIG. 4 shows a block diagram of a conventional raster scan type graphic display device. In FIG. 4, 1 is a screen display control signal generator (CRT Controller: hereinafter referred to as CRTC), which outputs 0 from a timing generator 10.
RTC: A clock is frequency-divided to generate display addresses for the frame memory 5 and vertical and horizontal synchronization signals used for composing images on the CRT screen. Here, the display address means, as shown in FIG. The contents of the bit are “
When it is 1', turn on 1 bit on the CR7 screen and set it to "0".
This is an address to be applied to the frame memory 5 in order to display the image by turning it off when .

2 is OP U (Central Processing
g Unit ), it sets the timing parameters of the vertical and horizontal synchronization signals for the 0RTC1 according to the clock from the timing generator 1o, and sends data to the frame memory 5 for setting and modifying graphic data. I also do some reading and writing.

3 is the CPU address output for writing and reading graphic data from the CPU 2 and the display address from 0RTC1, and the CPU address and the display address from 0RTC1 are outputted simultaneously and the CPU address is output to Cr1.
7 This is an address switch for switching and applying the voltage to the address input terminal of the frame memory 5 so as not to cause flickering on the screen.

41d, a buffer for connecting the data bus 13 of the CPU 2 and the data input terminal of the frame memory 6 when the CPU 2 writes graphic data to the frame memory 5;

5 is a frame memory that stores graphic data at a display address that corresponds one-to-one with the screen display position of a graphic to be displayed on the CRT screen, and has a data input terminal and an output terminal. It's separate.

6 is a buffer for connecting the data bus 13 of the CPU 2 and the data output terminal of the frame memory 6 when the CPU 2 reads the contents of the frame memory 5.

Reference numeral 7 denotes a parallel-to-serial converter, which converts the parallel graphic data outputted from the frame memory 5 into serial data according to the video clock of the timing generator 1Q.

Reference numeral 8 denotes a main memory that stores programs for controlling the operation of the CPU 2 and the like. Reference numeral 9 denotes an oscillator that generates a clock that is the basis of the operation of the device.

A timing generator 1o divides the frequency of the clock obtained from the oscillator 9 to generate a parallel data load clock for the parallel-to-serial converter 7, an operating clock for the 0RTC 1 and the CPU 2, a control clock for the frame memory 5, and the like.

Reference numeral 11 denotes a display address bus for transmitting the display address output from CRTCl to one input terminal of the address switch 3. Reference numeral 12 denotes an address bus for transferring the address output of the CPU 2 to other input terminals of the address switch 3, address input terminals of the main memory 8, and the like. 13
CPU2, CRTCI and buffer 4. Main memory memory8. This is a data bus for transferring control parameters, graphic data, programs, etc. to and from the buffer 6, etc.

Reference numeral 14 denotes a CRTC clock line for transmitting the basic clock of the oscillator 9 divided by the timing generator 1o as the basic clock of the CRTll. 16 is a CPU clock line for transmitting the basic clock of the oscillator 9 divided by the timing generator 10 to the CPU 2 as the basic clock, similar to the 0RTO clock. 16 is a WRITE signal line used when writing graphic data from the CPU 2 to the frame memory 6.

17 is a row address selection signal (Row Addasss) for setting a row address for the frame memory 5;
RA that conveys the execute signal (hereinafter abbreviated as RAS signal)
This is the S signal line. 18 is a column address selection signal (Col) for setting a column address for the frame memory 6.
umn Address 5 select signal - CA below
This is a CAS signal line that transmits the S signal. The RAS signal and the CAS signal are transmitted to a dynamic RAM (Dy
namic Random AccessM6mOr7
- When using DRAM (hereinafter abbreviated as DRAM), the address structure of DRAM is such that specific data bits can be read and written by a combination of row address and column address, and these row addresses and column addresses are sequentially set in DRAM. This signal is applied to the DRAM in order to do this.

Reference numeral 19 denotes a video clock line for transmitting a video clock generated by the timing generator 10 in accordance with the clock of the oscillator 9. 2o is a video signal line for transmitting the video signal output from the parallel-to-serial converter 7 to the CRT, and the video signal is output as serial data according to the video clock from the graphic data set in the parallel-to-serial converter 7. It is something that will be done.

The operation of the raster scan type graphic display device configured as described above will be explained below.

The display address output from the 0RTC 1 is applied to the address input terminal of the frame memory 5 via the address switch 3, and the graphic data in the frame memory S corresponding to the address is output.

This graphic data is converted from parallel data to serial data by the parallel-serial converter 7 according to the video clock, and is output as a video signal.

Next, the writing and reading operations of the CPU 2 with respect to the graphic data stored in the frame memory 6 will be explained. C
The PU 2 applies an address for writing or reading graphic data to the frame memory 5 via the address switch 3.

In the case of data writing, the CPU writes data to the frame memory 6 corresponding to the address via the buffer 4.
2 writes graphic data.

On the other hand, in the case of reading, the CPU 2 reads graphic data from the frame memory 5 corresponding to the address via the buffer 76.

The above is the operation of sequentially displaying the graphic data stored in the frame memory 5 on the 017 screen according to the display address output from the CRTCI, and the operation of the CPU 2 reading and writing graphic data to the necessary addresses of the frame memory 5. Now, the detailed configuration and operation of the surroundings of the frame memory 5, which are related to the present invention, will be explained using FIGS. 6 and 7.

FIG. 6 is a detailed block diagram of a portion consisting of the address switch 3, buffer 4, frame memory 5, buffer 6, and parallel-to-serial converter 7 in FIG. Figure 7 is the 6th
It is a configuration diagram of one memory block when the frame memory 5 in the figure is divided into N groups (N is a natural number) of memory blocks 5-1 to 5-N for convenience of explanation. FIG. 7 shows the D as a memory element, which has one data input terminal, one data output terminal, and separate input and output terminals.
It uses RAM. This memory block consists of 8 D
It is composed of RAM, and each memory block has eight data input/output lines 't'L.

Here, the performance of the raster scan type graphic display device currently being described is that the CRT screen display configuration is 1280 dots in the horizontal direction and 1024 dots in the vertical direction.

If the frame frequency is 60 Hz, the same frequency of the video signal is required to be approximately 100 MH2 based on the performance of current raster scan type CRTs. In general, a DRAM requires a cycle time of approximately 250 nS to 40 onS after an address is applied using a RAS signal and a CAS signal to read or write data until an address input is applied again. The frame memory 6 constituted by the DRAM has a period for writing and reading graphic data from the 0PU2 in FIG.
A period (hereinafter referred to as CR
Since two periods (referred to as TC periods) are repeated alternately, if the cycle time of the DRAM is 40On15, 0RTC1 applies a display address to the frame memory 5 and displays graphic data from the frame memory 5. 80 until the CPU period starts and the CRTOl can apply the display address to the frame memory 6 again.
It will take 01S.

On the other hand, the video signal has a frequency of 100 MH2° and a period of 101! Frame memory 601 corresponding to one dot in i
Since it is necessary to send bit data sequentially, the reading cycle of the frame memory 5 is 5 o which is not displayed on the CRT screen.
ons divided by the video signal period 101S: 8001g+10nS=80 From this, 80 bits of graphic data must be read out from the frame memory 6 at a time and set in the parallel-to-serial converter 7. The video clock having a period of 101S, which is the same as that of the video signal, is applied as a conversion clock to the parallel-to-serial converter 7, and the graphic data is sequentially outputted as serial data according to the video clock to become a video signal.

Therefore, if a DRAMfr with a video signal frequency of 100MH2 and a cycle time of 400ns is used as a memory element for the frame memory 5, at least 80 DR
AM is required. Furthermore, the parallel-serial converter 7 and buffer 16 connected to the data output terminal of the DRAM usually have many elements that perform 4-bit or 8-bit parallel processing.If 8-bit elements are used, the parallel-serial converter 7 and buffer 16 are ,
Each requires 8o÷8=10 elements. From the above, in the sixth factor, frame memory 6 is memory block 1
0 set (one set of memory blocks is composed of 8 DRAM elements), buffer 6 and parallel-serial converter 7 are each composed of f'L10 elements (assumed to be 8-bit elements). It becomes 1o.

The above is a description of the configuration and operation of Conventional Example 1. However, the above configuration requires a large number of elements, problems with printed circuit board mounting, power consumption, reliability,
This had problems such as cost.

In recent years, as a means to solve the above-mentioned problems, the frame memory has been constructed using dual port DRAM (hereinafter abbreviated as 2-port DRAM). The 2-point DRAM has the function of incorporating a DRAM and a shift register into the same IC element, and has a configuration as shown in FIG. The configuration and operation will be explained below based on FIG. Figure 8 1-
1 to 1-4 are column address decoders, and cell array 2
This decoder is used to set column addresses for -1 to 2-4. The cell arrays 2-1 to 2-4 are memory cells, which are units for storing data, arranged in rows and columns. Data registers 3-1 to 3-4 are for latching fixed length data in parallel from cell arrays 2-1 to 2-4. The selectors 4-1 to 4-4 are for outputting data at the position designated by the pointer 7 from the data registers 3-1 to 3-4. The serial output buffer 6 is for switching between outputting the output signals of the selectors 4-1 to 4-4 to the serial output lines b1 to b4, or not outputting them and making them a tri-state output.

Row address decoder 6 is a decoder for setting row addresses for cell arrays 2-1 to 2-4.

Pointer 7 is used to specify to selectors 4-1 to 4-4 which position of data registers 3-1 to 3-4 should be outputted. Timing generation 8 is R
This is to generate an appropriate lock for each circuit from the AS signal line f1, CAS signal line g, etc. Data input/output lines a1 to a4 are connected to cell arrays 2-1 to 2-4 and 2.
This is for transmitting parallel data between the port DRAM and the outside. Address line C is used to apply addresses to column address decoders 1-1 to 1-4, row address decoder 6 and pointer 7.

The serial clock line d is used to supply the pointer 7 with a serial clock for sequentially changing the data output positions specified for the selectors 4-1 to 4-4. The output enable line e is used to specify to the serial output buffer 6 whether or not to output data from the selectors 4-1 to 4-4 to the serial output lines b1 to b4.

The serial output lines b1 to b4 are connected to the serial output buffer 6.
This is for transmitting the output data to the outside.

The RAS signal lsf and the data transfer line transmit the FtAS signal and the data transfer signal in order to set the address applied via the address line C to the row address decoder 6 or pointer 7. The CAS signal line g is for transmitting a CAS signal in order to set the address applied via the address line C to the column address decoder.

The WRITE signal line is for transmitting a WRITIC signal to specify whether or not to write the data applied to the cell arrays 2-1 to 2-4 via the data input/output lines a1 to a4.

Based on the above configuration, the operation of the 2-port DRAM will now be explained. First, when reading and writing data to and from cell arrays 2-1 to 2-4, addresses are transferred to row address decoder 6, column address decoders 1-1 to 1-1 through address line C.
4, respectively, the RAS signal and the C
The AS signal is latched as a row address and a column address, and specifies the position where data is to be read or written to cell arrays 2-1 to 2-4. This cell array 2-1 to 2-
Data is transmitted to the memory cell at the designated position of 4 via data input/output lines &1 to a4i. At this time, if the WBITIC signal is ON, data is written to the memory cell, and if it is OFF, data is read from the memory cell. Next, cell array 2-
Data transfer from data registers 1 to 2-4 to data registers 3-1 to 3-4 will be explained. When the RAS signal is input.

When the data transfer signal is ON, the data transfer mode is entered. In the data transfer mode, the address is first transferred to the row address decoder 6 and pointer 7 via the address signal line C.
and are set by the RAS signal and the CAS signal, respectively. The row address set in the row address decoder 6 specifies the row position for the cell arrays 2-1 to 2-4, and the data in the memory cells at that position is transferred in parallel to the data registers 3-1 to 3-4. be done. The address set in the pointer 7 is used to specify from which position of the data registers 3-1 to 3-4 the data is to be output to the serial output buffer 6.

Next, serial output will be explained. data register 3
The data from -1 to 3-4 is sent to the serial output line b1= via the selectors 4-1 to 4-4 and the serial output buffer 5.
b 4 is output. As mentioned above, pointer 7 is
Data register 3-1 for selectors 4-1 to 4-4
This is used to specify which position of data from 3-4 to 3-4 is to be output, and the address set in the pointer 7 is sequentially increased (or decreased) by the serial clock. As a result, the selectors 4-1 to 4-4 are sequentially switched, and eventually the data registers 3-1 to 3-4
The data set to will be output as continuous serial data. Further, except in the data transfer mode, reading and writing from and to the memory cells 2-1 to 2-4 and serial output of data in the data registers 3-1 to 3-4 can be performed independently.

The above is an explanation of the configuration and operation of the 2-port DRAM (for example, "Nikkei Electronics Magazine" August 12, 1985 issue, p. 211-p. 240).

Next, an example of the configuration of the frame memory using the 2-bot DRAM will be described as Conventional Example 2.

Here, the performance of the raster scan type graphic display device is CR
The T screen display configuration is 1280 dots horizontally.

In the case of vertical direction 1024 dots, frame frequency 60H2° and video signal frequency 107MHIZ, the storage capacity of the 2-bot DRAM used is 26214 dots.
4 bits (64 x 4 bits), serial output is 256
X4 bits, number of data input/output lines is 4, number of serial output lines is 4, cell array cycle time is 230nS.
, the case where the cycle time of the data register is 401S will be explained (for example, NIECI!D41264.
Fujitsu type MB81461 etc.).

Conventional Example 2 will be described below with reference to the drawings, but since the overall configuration and operation of the raster scan type graphic display device are the same as those of Conventional Example 1, the surroundings of the frame memory Only the configuration and operation of the detailed block diagram will be explained.

Regarding this conventional example 2, the above-mentioned document "Nikkei Electronics Magazine J19E15 August 12, p. 211-p.
・p in 240, 25th figure in 239 1280X1024
Dual pixel display frame buffer
This will be explained by citing an example of a configuration in which a boat memory is used.

FIG. 9 shows a block diagram around the frame memory of a raster scan type graphic display device of conventional example 2. 9th
In the figure, a frame memory 61 has the same function as the frame memory 5 of the prior art example 1, but in this case it is constructed of a 2-baud DRAM. Here, frame memory 5
The bit configuration of 1 is as shown in Figure 10, and the CRT
The screen can be made up of 1280 dots in the horizontal direction and 1024 dots in the vertical direction for 4 screens.

Therefore, the number of elements of the 2-bot DRAM is 5 (for 1 play) x 4 = 20 elements. Here, a plane is a unit of one screen of memory constituting the frame memory, and the number of displayable colors etc. are determined by the number of planes.

Reading and writing data from the CPU to and from the frame memory 61 is performed, for example, in units of 0 to 16 at a time, as shown in FIG.
Processes 6 bits. In addition, in FIG. 9, the CPU and C
The path for reading and writing data from the RTC to the frame memory 51 is the same as that described in the prior art example 1, and is therefore omitted. The parallel-to-serial converter 7 is a part that latches the serial data coming out of the frame memory 61 and converts it into a video signal according to the video clock. The output enable control 8 controls the frame memory 51 to select memory elements 61-1 and 5 that can transmit data to the parallel-serial converter 7.
1-2, 51-3, . . . and so on.

Based on the above configuration, the display operation of Conventional Example 2 will now be described. As mentioned in the explanation about the 2-point DRAM, data is transferred from the cell array to the data register inside the 2-point DRAM when it does not have an adverse effect on the screen display such as flickering (for example, during the retrace period). The data of 266x4 pits is transferred to the data register.

As mentioned above, the display start position is 2-vote D.
Set the voice display start address in RAM. Here, the output enable control 8 enables the serial output of the frame memory 61-1 (ΣN
ABLIC), the data is transferred to the parallel-to-serial converter 7.
and converted into a video signal. Next, the serial output of 61-1 is turned off by the output enable control 8 (at the same time, the serial output is input to 61-1, making it possible to output the next data).
The serial output of -2 is enabled and the data of 51-2 is sent to the parallel-to-serial converter 7, which is repeated, and a graphic corresponding to the contents of the frame memory 6' is displayed on the CRT screen. That will happen.

Regarding the reading and writing of data from the CPU etc. to the frame memory 51, as described in the explanation of the 2-point DRAM, the display is not displayed except when data is transferred from the cell array in the 2-point DRAM to the data register. It can be done completely independently of the action.

The above is an explanation of the configuration and operation of Conventional Example 2 when a 2-baud DRAM is used as a frame memory. With this configuration, the cycle time for latching from the frame memory to the parallel-serial converter 7 is faster than 10,800 nS in the conventional example, but 4 onS in the conventional example 2, so the bit length of the parallel data sent from the frame memory is 80 bits. The number of elements can be reduced to 4 bits, and the number of elements can be reduced.

Problems to be Solved by the Invention However, in the above configuration, the parallel-serial converter 7
As an element used for the video clock signal 107MHz
It is necessary to use an element that can operate at Em
Ittor Coupled Logic (hereinafter referred to as ECL)
A parallel-to-serial conversion element (abbreviated as ) will be used. However, using an ECL parallel-to-serial converter requires high cost and generates a lot of heat, and high-speed signals with an enable period of 4 Q n56c must be used for the enable signals KNO to EN4 of the 2-port DRAM. First, there was a problem in that the serial output buffer of the 2-port DRAM had to have a high-speed response of 40 n55c.

In view of the above-mentioned problems, the present invention is capable of configuring a frame memory with the minimum necessary size, and by lowering the frequency of the shift clock applied to the parallel-serial converter, it uses an inexpensive parallel-serial converter and reduces costs. To provide a raster scan type graphic display device that is inexpensive and capable of displaying a high-resolution screen with little flicker.

Means for Solving the Problems In order to solve the above problems, the raster scan type graphic display device of the present invention uses a DRA having a serial shift function.
M, and multiple sets of parallel-to-serial conversion elements that convert serial output data from the DRAM into video signals.

Effect of the present invention With the above-described configuration, the number of DRAM elements can be kept to a necessary minimum with respect to the required number of planes, and parallel-serial conversion elements that are low in cost and consume little current are used. This makes it possible to display a high-resolution screen with low flicker and low cost.

EXAMPLE Hereinafter, a raster scan type graphic display device according to an example of the present invention will be described with reference to the drawings.

The performance of the raster scan type graphic display device is as follows:
As in Conventional Example 2, the CRT screen display configuration is 1280 dots in the horizontal direction, 1024 dots in the vertical direction, the frame frequency is 60 Hz, and the frequency of the video signal is 1'07 MHz.
Now, the case where the number of planes is 1 will be explained. Furthermore, 2-bot DRAM has a storage capacity of 282,144 bits (
84 x 4 bits).

Serial output 256 x 4 bits, number of data input/output lines 4, number of serial output lines 4, cell array cycle time 2301g, data register cycle time 40
I will explain the case where it is configured with nS (for example, NEC
Manufactured by D41264. Fujitsu M881461, etc.).

The overall structure and operation of the raster scan type graphic display device is the same as the structure and operation of the prior art example 1, so only the structure and operation of the detailed block diagram around the frame memory will be described here.

FIG. 1 shows a block diagram of the periphery of a frame memory of a raster scan type graphic display device according to the present invention. In FIG. 1, a frame memory 52 is composed of five elements, which is the minimum number of elements for one 2-bot DRAM. (1280 bits) Xl 024 bits = 13107
20 bits.

(1310720 bits/262144 bits/piece=5 pieces) The bit configuration of this frame memory is as shown in FIG. Also, bits 0 to 19 and the actual frame memory 62-1
The table below shows the correspondence between the serial outputs of ~52-5.

When reading and writing data from the CPU etc. to the frame memory, 20 bits from 0 to 19 are processed at one time.

71 is a parallel-to-serial converter that converts the serial data output from the frame memory 52 into a video signal in accordance with the video clock. Here, two sets of 6-bit parallel-to-serial converters are used.

9 is a tri-state gate, and frame memory 52
(2 baud) DRAM has a 4-bit output and is composed of 5 elements, so the 4-bit output of one of the elements is
It is a divider that divides the remaining four elements into two elements each and converts each output into parallel-serial converters 71-1 and 71-.
Allocate the same number of bits to 2.

1o is a signal switch, and is a parallel-serial converter 71-1.

The serial data from 71-2 is alternately switched to become a video signal. 1L and 1L2 are output enable lines that specify which signal line is to be enabled for the tristate gate 9. A serial clock line C supplies a serial clock for serial output of the 2-point DRAM.

Each shift clock line f9g connects to a parallel-serial converter 71-1.
, 71-2 are supplied with shift clocks having mutually opposite phases. The signal switching line supplies the signal switching device 1o with a switching signal for converting the serial output from the parallel-serial converter 71-1, 71-2 into a video signal.

The operation of this embodiment having the above configuration will be described below.

First, the display operation will be explained. It is basically the same as the display operation of the conventional example 2.

However, the circuit for enabling serial output from the frame memories 52-1 to 52-5 and the circuit for converting serial output data into a video signal are different.

Regarding the enable circuit, for example, when displaying the first scan line, the frame memory 52-1 is used.

52-2. The serial outputs of SDO and SDl of 62-3 are enabled by the output enable line a1, and this serial output data is sent to the parallel-to-serial converter 71. Next, when the first scan line display ends and the second scan line display begins, the frame memory 52-
4.Sn2 of 52-5 and 52-3. The serial output of Sn3 is enabled by the output enable line a2, and the serial output data is sent to the parallel-to-serial converter 71. Furthermore, for the third scan line, the SD of frame memories 52-1, 52-2 and 52-3 is
Serial output of O and SDl is enabled. Display operation is performed by repeating the above, but with this configuration, the enable period is approximately 11.9 μsec,
Compared to the short enable period of about 40 nS in Conventional Example 2, there is sufficient margin, so that the frame memory 52 can be configured with a 2-port DRAM having a low-speed serial output buffer response.

Next, we will explain the operation of the circuit that converts the serial output data of the frame memory 52 into a video signal.
The frame memory 52 outputs 10 bits of data at a time, and 5 bits each are sent to the parallel to serial converter 71.
-1, latched to 71-2. The latched data is sequentially processed by shift clocks having a frequency of 1A per video clock and having mutually different phases, which are applied to the parallel-serial converters 71-1 and 71-2 via output enable lines a1 and a2. , is output to the signal switch 1o. Signal switch 1
At o, the outputs of the parallel-to-serial converters 71-1 and 71-2 are alternately switched and converted into video signals by a switching signal applied via a signal switching line.

According to the above explanation, the parallel-serial converter 71-1゜71-2
The shift clock applied to the video clock is X12 of the video clock.
(107 MH2/2=53.5 MHz) f is good and can be used even with an inexpensive Schottky TTL parallel-serial converter.

As described above, in this embodiment, two sets of parallel-to-serial converters are used, but by providing multiple sets of these, it is possible to lower the shift clock of the parallel-to-serial converters with respect to the video clock. .

Furthermore, among the odd number of frame memories (5 elements in this embodiment), multiple bits of one DRAM are
Although a tri-state gate was used as a distributor to distribute data to the plurality of parallel-serial converters, the same effect can be achieved by using a data selector. In addition, the signal switching device of this embodiment has an actual EC.
Although the L HD10124 (Hitachi type TTI, ECL converter) is used, the same effect can be achieved by using a data selector here.

Effects of the Invention As described above, the present invention provides a DRAM having a serial shift function of the minimum number of elements required for each plane, which is a unit forming the periphery of a frame memory, and a DRAM connected to a serial output terminal of the DRAM. By constructing two sets of parallel-to-serial converters that can convert the serial output data from the 3D to video signals at the video clock frequency, it is possible to display a high-resolution screen with low flicker at a low cost. A scanning graphics display device can be provided.

[Brief explanation of drawings]

FIG. 1 is a detailed block diagram of the periphery of the frame memory of a raster scan type graphic display device according to an embodiment of the present invention;
Figure 2 is a bit configuration diagram of the frame memory in Figure 1;
The figure is a block diagram showing an example of a graphic information processing system, and FIG. 4 is a block diagram of a raster scan type graphic display device of conventional example 1.
Figure 5 shows the contents of frame memory and raster scan type CR.
A correspondence diagram showing the correspondence relationship with the dots on the T screen, Figure 6 is a detailed block diagram around the frame memory of the M4 diagram, and Figure 7
The figure is a block diagram of one memory block constituting the frame memory 5 in FIG. 6, and FIG.
A block diagram of the AM element, FIG. 9 is a detailed block diagram of the periphery of the frame memory of conventional example 2, and FIG. 10 is a bit configuration diagram of the frame memory of FIG. 9... Tritate gate, 1o... Signal switch, 52... Frame memory, 71...
...Parallel-serial converter, 2L1. a2... Output enable line, C... Serial clock line, f, g
...Shift clock line, h...Signal switching line. Name of agent: Patent attorney Toshio Nakao and 1 other person Compilation 1
Figure 2 Figure 50, CRT&m □ Figure 6 Figure 7 Figure 8

Claims (4)

[Claims] (1) a raster scan type cathode ray tube, a frame memory that corresponds one-to-one to the screen of graphics to be displayed on the cathode ray tube, and a dynamic memory element provided in the frame memory and having a serial shift function; a plurality of parallel-serial converters for storing serial data output from the serial shift function of the frame memory; a plurality of shift clocks having different phases are applied to the plurality of parallel-serial converters; A raster scan type graphic display device that sequentially switches the output of a parallel-to-serial converter and applies it to the cathode ray tube as a video signal. (2) A dynamic memory with a serial shift function has a serial output terminal of multiple bits in one element, an odd number of the dynamic memories are provided in one plane, and one multiple bit of the odd number of dynamic memory elements is provided. 2. The raster scan type graphic display device according to claim 1, wherein the serial output of said divider is applied to a distributor, and the output of said distributor is connected to be inputted to a plurality of parallel-serial converters. (3) The raster scan type graphic display device according to claim 2, wherein the distributor is constituted by a tristate gate. (4) A raster scan type graphic display device according to claim 2, wherein the distributor is constituted by a data selector.