JPS62152063A - Bus configuration system for multi-processor system - Google Patents

Abstract

PURPOSE:To package freely memories and I/O as desired into a single CPU by providing the 1st connection means on a single side of the substrate of the CPU together with the 1st and 2nd connection means set on the substrates on the memory and the I/O respectively. CONSTITUTION:A CPU substrate 1-1B is put into a slot formed at the left end of a mother board 8' and fitted to a substrate connector 11-1. Then a memory substrate 5-1B is put into a slot formed at the right of the slot at the left end and fitted to a substrate connector 11-2. At the same time, a connector 12-1 on the substrate 1-1B is fitted to a connector 13-1 on the substrate 5-1B. thus the transfer of signals is possible between a CPU 1-1 and a memory 5-1. Then an I/O substrate 6-1B is put into a slot formed at the right of the substrate 5-1B and fitted to a substrate connector 11-3. At the same time, a connector 12-2 on the substrate 5-1B is fitted to a connector 13-2 on a substrate 6-1B. Thus the transfer of signals is possible among the CPU 1-1, a memory 5-1 and an I/O 6-1. In the same way, the connection of an I/O substrate 6-2B, etc. are also possible.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method of configuring a bus in a multiprocessor system, and particularly to the configuration of an individual bus for each processor.

(Prior Art) FIG. 6 is a block diagram showing an example of the configuration of a general multiprocessor system. In the same figure, 1-1 to 1-4
is a processor (CPtJ), 2 is a common bus connecting cpui to 4, 3 is a system controller (SBC) that controls common bus 2, and 4-1 to 4-4 are corresponding CPUl
-1 to 1-4 are individual buses, and 5-1 to 5-5 are memories connected to the corresponding individual buses 4-1 to 4-4.

6-1 to 6-3 to individual bus 4-1, 6-4 to 6-6 to individual bus 4-2, 6-7 to 6-9 to individual bus 4-3, 6-10 to 6 -12 is an input/output device (Ilo) connected to each individual bus 4-4.

FIG. 7 is an implementation diagram of a conventional multiprocessor system. In this figure, the same reference numerals as in FIG. 6 indicate the same components. 8 is a common bus 2 and an individual bus 4-
A motherboard having a printed pattern of 1 to 4-4, with multiple connectors (not shown) arranged at predetermined intervals in the horizontal direction.
is provided. Reference numeral 9 denotes a rack (casing or rack) having guides 9a on the upper and lower surfaces for inserting and fixing printed circuit boards in accordance with the spacing between the connectors of the motherboard 8, and the motherboard 8 is attached to the rear thereof. IO is a printed circuit board (module) that is modularized into component units such as CPU t-i to 1-4.5BC3 and memories 5-1 to 5-3 described in FIG. As shown in FIG. 7, each printed circuit board IO is inserted from the front side of the rack 9 along the guide 9a, and its tip is connected to the connector of the motherboard 8, thereby connecting the common bus 2 and the individual bus 4-1. - Connected to 4-2.

FIG. 8 is a conceptual diagram of the mounting seen from the front side of the rack 9 of FIG. 7. Here, each area of the rack 9 into which the printed circuit board IO of each component of the multiprocessor system is inserted is defined as a slot. As shown in FIG. 8, each slot is given a slot number, and this rack 9 has 30 slots (slots) with slot numbers O to 29. Slot numbers 0 to 2 have 5BC3 and common memory 7
By inserting each printed circuit board IO of the CPU 1-1 and coupling it to the connector of the motherboard 8, the 5BC 3, the common memory 7, and the CPU 1-1 are connected to the common bus on the motherboard 8.

Further, CPU1-1 is also connected to an individual bus 4-1 on the motherboard 8. The slots with slot numbers 3 to 6 have memories 5-1. By connecting each printed circuit board lO of t106-1 to t106-6-3 to each connector of the motherboard 8 in the same way, the CPU lO on the motherboard 8
-1 individual bus 4-1. Slot number 7.
Slot 8 is empty. Similarly, slot numbers 9 to 13 have CPU1-2 and memory 5-2゜r1.
Each printed circuit board 10 of 06-4 to 6-6 is connected to each connector of the motherboard 8, and is connected to an individual bus 4 of the CPU1-2.
-2. Similarly, CPUs 1-3 . Memory 5-3. l106-
7 to 6-9 to individual bus 4-3, slot number 2:l
~27 CPU 1-4. Memory 5-4. l106-
10 to 6-12 are respectively connected to the individual bus 4-4. In the individual buses 4-1 to 4-4 with such a configuration, seven slots correspond to one individual bus, and the l slot corresponds to C.
Since it is used by PU, the remaining 6 slots are used for memory and [10
and use it.

FIG. 9 is a pattern diagram on the motherboard 8 viewed from the rear surface of the rack 9, and shows portions corresponding to slot numbers 7 to 11. The patterns of the individual buses 4-1, 4-2 are disconnected between the slots numbered 8 and 9, but the pattern of the common bus 2 is connected to all the slots.

In a multiprocessor system as shown in Figure 6, each C
Various tasks can be performed by Ilo connected to the individual buses 4-1 to 4-4 of the PU. The Ilo used here is classified by the type of target work, for example, in the communication field, line type, transmission control procedure, communication speed, etc., and the system is configured by inserting the Ilo of the necessary function into the slot. The individual bus has a configuration (slot free) in which any combination of Ilo's can be inserted to configure an optimal system according to the user's required specifications. The memory can also be installed anywhere within the individual bus as long as the slots allow so that the memory capacity required for each CPU can be installed.

In addition, in the multiprocessor system shown in Fig. 6, CPU4
-1 to 4-4 The configuration has a maximum of 4 printed circuit boards, but in the case of less than this, that is, in the case of only 3, 2, or 1, the rack 9 is the same and only the number of mounted boards is reduced. There is a need for a multiprocessor system that has a high degree of freedom in system design and is expandable so that it can be easily expanded on-site even after delivery to the user.

(Problems to be Solved by the Invention) However, the bus configuration method of the multiprocessor system has the following problems.

Since the individual buses 4-1 to 4-4 of each CPUl-1 to 1-4 are a fixed pattern on the motherboard 8, the number of CPUs is determined by the number of individual buses, and it is impossible to increase the number of CPUs further. there were. In addition, if you want to connect devices such as memory or l10 in excess of the maximum number that can be connected to the individual bus of one CPU, the individual bus will have a fixed pattern even if there are empty slots connected to other individual buses. Therefore, it was not possible to connect a device to that empty slot.

The present invention solves the above-mentioned problems and provides flexibility in that devices can be connected to the individual bus of one CPU within the maximum number of slots in the rack, and the number of CPUs can be freely set. The purpose is to provide a bus configuration method for a multiprocessor system with a high degree of flexibility.

(Means for Solving the Problems) In order to solve the above problems, the present invention provides a common bus that connects a plurality of processors, and an individual bus that connects devices to be controlled by each of the processors. , the processor and the device are each mounted on a board, and these boards are accommodated in areas separated by a predetermined interval of a housing with the board surfaces facing each other and connected to the common bus and the individual bus. In the multiprocessor system configured by the above-mentioned device, a first connection means is provided on one side of the substrate of the processor to connect an individual bus of the processor to a substrate accommodated in an adjacent area, and the device to be controlled The board is provided with a first connection means and a second connection means connected to each other on separate surfaces, which are connectable to the board housed in an adjacent area, and are adjacent to the area where the processor board is housed. This is a bus configuration method for a multiprocessor system in which the boards of the devices to be controlled by the processor are sequentially accommodated from the area where the processor is to be controlled, and when the boards are accommodated, the first connection means and the second connection means are combined to form an individual bus.

(Function) According to the present invention, since the bus configuration method of the multiprocessor system is configured as described above, the technical means functions as follows. First, the processor (CPU) board is
For example, it is accommodated in an arbitrary area (slot) of a housing (rack) with the substrate surface provided with the first connection means on the right side, and connected to the common bar support. Next, in an area adjacent to the right side of the area where the CPU board is accommodated, the board of the device to be controlled (for example, memory or l10) is also placed with the board surface provided with the first connection means on the right side (therefore, The second connection means is housed on the left side). As a result, the first connection means (for example, a female connector) of the CPU board and the second connection means (for example, a male connector) of the device to be controlled are coupled, and the individual bus of the CPU is connected to the device to be controlled. connected to the device. Similarly, the board of the next device to be controlled is accommodated in an area adjacent to the area where the board of the previous device to be controlled is accommodated, and is individually connected by coupling the first connection means and the second connection means. A bus is formed and the previous individual bus is extended. in this way,
Since the individual buses are extended in accordance with the number of boards of the devices to be controlled, a desired number of devices to be controlled can be connected to the individual buses of the CPU. Furthermore, the CPU board can be accommodated in any area. Therefore, the number of CPUs can also be changed freely. Therefore, the problems of the prior art described above can be solved.

(Embodiment) FIG. 1(a) is a mounting diagram showing a first embodiment of the present invention, in which each printout corresponds to a part of the motherboard 8' attached to the rack 9 described in FIG. This shows the connection state of the board. This motherboard 8° has a pattern of only the common bus 2. 1-IB and 1-2B are CPU1-1 and 1 of the multiprocessor system shown in FIG. 6, respectively.
A CPU board, which is a printed circuit board on which -2 is mounted, 5-
IB, 5-2B are memories 5-1. Memory 5-2
Memory board, 6-IB, which is a printed circuit board on which is mounted
6-4B are I10 boards which are printed circuit boards on which I106-1 to 6-4 are mounted, respectively. 11-1~1
1-8 is a board connector that connects the motherboard 8゛ and each board. By inserting the board in the direction of arrow a, the terminals (contacts) provided at the tip of the board come into contact with the contacts of the connector, and the motherboard This allows signals to be exchanged between the common bus 2 on the board 8' and devices mounted on the board. 1
2-1 to 12-8 are connectors F (female) provided on one side of each board to configure individual buses; CPU boards 1-IB to 1-2B and memory boards 5-IB to 5-2B. and I10 boards 6-IB to 6-4B. In each of these boards, the pin 12a of the connector (F) 12 (described later) and the CPU mounted on the board
l-1, 1-2, memories 5-1 to 5-2. l106-1
The devices 6-4 are connected to each other using patterns on the board.

13-1 to 13-6 are connectors (F) 12-1 to 12-
Connector M (
(male), and is attached only on multiple sides of memory boards 5-IB to 5-2B and I10 boards 6-IB to 6-4B. On each of these boards, the connector (
F) Pin 12a of 12 and the connector attached to the other side (
It is connected to pin 1:lb (described later) of M) 13 by a pattern on the board.

FIG. 1(b) is a perspective view of the connector (F) 12 and the connector (M) 1 for connecting the individual buses described above. The connector (F) 12 and the connector (M)+3 have an elongated substantially rectangular parallelepiped shape. The connector (F) 12 is arranged in the longitudinal direction on one side, and as shown in FIG. , and longitudinally arranged sockets 12b on adjacent surfaces. Connector (M) 13 has socket 12 of connector (F) 12 on one side.
The connector (M) 13 has a plurality of pins 13a that can be fitted into the connector (M) 13b, and a plurality of pins 13b that connect to the pattern on the board when the connector (M) 13 is attached to the board on the adjacent surface.

Next, the mounting procedure will be explained using FIG. 1(a).

First, CPU1- of the multiprocessor system shown in FIG.
1 individual bus 4-1 with memory 5-1゜l106-1~6
Consider the case where -3 is connected.

As shown in FIG. 1(a), the CPU board 1-IB is inserted into the left end slot and fitted into the board connector 11-1. As a result, it is connected to the common bus 2 on the motherboard 8° via the CPU1-1 in the CPU&board 1-IB and the board connector 11-1. Next, insert the memory board 5-IB into the slot to the right of the slot in which you inserted the CPU board 1-IB.
is inserted and fitted into the board connector 11-2. At the same time, connecter (F) 12-1 on CPU board 1-IB.
and the connector (M)+3-1 on the memory board 5-IB are fitted together. As a result, connector (F) 12-1 and connector (
M) +3-1.

Therefore, the CPU 1-1 and the memory 5-1 can exchange signals through the formed individual bus 4-1. continue,
Insert the I10 board 6- into the slot to the right of the memory board 5-IB.
Insert the IB and fit it into the board connector 11-3, and also fit the connector (F) 12-1 on the memory board 5-IB with the connector (M) 13-2 on the I10 board 6-IB. . As a result, the connection between the memory 5-1 of the individual bus 4-1 and the connector (F) 12-2 and the connector (
Connector (M) 13 formed by M) 13-2
-1 and connector (F) 12-2 are memory board 5-IB
Since the connection is made with the upper button, the individual bus 4-1 is extended. Therefore, CPU1-1, memory 5-1 and [
106-1, it is possible to send and receive signals through the formed individual bus 4-1. In this way, the I10 board 6-
By sequentially inserting 2B and 6-3B into the slots,
Individual bus 4-1 is CPU l-1, memory 5-1 and l1
It is formed between 06-1 and 06-3.

Now that the connection of the individual bus 4-1 of CPUl-1 has been completed, the slot to the right of the I10 board 5-3, which is the last Ilo, is the CPU in which the next CPUl-2 is mounted.
Insert board 1-2B.

Since the CPU board 1-2B does not have a connector that connects to the board on the left side of the slot, the individual bus 4-1 of the CPU 1-1 and the individual bus 4-2 of the CPU 1-2 are separated here.

Similarly, there are no empty slots within the range where the individual buses are connected in order from the left, such as the memory board 5-2B and the I10 board 5-4B, which are connected to the individual bus 4-2 of CPU1-2. Implement left-aligned.

FIG. 2 is a conceptual diagram when the method of the present invention described above is applied to the multiprocessor system of FIG. 6. This figure shows slot numbers 0 to 29, 3, as in the conventional case shown in FIG.
0 slot configuration. Since the slots are filled in order starting from the left slot, the slots that were previously empty on each individual bus are concentrated on the right, and slot numbers 22 to 29 become empty slots.

FIG. 3 is an example in which the number of CPUs is reduced and, instead, more memory and Ilo are mounted on the individual bus of one CPU.

Slot number? Individual bus 4 from i2 to slot number 12
-5. Individual buses 4-6 are formed for slot numbers 13 to 23. Such an implementation is one C
This is possible when the PU has a large capacity and the Ilo processing speed is slow compared to it, and in the communications field, this corresponds to the I10 control unit that supports devices with slow line speeds.

Since the cost of the CPU board is higher compared to such Ilo etc., it is necessary to reduce the CPU board as much as possible and use the memory and Ilo.
A method of implementing O to the maximum support capacity of the CPU is also often used.

FIG. 4 is an implementation diagram showing a second embodiment of the present invention. The figure shows that in the first embodiment, the common bus 2 was realized by a motherboard 8° of a printed circuit board, but a connector 15 is provided on each board, and the connectors 15 are connected with a flat cable to form a common bus. It is something. 16 in the figure is a common bus using a flat cable.

FIG. 5 is a perspective view showing a second embodiment of the present invention, as seen from the rear surface of the rack 9. FIG.

(Effects of the Invention) As described above in detail, according to the present invention, in a multiprocessor system having one common bus and a plurality of individual buses depending on the CPU, the board of the CPU is When either a memory or Ilo board is inserted into the adjacent slot facing that side on one side, the first connection means to which the individual bus connects, and the memory and Ilo board are inserted. A first connection means and a second connection means that connect to the memory or Ilo board on both sides of the slot when the
Since we have provided a connection means, as long as it is within the maximum number of slots in the rack, it is possible to install as much memory and Ilo as you like for one CPU, and the number of CPUs to be installed can be freely set. can be expected. Furthermore, in systems that use a motherboard, compared to conventional systems, only the common bus pattern needs to be connected to the motherboard, so the connector for the motherboard can be small, and the motherboard itself can be expected to be effective without being small.

[Brief explanation of drawings]

1(a) and 1(b) are implementation diagrams showing the first embodiment of the present invention, FIG. 2 is a conceptual diagram of implementation when the method of the present invention is applied to the system of FIG. 6, and FIG. 3 is a conceptual diagram of implementation when the number of devices per individual bus is increased, FIG. 4 is an implementation diagram showing the second embodiment of the present invention, FIG. 5 is a perspective view of the second embodiment, and FIG. The figure is a configuration diagram of a general multiprocessor system, Figure 7 is an implementation diagram of a conventional multiprocessor system, Figure 8 is a conceptual diagram of the implementation seen from the front of a conventional rack, and Figure 9 is a diagram of a conventional rack. It is a pattern diagram of the motherboard seen from the back side. 1-1 to 1-4-... Processor (CPU) 2... Common bus 3... System controller (SBC) 4-1 to 4-
4... Individual buses 5-1 to 5-5-, memory 5-IB to 5-5B... memory board 6-1 to 6-12... input/output device (I 10 > 6-
IB~6-12B...f10 board 7...Common memory 8°...Motherboard 9...Rack 11-1 to 11-8-...Board connector 12: 12
-1 to 12-8... Connector (F) 13; 13-
1-13-8... Connector (M) + 5-... Connector 16... Flat cable

Claims (1)

[Scope of Claims] A common bus that connects a plurality of processors, and an individual bus that connects devices to be controlled by each of the processors, and the processors and devices are each mounted on a board, and these In a multiprocessor system configured by accommodating substrates in areas separated by predetermined intervals in a housing with the substrate surfaces facing each other and coupling them to the common bus and the individual buses, one side of the substrate of the processor is provided. is provided with a first connection means capable of connecting the individual bus of the processor to a board housed in an adjacent area, and a first connection means connectable to the board housed in an adjacent area, and a first connection means connectable to the board of the device to be controlled. , the first connection means and the second connection means connected to each other are provided on different surfaces, and the substrates of the devices to be controlled by the processor are sequentially accommodated from the area adjacent to the area accommodating the substrate of the processor, A bus configuration method for a multiprocessor system, characterized in that an individual bus is formed by combining a first connection means and a second connection means when accommodated.