JPS62152044A - Control method for hardware timer - Google Patents

Abstract

PURPOSE:To improve the throughput of a system by using the hardware function to perform the request for start of a timer, the control of the timer and the management of the timer and therefore omitting a fixed interruption for control of the timer and also decreasing the generating frequency of instructions. CONSTITUTION:The set value of a timer is set to a register 12 with the first timer start request and a counter 11 starts its action. If no timer start request is received while the counter 11 is working, an interruption request is produced from a comparator 14 when the count value of the counter 11 reaches the set value. While the count value is subtracted from the set value of the register 12 and the remaining time value is obtained when a timer start request is received during the working of the timer 11. Then the obtained time value is compared with the timer set value obtained by a new timer start request. If the new set value is smaller than the old set value, the timer set value stored in the register 12 is saved temporarily, and the count value of the timer 11 is added to the value set newly by a timer start request. Thus the new set value is set to the register 12.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for controlling a timer mechanism in an information processing device that logically multiplexes a single hardware timer, and particularly relates to a method for controlling a timer mechanism that logically multiplexes a single hardware timer in an information processing device. This invention relates to a hardware timer control method that can significantly reduce the frequency of count control interrupts and improve system throughput.

[Prior Art] Conventionally, as a control method for a timer mechanism that logically multiplexes a single hardware timer, interrupts are generated at fixed time intervals regardless of the set time of the timer, and the information on the control table is The set time of each software timer registered in is subtracted, and when the value becomes [0], a timeout is detected.

However, the conventional timer control means as described above suffers from the following drawbacks.

That is, in the above-mentioned timer control means, the fixed time @
Since the configuration is such that an interrupt is explicitly generated and the set time of the software timer placed on the control table is subtracted, regular interrupts are required at fixed time intervals, and therefore the set time unit is made smaller. The more interrupts are taken, the more interrupts occur, resulting in a decrease in system throughput.

[Problems to be Solved by the Invention] The present invention significantly reduces the frequency of occurrence of interrupts for timer count control in a timer mechanism that logically multiplexes a single hardware timer. The present invention provides a hardware timer control method that can improve system throughput.

[Means and effects for solving the problems] The present invention includes a register for storing timer setting values, a counter for performing time counting in response to a time signal at a constant timing, and a count value of this counter that is equal to the setting value of the register. In addition to preparing timer hardware consisting of a comparator that generates an interrupt request when the above-mentioned counter is performing counting operation, when a timer start request occurs, the setting value stored in the above-mentioned register is The value of the remaining count time obtained by subtracting the current count value of the counter from the above is compared with the new setting value according to the above request, and if the new setting value is smaller than the remaining time value, it is stored in the register. a control means that saves the current set value as a timer count wait state, and sets a value obtained by adding the count value of the counter to the new set value in the register as a new comparison target; When the value of the remaining time is greater than the value of the remaining time, the new set value is saved as a timer count waiting state, and the count value of the counter is used as a comparison target without being changed; and an interrupt request is made from the comparator. means for initializing the counter, searching for the minimum timer setting value from among the timer setting values in the timer count waiting state, and setting the same timer setting value in the register as a new comparison target when the timer setting value occurs. This system performs timer control and timer management for each timer activation request, thereby making effective use of the above hardware functions and controlling the interrupt occurrence tendency without requiring constant interrupts for timer control. This can be significantly reduced, and the system throughput can be improved accordingly.

[Example] An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a hardware configuration for realizing an embodiment of the present invention.

In FIG. 1, numeral 11 is a count register that increases by +1 in response to a time signal (Tp) from a hardware circuit (not shown), and is hereinafter simply referred to as a counter. Reference numeral 12 denotes a maximum value register that stores a timer setting value (that is, the maximum value that the counter 11 should reach) in accordance with a timer activation request, and is hereinafter simply referred to as a register.

Reference numeral 13 denotes a control register for starting/stopping the counter 11. Reference numeral 614 compares the count value of the counter 11 with the set value of the register 12, and determines whether the count value of the counter 11 reaches the set value of the register 12. This is a comparator that generates an interrupt request (IRQ) based on the IRQ.

FIGS. 2 to 7 are for explaining the operation of the above embodiment, respectively. FIGS. 2 to 5 are for explaining the time relationship between each timer element, and FIGS. Each figure is a flowchart showing the operation processing flow. Of these, FIGS. 2 and 3 show cases in which a new timer activation request occurs while the counter 11 is executing a counting operation using the set value stored in the register 12 as the final count value. Each time value is shown in FIG.
This is a case where the remaining time value TL after subtracting the count value of TL is longer than the remaining time value TL (TL > T2), and in FIG.
This is a case where the time is longer than the remaining time value TL obtained by subtracting the count value of the main memory 11 from the set value of 2 (TL<T2). Here, in the case of FIG. 2 (that is, when TL>T2), the timer setting 1a of the communication channel 12 is changed,
In the case of FIG. 3 (ie, TL≦T2), the timer setting value is not changed.

4 and 5 show changes in the setting states of the counter 11 and the register 12 when an interrupt occurs and after the interrupt occurs.
An interrupt request from the comparator 14 when the count value reaches the set value of the register 12 (when IRQ>output), Figure 5 shows the result after the interrupt has occurred, and Tr, T2, and T3 are each caused by a timer activation request. Indicates the timer setting value.

Further, FIG. 6 shows the processing flow when a new timer activation request is made in the above embodiment, and FIG. 7 shows the processing flow when an interrupt request (IRQ) is generated. In the figure, Tc is the timer setting value (stored in counter 11) that is compared with the current timer count, TN is the timer setting value due to a new timer activation request, and To is temporarily saved as having the timer count. The timer setting value, C is the count value of the counter 11, and R is the setting value of the register 12.

Here, the operation of one embodiment will be explained without reference to the above figures.

In the initial state, the counter 11 stops counting under the control of the control register 13. Therefore, the comparator 14 does not generate an interrupt request (IRQ>).

At the first timer activation request, the timer setting value is registered in register 1.
2, and the counter 11 starts counting.

Here, if there is no timer activation request while the counter 11 is executing the counting operation, the count value of the counter 11 reaches the set value of the register 12, and the comparator 1
An interrupt request (IRQ> is generated from 4).

Further, when a timer activation request is received while the counter 11 is performing a counting operation, the process shown in FIG. 6 is executed.

This process first calculates the remaining time value (TL) by subtracting the count value (C) of the counter 11 from the set value of the register 12<Tc, and then calculates the remaining time value (TL).
(TL) and the timer setting value (TN) based on the new timer activation request.

Here, the timer setting value (T
N) is smaller than the remaining @darkness value (TL) (TN<TL
), the timer setting stored in register 12 [
(Tc) is temporarily saved as a timer count waiting state (To +Tc), and the count m of the counter 11 is set to the timer setting l1a (TN) by a new timer activation request.
A new timer setting value including (C) is set in register 12 (R4-TN 10).

As a result, from now on, timer counting is started using the timer setting value (TN) based on a new timer activation request.

The time relationship of each timer element at this time is shown in FIG. Here, timer setting 1i by new timer start request
fi(TN) is indicated by T2.

Also, the timer setting value (T
N) remains fi! III (TL) is larger (T
When N > TL), the timer setting value (TN) due to a new timer activation request is temporarily saved as a timer count wait state (To 4-TN), and the timer count continues with the current timer setting 1ifl (Tc). do.

The time relationship of each timer element at this time is shown in FIG.

Next, when the count value of the counter 11 reaches the setting of the register 12 and an interrupt request (IRQ> is generated from the comparator 14), the processing shown in FIG. 7 is executed.

This process begins with the temporarily saved timer setting fi1 (
To) is the count value (C) of the counter 11, respectively.
(To←To−C), and then the counter 11 is initialized (cleared).

Then, each timer setting value (To) is temporarily saved.

), the smallest setting value is searched and set in the register 12 as a new timer setting value.

As a result, a new timer count is started again using the temporarily saved timer setting value.

The counter 11 when an interrupt request (IRQ) is generated at this time,
FIG. 4 shows the states of the register 12 and the register 12, and FIG. 5 shows the same state after the occurrence of the same side interference.

Note that each timer setting value (To,
To,...) to T1. They are shown as T2 and T3.

The above-mentioned process is repeatedly executed for each event occurrence,
The timer functions by logically multiplexing a single hardware timer.

Since the timer processing is executed as described above, it is not necessary to interrupt at regular intervals, and the frequency of occurrence of interrupts can be reduced to improve the throughput of the system.

Incidentally, in the embodiment described above, the counter 11 is connected to the time signal (Tp
), but for example, when starting a timer, a set value is set in the counter,
When the timer starts, the counter 11 is sent to the time signal (Tp).
The same timer operation as in the above embodiment can also be realized by using a configuration in which the count is subtracted according to the number of seconds.

[Effects of the Invention] As detailed above, according to the hardware timer control method of the present invention, in a timer mechanism that logically multiplexes a single hardware timer, a register for storing timer setting values is used. In addition, we prepare timer hardware consisting of a counter that performs time counting in response to a time signal at a fixed timing, and a comparator that generates an interrupt request when the count value of this counter reaches the set value of the above register. , When a timer start request is generated while the above counter is executing a counting operation, the value of the remaining count time obtained by subtracting the current count value of the above counter from the set value stored in the above register and the new setting according to the above request. If the new set value is smaller than the remaining time value, the set value stored in the register is saved as a timer count wait state, and the counter is set to the new set value. a control means for setting the added value in the register as a new comparison target; and when the new set value is larger than the remaining time value, the new set value is saved as a timer count waiting state; A control means that uses the count value of the counter as it is for comparison without changing it, and when an interrupt request is generated from the comparator, initializes the counter and calculates the minimum value from each timer setting value in the timer count waiting state. means for searching for a timer setting value and setting the same timer setting value in the register as a new comparison target;
By executing timer control and timer management for each timer activation request, the above hardware functions can be effectively used, and the frequency of interrupts can be significantly reduced without the need for constant interrupts for timer control. Accordingly, the system throughput can be improved.

[Brief explanation of drawings]

The figures are for explaining one embodiment of the present invention, and FIG. 1 is a block diagram showing the hardware configuration, and FIGS.
Each figure is a diagram for explaining the time relationship between each timer element, and FIGS.
This is flowchart 1. 11... Counter (count register), 12...
Register (maximum value register), 13... control register, 14... comparator. Applicant's agent Patent attorney Takehiko Suzue Figure 4
Figure 5 Figure 6 Figure 7

Claims (1)

[Claims] A timer mechanism that logically multiplexes a single hardware timer includes a register that stores timer setting values, a counter that performs time counting in response to a time signal at a fixed timing, and a register that stores timer setting values. It has a comparator that generates an interrupt request when the count value of the counter reaches the set value of the above register, and when a timer start request occurs while the above counter is performing counting operation, the timer start request is stored in the above register. The value of the remaining count time is calculated by subtracting the current count value of the counter from the set value, and the value of the remaining count time is compared with the new set value based on the above request, and the new set value is determined as the remaining time. When the value is smaller than the value, the set value stored in the above register is saved as a timer count wait state, and the value obtained by adding the count value of the above counter to the new set value is set in the above register as a new comparison target. However, when the new set value is greater than the remaining time value, the new set value is saved as a timer count wait state, and the count value of the counter is used as a comparison target without changing, and the comparator When an interrupt request is generated, the above counter is initialized, the minimum timer setting value is searched from among the timer setting values waiting for the timer count, and the same timer setting value is set in the above register as a new comparison target. How to control the hardware timer.