JPH02114360A - Clock synchronizing method for multiprocessor system - Google Patents

Abstract

PURPOSE:To allow the clocks of all processors to point out the same time within the range of a certain synchronizing accuracy by allowing each processor to control its own clock based upon all clock information arriving every generation of a time interruption. CONSTITUTION:After measuring a random time within a previously determined time range, a timer generates a time-out, each of processors 301 to 305 starts the timer at the time of a generation of a time interruption. When the time-out generating time is before the generation of a time interruption, each of the processors 301 to 305 sends its own clock shown in its parentheses to all the processors 301 to 305 at the time of generating a time-out. In addition, each of the processors 301 to 305 controls its own clock based upon all clock information arriving every generation of a time interruption. Even when the number of processors in the system is increased, the increment of processing overhead due to the sharp increment of the number of communication message is not generated and the total number of messages in the system can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention is a multiprocessor system in which each processor does not have a shared memory that can be accessed in common, and in which each processor mutually adjusts the clocks that each processor has to indicate time. This paper relates to a clock synchronization method for

[Conventional technology]

In a multiprocessor system, it is necessary to synchronize the clocks of each processor that makes up the system so that they indicate a common time for the entire system.For example,
In a distributed filing system, a common time is required between each processor in order to identify a file version based on the creation and editing times recorded in each file. In addition, if each processor accumulates its own history information based on a time common to the system, it will be possible to know the order in which failures were detected when they occur, and to identify the location of the failure. You can obtain useful information for this purpose.

Even in a communication network system, which is an example of a multiprocessor system that does not have a shared memory, a synchronization method is required so that the clocks of each communication node indicate a common time. For example, at the 6th International Conference on Distributed Computing Systems held in May 1986,
e on DI STRI BUT EDCO
MPUTING SYSTEMS) Proceedings 2゜36
4-371, the paper “An Election Algorithm for Distributed Clock Synchronization Programs (An
Election Algorithm for a
Distributed C1ock 5syncron
The clock synchronization method TEMPO introduced in the document 1 (Reference 1) is compatible with UNIX
It is implemented in a network running on operating system 4.38SD. In the above system, one node serving as a mask is
Time queries are made to all nodes at predetermined intervals, and an average time is calculated based on the determined times of each node. Thereafter, a clock adjustment instruction is given to all nodes, and each node adjusts its clock according to this instruction.

In addition, the 16th Annual International Symposium on Fault-Tolerant Computing (Annual Intel) was held in 1986.
National Symposium on
FAULT-T.

The paper ``Clock Synchronization in the Presence on Omission and Performance Faults and Processor Joins (CLO
CK 5YNCHRONIZATION IN THE
PRESENCE OF 0Ml5SION AND
PERFORMANCE FAULTS, ANDPR
The clock synchronization method introduced in OCESSORJOINS) J (Reference 2) is
It uses distributed control rather than masked slave type control like MPO'''. In this method, the processor selects the earliest time among the synchronization messages that are periodically broadcast within the system. The clocks are time-synchronized according to the synchronization message shown, and as a result, the clock that advances fastest controls the time within the system.

In addition, the Journal on Association for Computing Machinery (J.

Urnal of As5ocation for
Computing Machinery), Vol.
32. No, 1. January 1985. p.52
-78, the paper “Synchronizing Clocks in the Presence on Faults”
Synchronizing C1ocks in t
The clock synchronization method introduced in ``He Presence of Faults'' (Reference 3) is a synchronization method using completely distributed control in which all processors periodically communicate the time of each other's processors [Problem to be solved by the invention] ] UNIX operating system 4.3BS mentioned above
In D's TEMPO synchronization method, a master node is essential. Therefore, in the event of a failure of the master node, a method of acting as a master node is required so that another node can perform the function of the master node. In addition, since one master node queries the clocks of all nodes, as the number of nodes increases, the amount of communication to the master node increases, and the task of calculating the average time of all nodes increases. do.

On the other hand, in the method described in Document 2 that employs distributed control, although it is distributed, one processor with the fastest clock controls the time within the system. Further, in the method of Document 3, since all processors communicate with each other, communication overhead becomes a problem when applied to an actual system.

An object of the present invention is that there is no need to provide a processor for centralized control, so that one processor does not control the time in the system, and even when the number of processors in the system increases, the number of communication messages can be reduced. An object of the present invention is to provide a clock synchronization method in a distributed control multiprocessor system, which is capable of reducing the total number of messages in the system compared to conventional methods without excessively increasing processing overhead.

[Means to solve the problem]

According to the present invention, in a clock synchronization method for a multiprocessor system consisting of n processors, each processor has a clock indicating the time, a timer measuring random time, and means for generating time interrupts at predetermined intervals. The timer times out after measuring a random time within a predetermined time range, and in each of the processors, when the time interrupt occurs, the timer is started, and the time when the timeout occurs is set as the time. If it is before an interrupt, the clock will be sent to all processors at the time when the timeout occurs, and each processor will transmit its own clock based on all the clock information that arrives each time the time interrupt occurs. A clock synchronization method for a multiprocessor system is obtained, which is characterized by controlling the clock of the multiprocessor system.

[Effect]

In a multiprocessor system that does not have a shared memory that can be commonly accessed by each processor, the clocks of each processor do not indicate the same time when the system is in an initial state. Moreover, although clocks that start from the same value measure time at roughly the same rate, they gradually shift as time passes. Therefore, each processor needs to adjust the clocks of each other through message communication according to this synchronization method described below.

As a result, the clocks of all processors are controlled to point to the same time within a certain synchronization accuracy.

The principle of the present invention will be explained with reference to FIGS. 2 and 3. FIG. 3 shows a specific example of a multiprocessor system. Each processor 301, 302. 303, 304.
305 is provided with a clock that indicates its own time, and generates a time interrupt based on its own clock. Furthermore, each processor is connected to each other by a logical communication path so that clock information can be notified to any processor. For example, processor 303 and processor 304 are connected by a communication path 306.

Furthermore, each processor is equipped with a timer capable of measuring random time, and can measure random time within a predetermined time range.

FIG. 2 shows a timing chart for a certain processor i, and describes the principle of the clock synchronization method of the present invention while explaining the operations of the above-mentioned time interrupt and random timer.

In FIG. 2, the time from one time interrupt to the next time interrupt is the clock synchronization control period, which is, for example, one hour in this example. Now, as shown in the figure, k
The time interrupt indicating the start of the clock synchronization control period at address k is set to O:00, and the time interrupt indicating the end of the clock synchronization period at address k and the start of the (k+1)th clock synchronization period is set to 1:00. On processor i, 0:
When a time interrupt of 00 is detected, the timer is activated. For example, assume that a timer is set so that a timeout occurs at a random time within 360 minutes. In this way, from the time interrupt at 0:00,
The probability that a timeout occurs during the time interrupt is 1/
It becomes 6. All processors in the network independently perform the same timer activation and random timeout generation processing, so if the total number of processors in the network is n, in the above example, on average, n / 6 processors perform the clock synchronization control period. A timeout will occur in between.

In Fig. 2, timeout example 1 is an example in which a timeout occurs during the clock synchronization control period.
Timeout example 2 is an example in which a timeout occurs after the (k+1)th time interrupt. However, since the timer is actually restarted at 1:00, the timer started at 0:00 will not time out after 1:00.

In the method of the present invention, as shown in timeout example 1 above, only when a timeout occurs during the clock control period, clock information at that time is sent to all processors at the time when the timeout occurs. be. On the other hand, in each processor, reception processing is performed on clock information that has already arrived before each time interrupt occurs.

This synchronization method will be explained using the network example shown in FIG. In the explanation, the number of time interrupts in each processor is 1:
Set to 00. When each processor detects a time interrupt from its own processor, it starts a timer, and if the timeout is before 1:OO as measured by its own clock, it notifies all processors of clock information stamped with the time when the timeout occurred. . In addition, for a processor that receives a clock before 1:00, the difference is calculated between all the received clock values and the time of the own processor that received the clock value, and the clock is adjusted using the average value Δ of the differences. be. That is, if Δ is positive, add Δ to the own clock value,
If Δ is negative, the own clock is stopped by Δ. Assuming that each processor causes a timeout according to the timeout distribution described earlier, an average of n/6 processors will send their own clock to all processors per control for the total number n of processors. Each processor adjusts its own clock value to the average value of the clock values from n/6 processors.

For example, before the clock control according to the present invention is applied,
It is assumed that each processor has a lock value as shown in FIG. 3(a). Now, assume that processor 301 and processor 302 have caused a timeout before 1:00 of the next clock synchronization control period, and if we check the timeout time of processor 301 using the clock of processor 301 and find that the timeout time of processor 302 is 0:38, then It is assumed to be O:46 based on the clock of the processor 302. Ignoring communication delays and clock deviations caused by the clock inclination of each processor, first, the processor 30
The clock value of 1 reaches 0:38, and the clock value (
0:3g) to all processors.

The time indicated by each processor when the processor 301 sends out its clock value is shown in FIG. 3(b). Figure 3 (
As can be seen in b), the times indicated by each processor are all before 00, and all processors receive clock information from processor 301. When each processor receives the clock value of the processor 301, it calculates the difference between it and its own clock value. The difference value is 0 in the processor 301.
, +6 for processor 302, +6 for processor 303
4, the processor 304 has +8, and the processor 305 has +2. Subsequently, when the clock value of the processor 302 reaches 0:46, it sends out a clock value, and all processors receive the clock value. The times indicated by each processor at this time are shown in FIG. 3(C). In this case as well, the times indicated by each processor are all before 1:00, and all processors are
Receive clock information from 2. The difference value for each processor is -6 for processor 301, and -6 for processor 302.
0 for processor 303, -2 for processor 304,
In the case of the processor 305, the value is +2, and in the processor 305, the value is -4. Therefore,
Each processor takes the average value of the above difference values, and the value is -3 for processor 301 and +3 for processor 302.
, +1 for processor 303, +1 for processor 304
5, it becomes -1 in the processor 305. If the clock value shown above is adjusted based on the average value of the difference values, when a time interrupt of 1=00 occurs in each processor, the clock of the processor 301 will be delayed by 3 minutes, The clock of processor 302 is advanced by three minutes;
It can be seen that the clock of processor 303 is advanced by one minute, the clock of processor 304 is advanced by five minutes, and the clock values of all processors are adjusted to the same value.

The above control is repeatedly performed by all processors according to time interrupts based on their own clocks. Of course, since the timeout time is random for each processor in each clock synchronization period, the processors that send their own clocks and the number of processors in each clock synchronization period are random as a result.

In this way, all processors are on a completely equal footing and implement exactly the same algorithms.

At this time, only the randomly selected processor sends out its clock value, so the amount of communication can be reduced compared to the conventional method. Further, by controlling the system time using the average time of a plurality of processors instead of only one processor controlling the system time, fault-tolerant time control becomes possible. Furthermore, the degree of fault tolerance can be flexibly controlled by changing the probability of timeout occurring between timed interrupts. Also, within a certain range of time to send clock information (clock synchronization control period)
Since the clock information is random, it is possible to reduce the possibility that the network will be congested due to clock information sent by multiple processors.

〔Example〕

FIGS. 1(a) and 1(b) show an example of a flowchart of control executed by each processor to implement the method of the present invention. FIG. 1(a) is a flowchart showing clock information transmission control. As an example, FIG. 1(b) is an example flowchart showing clock information reception control.

First, the transmission control flowchart of FIG. 1(a) will be explained. In each processor, when a time interrupt is detected in block 100, a timer is activated in block 101. Block 102 detects the occurrence of a time interrupt,
If a time interrupt is detected, the transmission control in this synchronous control period is terminated (in other words, the clock information sending processor did not become a processor in this period), the process returns to block 100, and the timer is started again. block 102
If no time interrupt is detected at block 103, it is detected whether the set timer has timed out. If the timeout has not occurred, the process returns to block 102 again to determine if a time-of-day interrupt has been detected.

That is, the loop between block 102 and block 103 continues until either a time interrupt or a timeout is detected, and when a timeout is detected in block 103 (at this time, the timeout is detected before the time interrupt occurs). ), in block 104, clock information stamped with the time when the timeout occurred is sent to all processors (that is, they became clock information sending processors during this clock synchronization control period), and the transmission control during this synchronization control period is performed. Upon completion, the process returns to block 100 and waits for a time interrupt indicating the start of the next synchronous control period.

In the reception control shown in FIG. 1(b), in block 111, clock information transmitted by another processor is received. In the subsequent block 112, the difference between the received clock value and the own clock value is calculated and stored. Block 113
Now, let's determine whether a time interrupt has occurred,
If no time interrupt has occurred, clock information is received again, and this loop is repeated until the reception time window ends. When it is detected in block 113 that a time interrupt has occurred, the process goes to block 114 and calculates the average value of the differences between all the received clock information and its own clock value (calculated in block 112).

In the following block 115, control is switched depending on the sign of the calculated Δ, and if Δ is positive, block 1
In block 16, the own clock is adjusted by adding Δ to the own clock value. If Δ is negative, in block 117, the second clock is stopped by Δ and the own clock is adjusted. When the process of plot 116 or 117 is completed, the reception process in this periodic control period is ended and the process returns to block 110, where reception control in the next clock periodic control period is started.

〔Effect of the invention〕

In this way, by using the clock synchronization method of the present invention, in a multiprocessor system, all processors can operate equally without providing a processor that performs centralized control, and the clocks of each processor can point to a common time. It can be controlled as follows. Processors that perform clock synchronization control are randomly selected for each synchronization control period, and a failure of a particular processor will not cause a fatal failure of the system, ensuring high reliability. Furthermore, the degree of reliability can be flexibly changed by controlling the probability that a timeout will fall within the clock synchronization control interval.

Furthermore, a fixed number of processors is not selected for each synchronous control period, but the number of processors that send out clocks for synchronous control is also random, and is given as an average value for each synchronous control period. It is easy to avoid deadlock situations associated with control. In addition, since synchronous control is not performed using the clock values of all processors, but is performed using the clock values of a partial set of processors, the processing time required for synchronous control even when the number of processors increases. It will not increase significantly.

Furthermore, since the timing of transmitting clock information is randomly distributed during the clock synchronization control period, it is possible to avoid network congestion caused by transmitting clock information.

As described above, the effects obtained by the present invention are significant.

[Brief explanation of the drawing]

FIGS. 1(a) and (b) are flowcharts showing an embodiment of the clock synchronization method according to the present invention, FIG. 2 is a control timing chart of the clock synchronization method according to the present invention, and FIGS. 3(a) and (b). , (c) are diagrams showing an example of a multiprocessor system and an example of time of each processor for detailed explanation of the present invention. 100-104, 111-117... control blocks,
301 to 305... Processor, 306... Logical communication between processor 303 and processor 304 first
Times (,1), Mu! Flash (b) Chiga (wa) Rose, Zosa 3θ / Kayakuni (b)

Claims (1)

[Claims] 1. In a clock synchronization system for a multiprocessor system consisting of n processors, each processor generates time interrupts at predetermined intervals using a clock indicating time and a timer measuring random time. and the timer times out after measuring a random time within a predetermined time range, and in each of the processors, when the time interrupt occurs, the timer is activated and the time at which the timeout occurs is determined. Before the time interrupt occurs, each processor sends its own clock to all processors at the time when the timeout occurs, and each processor sends its own clock to all clock information that arrives each time the time interrupt occurs. A clock synchronization method in a multiprocessor system, which is characterized by controlling each clock based on the system. 2. In the clock control of each processor, if the average time of all the received clock information is Δ ahead of the time indicated by its own clock, add Δ to its own clock, and set the average time to its own clock. In the multiprocessor system according to claim 1, the clock in the multiprocessor system according to claim 1 is characterized in that when the timer is delayed by Δ from the time indicated by the clock, the clock stops its own clock until the timer notifies that the time Δ has elapsed. Synchronous method.