JPS62151283U - - Google Patents
Info
- Publication number
- JPS62151283U JPS62151283U JP3631386U JP3631386U JPS62151283U JP S62151283 U JPS62151283 U JP S62151283U JP 3631386 U JP3631386 U JP 3631386U JP 3631386 U JP3631386 U JP 3631386U JP S62151283 U JPS62151283 U JP S62151283U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- circuit
- digital video
- output
- signals
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000003111 delayed effect Effects 0.000 claims 4
- 239000000284 extract Substances 0.000 claims 2
- 230000010354 integration Effects 0.000 claims 2
- 238000005070 sampling Methods 0.000 claims 2
- 238000000926 separation method Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
- 238000000605 extraction Methods 0.000 description 1
Landscapes
- Picture Signal Circuits (AREA)
- Processing Of Color Television Signals (AREA)
Description
第１図はこの考案の一実施例を示す回路図、第
２図は従来のデジタルビデオ処理回路を示す図で
ある。
２０１……アナログデジタル変換器、２０４…
…遅延回路、３０１……減算器、３０２……信号
抜き取り回路、３０３……リミツタ、３０４……
絶対値回路、３０５……積分回路、３０６……時
定数回路、３０７……マイクロコンピユータ。
FIG. 1 is a circuit diagram showing an embodiment of this invention, and FIG. 2 is a diagram showing a conventional digital video processing circuit. 201...Analog-digital converter, 204...
...Delay circuit, 301...Subtractor, 302...Signal extraction circuit, 303...Limiter, 304...
Absolute value circuit, 305...integrator circuit, 306...time constant circuit, 307...microcomputer.
Claims (1)
オ信号が供給され、順次１水平周期ずつ時間のず
れた複数の遅延デジタルビデオ信号を出力する遅
延回路と、 前記複数の遅延デジタルビデオ信号を用いて、
輝度信号、色度信号を分離抽出する輝度・色度分
離回路と、 前記複数の遅延デジタルビデオ信号のうち、バ
ースト信号が同相の関係にある２つの遅延デジタ
ルビデオ信号が供給され、差分信号を得る減算器
と、 前記差分信号の中から前記バースト信号期間の
信号を抜きとる抜き取り回路と、 前記抜き取り回路の出力をリミツタにて所定の
値に制限したものを全て一方の符号の値の信号に
変換する絶対値回路と、 前記絶対値回路の出力信号を入力とし１バース
ト期間積分して出力するバースト積分回路と、 前記バースト積分回路の出力信号を入力とし、
所定の時定数を持たせて出力する時定数回路と、 前記時定数回路の出力がノイズの大きいことを
示す場合と小さいことを示す場合とで入出力特性
が制御されるデジタルビデオ処理部とを具備した
ことを特徴とするデジタルビデオ信号処理回路。[Claims for Utility Model Registration] A delay circuit that is supplied with a digital video signal obtained by quantizing an analog video signal and outputs a plurality of delayed digital video signals that are sequentially time-shifted by one horizontal period, and the plurality of delayed digital video signals. using a signal,
A luminance/chromaticity separation circuit that separates and extracts a luminance signal and a chromaticity signal, and two delayed digital video signals whose burst signals are in phase among the plurality of delayed digital video signals are supplied to obtain a difference signal. a subtracter; a sampling circuit that extracts the signal of the burst signal period from the difference signal; and a limiter that limits the output of the sampling circuit to a predetermined value and converts all the signals into signals having a value of one sign. an absolute value circuit that receives the output signal of the absolute value circuit as an input, integrates it for one burst period, and outputs the result, a burst integration circuit that receives the output signal of the burst integration circuit as an input,
A time constant circuit that outputs an output with a predetermined time constant, and a digital video processing unit whose input/output characteristics are controlled depending on whether the output of the time constant circuit indicates that the noise is large or small. A digital video signal processing circuit characterized by comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3631386U JPS62151283U (en) | 1986-03-14 | 1986-03-14 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3631386U JPS62151283U (en) | 1986-03-14 | 1986-03-14 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62151283U true JPS62151283U (en) | 1987-09-25 |
Family
ID=30846599
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3631386U Pending JPS62151283U (en) | 1986-03-14 | 1986-03-14 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62151283U (en) |
-
1986
- 1986-03-14 JP JP3631386U patent/JPS62151283U/ja active Pending
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