JPS62150922A - Digital oscillator - Google Patents

Abstract

PURPOSE:To obtain the titled oscillator with small circuit scale and high phase accuracy by taking an output of a counter circuit as a high-order bit and outputting the output of an adder circuit as a low-order bit. CONSTITUTION:A control signal inputted from an input terminal 10 is added to a value corresponding to the center frequency inputted from an input terminal 11 by an adder circuit 12 and the result is inputted to an adder circuit 13. An output of the adder circuit 13 is delayed by T at a register circuit 14 and the result is fed back to the other input of the adder circuit 13. As a result, the adder circuit 13 stores the inputted data one after another. An m-bit counter 15 is counted once every time the adder circuit 13 overflows. The overflow is detected by the change of the most significant bit of the adder circuit 13 from '1' to '0'. Thus, the same phase accuracy of a digital oscillator using an (m+n)-bit adder circuit is provided, n-bit is enough for the adder circuit and the oscillator with small scale is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a digital oscillation device with variable frequency used in digital PLLs (phase locked loops), digital FM modulators, and the like.

Conventional technology In recent years, digitalization of signal processing has been actively carried out, and PLL and F
Digitalization of M modulators has also been carried out, and there is an increasing demand for digitalization of variable frequency oscillators used in these modulators.

A conventional digital oscillator will be described below with reference to the drawings. FIG. 3 is a block diagram showing the configuration of a conventional digital oscillator, and FIG. 4 is a schematic diagram showing the output of adder 4 in FIG.

In FIG. 3, the control signal input from the input terminal 1 is added with a value corresponding to the center frequency input from the input terminal 2 in the adder circuit 3, and is input to the adder circuit 4. The output of the adder circuit 4 is delayed by one clock period (hereinafter referred to as T) in the register circuit 5 and fed back to the other input of the adder 4. As a result, the adder circuit 4 performs an operation of accumulating the input data one after another.

FIG. 4 schematically shows the output of the adder circuit 4.

In FIG. 4, the horizontal axis represents time, and the vertical axis represents the output of the adder circuit 4. Assuming that the adder circuit 4 is an n-bit adder circuit, the output of the adder circuit 4 increases every T, as can be seen from this figure, and is reset to 0 when it exceeds 2 to the n power. At this time 2
The n-th power corresponds to the phase 2π. Further, the rate of increase is proportional to the input to the adder circuit 4. Therefore, by passing the output of the adder circuit 4 through a ROM (read-only memory) 6 and referring to a prewritten table of sine waves, etc., an oscillation frequency proportional to the input can be obtained at the output terminal 7. Examples of this are, for example, Applications of Digital Signal Processing (IEICE M) pp15
9-160.

Problems to be Solved by the Invention However, in the digital oscillator with the above configuration, as can be seen from FIG. 4, the phase per step is 2π/2''.
Therefore, in order to improve the phase accuracy, it is necessary to increase the number of bits n of the adder 4, which increases the scale of the adder. In particular, when operating a circuit at high speed, it is necessary to use a parallel type adder.Increasing the number of bits by 1 bit in such an adder increases the circuit size exponentially, so it is necessary to use a digital adder with high phase accuracy. When an oscillation device was realized, there was a drawback that the circuit scale increased.

In view of the above problems, the present invention provides a digital oscillation device with a small circuit scale and high phase accuracy.

Means for Solving the Problems In order to solve the above problems, the digital oscillation device of the present invention includes an n-bit addition circuit that adds two input signals;
an n-bit register circuit that delays the output of the adder circuit by one clock period and feeds it back to one input of the adder circuit; and a counter circuit that counts by one each time the output of the adder circuit overflows; The circuit is configured to output the output of the circuit as the upper bit and the output of the adder circuit as the lower bit.

Effect of the Invention With the above configuration, the present invention can reduce the number of bits of the adder of the digital oscillator and reduce the circuit scale.

Embodiment An embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing the configuration of a digital oscillation device of the present invention, and FIG. 2 is a schematic diagram showing the values of each part of the digital oscillation device of FIG. 1. In FIG. 1, the control signal input from the input terminal 10 is added with a value corresponding to the center frequency input from the input terminal 11 in the adder circuit 12, and is input to the adder circuit 13. The output of the adder circuit 13 is delayed by T in the register circuit 14 and fed back to the other input of the adder circuit 13. As a result, the adder circuit 3 performs an operation of accumulating the input data one after another. The m-bit counter 15 counts by 1 each time the adder circuit 13 overflows. Overflow can be detected by a change in the top bit of the adder circuit 13 from 1 to O.

The outputs of the adder circuit 13 and the m-bit counter 15 are schematically shown in FIGS. 2(a) and 2(b). In FIG. 2(a), the horizontal axis represents time, and the vertical axis represents the output of the adder circuit 13.

Further, in FIG. 2(b), the horizontal axis represents time, and the vertical axis represents the output of the m-bit counter 15. If the adder circuit 13 is an n-bit adder circuit, the adder circuit 13 as in the conventional example.
The output increases every T, and when it exceeds 2 to the nth power, it is reset to 0, and the rate of increase is proportional to the input of the adder circuit 13.

The m-bit counter 15 counts by 1 each time the adder circuit 13 overflows, and returns to O at 2 to the m power. Therefore, if we consider the output of the m-bit counter 15 to be the upper m bits and the output of the adder circuit 13 to be the lower n bits, and consider the total amount + n bits as the output, the output will be as shown in Fig. 2 (c), which is different from the conventional m + n bits. It operates in the same way as a digital oscillator using a bit adder circuit. Moreover, in this embodiment, the adder may be n bits. Finally, the output of the adder circuit 13 is RO
If you pass it through M16 and refer to a table of sine waves written in advance, the oscillation frequency proportional to the input will be output to the output terminal 17.
can be obtained.

Incidentally, in the above explanation, the counter was explained as a binary counter, but there is no problem even if an n-ary counter of -i is used. When a binary counter is used to refer to the ROM 16, the address is generally a binary number, so there is an advantage that the memory capacity can be used efficiently. Further, as can be seen from FIG. 2 (al) and (C1), (C1 has a relationship in which the output of the adder circuit 13 is divided by m/m, and can also be used as a frequency dividing circuit.

Effects of the Invention As described above, the present invention provides an m
By providing a bit counter, it is possible to obtain a small-scale digital oscillation device that has the same phase accuracy as a digital oscillation device using an m + n-bit addition circuit, and the addition circuit only needs n bits.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a digital oscillator in an embodiment of the present invention, FIG. 2 is a schematic diagram showing the values of each part of the embodiment of FIG. FIG. 4 is a block diagram showing the configuration of the digital oscillator. FIG. 4 is a schematic diagram showing the output of the adder circuit in the conventional example shown in FIG. 4...Addition circuit, 5...Register, 1
3...addition circuit, 14...register,
15...m-bit counter.

Claims (2)

[Claims] (1) An n-bit adder circuit that adds two input signals; an n-bit register circuit that delays the output of the adder circuit by one clock period and feeds it back to one input of the adder circuit; 1 each time the output overflows
A digital oscillation device comprising a counter circuit for counting, outputting an output of the counter circuit as an upper bit and outputting an output of the adding circuit as a lower bit. (2) The digital oscillator according to claim 1, wherein the counter circuit is an m-bit binary counter circuit.