JPS62150710A - Manufacture of superlattice semiconductor - Google Patents

Manufacture of superlattice semiconductor

Info

Publication number
JPS62150710A
JPS62150710A JP29121485A JP29121485A JPS62150710A JP S62150710 A JPS62150710 A JP S62150710A JP 29121485 A JP29121485 A JP 29121485A JP 29121485 A JP29121485 A JP 29121485A JP S62150710 A JPS62150710 A JP S62150710A
Authority
JP
Japan
Prior art keywords
raw material
layer
gas
superlattice semiconductor
superlattice
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP29121485A
Other languages
Japanese (ja)
Inventor
Hideaki Iwano
岩野 英明
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP29121485A priority Critical patent/JPS62150710A/en
Publication of JPS62150710A publication Critical patent/JPS62150710A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To enable realization of Si, Si1-xGex semiconductor superlattice which can lower the temperature of a substrate for thermal CVD and has the steep change of an interface composition by using raw materials of high order silicon hydride (SinH2n+n, n=2,3...) and GeH4. CONSTITUTION:The growth of an Si layer uses a raw material of high order silicon hydride (SinH2n+n, n=2,3...) gas, an SixGe1-x mixed crystal layer uses a raw material of the mixed gas of SinH2n+2 and germanium hydride (GeH4) and these layers are alternately and repeatedly laminated by thermal CVD. In the above-mentioned method, the thermal decomposition temperature of the high order silicon hydride, the raw material of the Si layer, is as low as 300 deg.C-500 deg.C and a single crystal thin film can be grown at a low substrate temperature of 830 deg.C-900 deg.C. This makes the composition of Si and Si1-xGex in the interface between an Si film and the Si1-xGex layer steep change and an ideal superlattice structure can be manufactured.

Description

【発明の詳細な説明】 〔(産業上の利用分野〕 本発明は、Si.BizGal−x系超格子半導体の製
造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [(Industrial Field of Application)] The present invention relates to a method for manufacturing a Si.BizGal-x based superlattice semiconductor.

(発明の概要〕 本発明は、Bi、BizCkal−z系超格子半導体の
製造方法において、BinHn十g気体を原料としてS
ぜ層を、及び、BイnHn+* とG−H4混合気体を
原料としてBizGal−z層をCVD法により交互に
積層することにより、s7層、BtzGel−ya層が
低温基板温度において成長可能となシ、そのことにより
、”sとBizCkel−1層の界面における組成変化
の急峻性が保証され、電気的光学的特性を著しく改善し
たものである。
(Summary of the Invention) The present invention provides a method for manufacturing a Bi, BizCkal-z based superlattice semiconductor, in which S
The s7 layer and the BtzGel-ya layer can be grown at low substrate temperatures by alternately stacking the BizGal-z layer and the BizGal-z layer using the B-inHn+* and G-H4 mixed gas as raw materials by the CVD method. As a result, the steepness of the compositional change at the interface between the "s" and the BizCkel-1 layer is ensured, and the electro-optical characteristics are significantly improved.

(従来の技術〕 従来のBt、BszGel−z素超格子半専体の製造方
法はジャーナル、オブ、バキュームサイエンス、アンド
テクノロジー(:fourTLat of Vacww
nBaianca and TachnoLoly)誌
の1984年第A2巻486頁に記載さnた論文に見ら
nる様に、分子線エビキシ−法による製造方法と、アプ
ライド、フィジックス、レターズ(hppLied P
hysicsLeHevs )誌の1982年第41巻
464頁に記載さtた論文に見らnるようにモノシラン
(以下、sea番と記す)G$H,を原料とするOVD
法による製造方法があった。
(Prior art) The conventional manufacturing method of Bt, BszGel-z elementary superlattice semi-dedicated method is described in the Journal of Vacuum Science and Technology (: fourTLat of Vacuum
As can be seen in the paper published in Volume A2, page 486 of Baianca and TachnoLoly, 1984, a manufacturing method using the molecular beam evixilation method and Applied, Physics, Letters (hppLied P
OVD using monosilane (hereinafter referred to as sea number) G$H, as a raw material, as seen in the article published in vol. 41, p. 464, vol. 41, p.
There was a manufacturing method based on the law.

(発明が解決しようとする問題点及び目的〕しかし前述
の従来技術では、まず分子線コピタキシー法においては
、基板温度を低温にして製造することは可能であるが、
超高真空の炉と排気系が必要であるため、高真空を得る
ために多大の時間を必要とし、更に、大面積に一様に超
格子半導体を製造することが難しく、量産性に欠けると
いう問題点を有している。また、OVD法による製造方
法は、量産性は有するが、sea、を原料気体としてい
るため、日(単結晶薄膜を製造するためには、成長基板
温度を950℃〜1000℃の高温で成長させる必要が
あった。その結果、超格子半導体を製造する場合、Bt
xCkel−x薄膜もSZと同一基板温度で成長させる
ため、G−原子の拡散現象が起こり、84層と5jzG
s、−c層の界面の急峻性が保証されず、良好な電気的
、光学的特性を得られないという問題点を有していた。
(Problems and objects to be solved by the invention) However, in the prior art described above, first, in the molecular beam copytaxy method, it is possible to manufacture the substrate at a low temperature;
Because it requires an ultra-high vacuum furnace and exhaust system, it takes a lot of time to obtain a high vacuum, and it is difficult to uniformly manufacture superlattice semiconductors over a large area, making it difficult to mass-produce. There are problems. In addition, although the OVD method is suitable for mass production, since it uses sea as a raw material gas, it is necessary to grow the substrate at a high temperature of 950°C to 1000°C to produce a single crystal thin film. As a result, when manufacturing superlattice semiconductors, Bt
Since the xCkel-x thin film is also grown at the same substrate temperature as SZ, a diffusion phenomenon of G atoms occurs, and the 84 layer and 5jzG
There was a problem in that the steepness of the interface between the s and -c layers was not guaranteed, and good electrical and optical properties could not be obtained.

そこで本発明はこのような問題点を解決するもので、そ
の目的とするところは、5iRs Sz$G#1−1層
の単結晶薄膜の成長を、大面積、一様に成膜可能な化学
気相成長法により、且つ、低温基板温度で可能にする超
格子半導体の製造方法を提供するものであシ、その結果
として、S<層と84zGg、−2層の間の界面の組成
構造の変化の急峻性が保証され、良好な電気的、光学的
特性を有する超格子半導体を提供するものである。
The present invention is intended to solve these problems, and its purpose is to grow a single crystal thin film of 5iRs Sz$G#1-1 using a chemical method that can uniformly form a film over a large area. The present invention provides a method for manufacturing a superlattice semiconductor using a vapor phase growth method and at a low substrate temperature, and as a result, the composition structure of the interface between the S< layer and the 84zGg,-2 layer changes. The present invention provides a superlattice semiconductor with guaranteed steepness of change and good electrical and optical properties.

(問題点を解決するための手段〕 本発明のs(,5zzG−ヨー2薄膜を交互に繰シ返し
積層して成る超格子半導体を熱CVD法により製造する
超格子半導体の製造方法は、s7層の成長を高次水素化
シリコン(日(?SHs+、、n=298 、、、) 
2体を原料とし更にS i z G e@ −c混晶層
をBtnTln−4−2と水素化ゲルマニウム(G 、
 H,)の混合気体を原料とし熱OVD法によシ、交互
に繰シ返し製造することを特徴としている。
(Means for Solving the Problems) A method for manufacturing a superlattice semiconductor in which a superlattice semiconductor formed by alternately and repeatedly stacking s(,5zzG-Yo2 thin films) of the present invention is manufactured by a thermal CVD method, The growth of the layer was performed using highly hydrogenated silicon (days (?SHs+, n=298,...)
Using these two bodies as raw materials, a Si z Ge@-c mixed crystal layer is made of BtnTln-4-2 and germanium hydride (G,
It is characterized in that it is produced alternately and repeatedly by a thermal OVD method using a mixed gas of H, ) as a raw material.

(作用〕 本発明の上記の製造方法によれば、SZの原料である。(effect) According to the above manufacturing method of the present invention, it is a raw material for SZ.

%次水素化シリコン(SZ%mn+意 an=2 、8
 、 、、、)の熱分解温度が、800℃〜500℃の
低温でちり、5OTX、を、原料とした場合、単結晶薄
膜の成長温度が950℃〜1100℃の高温であったの
に比較して、880℃〜900℃の低温基板温度で単結
晶薄膜の成長が可能となった。その結果、熱OVD法で
84.S<1−zGe系超格子半導体を製造する場合、
問題であった、Ge元素の成長時の拡散が数10 A以
内になるため、a6層と、S il −zGaz層の間
の界面は、SiとSi、−cGgの組成が急峻に変化し
、理想的超格子構造を製造することが可能となるのであ
る。
% silicon hydride (SZ%mn+an=2,8
When dust, 5OTX, is used as a raw material, the thermal decomposition temperature of As a result, it has become possible to grow a single crystal thin film at a low substrate temperature of 880°C to 900°C. As a result, 84. When manufacturing S<1-zGe-based superlattice semiconductor,
Since the diffusion of the Ge element during growth, which was a problem, is within several tens of amperes, the composition of Si, Si, and -cGg changes rapidly at the interface between the a6 layer and the Sil-zGaz layer. This makes it possible to manufacture an ideal superlattice structure.

(実施例〕 第1図は本発明の実施例におけるsz、sz、−cGe
z超格子半導体の製造方法による製造装置の主要構成図
である。(119)に示す石英製熱aVD反応炉に設置
された。カーボンサセプター〔128〕上に単結晶B(
基板を誼く。単結晶S(基板は表面の方位(100)方
向であり、フッ酸系による前処理洗浄がほどこされてい
る。(127〕の高真空排気系により、反応炉中を1O
−qT。
(Example) Figure 1 shows sz, sz, -cGe in an example of the present invention.
1 is a main configuration diagram of a manufacturing apparatus according to a method for manufacturing a z superlattice semiconductor. (119) was installed in a quartz thermal aVD reactor. Single crystal B (
Destroy the board. The single-crystal S (substrate is in the (100) direction of the surface, and has undergone pretreatment cleaning with a hydrofluoric acid system. (127)) The inside of the reactor is 1O
-qT.

21台の真空に保持した後、(116)の水素ガスボン
ベから(109)のマス70−コントローラを通して水
素ガスを反応炉中に、且つ同一流量(D水Xガスt−(
110)のマスフローコントローラを通して(125)
のロータリーポンプで直接流す、更に(116)のSi
.a−ガスボンベをGn放して、(107)のマス70
−コントローラーを通して、電磁弁(101)を通しく
125ンのロータリーポンプに直接流す。(124)の
ニードルパルプで反応管内の圧力を適当な値に設定し、
(129)、(180)のニードルパルプで、反応管に
通じるガスラインの配管内圧力とロータリーに直接つな
がるガスライン配管内の圧力を同一になるように調節す
る。このあと、(121)の高周波発振電源によシ、(
120)のコイルによって、反応管中のカーボンサセプ
ターを加熱する。880℃〜900℃に基板温度を保持
して電磁弁(101)を通していたSZ、a、ガスをg
L電磁弁102)を通して反応管中に導く。反応管に導
かnたEli、H,ガスは単結晶84基板の上で、13
4.BinHrn、H@に分解し、基板表面上で表面反
応を経て、Siの単結晶薄膜が得られる。Si層を50
〜200Aの薄膜に形成した後、(117)のG $ 
H4ガスボンベから、543H6ガスを反応管中に導い
たと同一の方法で、GaT(、ガスを導入する。適当な
ガスの混合比により、前述のs7極薄膜上にai、−、
G−の混晶薄膜が形成さ牡る。この操作を何回も、繰シ
返し行なえば、Bt、f3il−zGaの薄膜が積層さ
れた、超格子半導体が得らnる。この一連の極薄膜形成
の基板温度が880℃〜900℃と低温であるため、界
面の組成の急峻性が保証されるのである。第2図は本実
施例によシ形成されたSi,541−cGaz界面のG
−元素の濃度の膜厚方向分布を示す図である。測定はオ
ージェ電子分光法によシ行なった。実線が本実施例によ
るs7.a。
After maintaining the vacuum in the 21 units, hydrogen gas is introduced into the reactor from the hydrogen gas cylinder (116) through the mass 70-controller (109), and at the same flow rate (D water
110) through the mass flow controller (125)
The Si of (116) is directly supplied with a rotary pump of
.. a- Release the gas cylinder Gn and move to square 70 of (107)
- Direct flow through the controller to the 125 rotary pump through the solenoid valve (101). Set the pressure inside the reaction tube to an appropriate value using the needle pulp (124),
The needle pulps (129) and (180) are used to adjust the pressure in the gas line leading to the reaction tube and the pressure in the gas line leading directly to the rotary to be the same. After this, the high frequency oscillation power supply of (121) is applied, (
120) heats the carbon susceptor in the reaction tube. The SZ, a, and gas, which were passed through the solenoid valve (101) while maintaining the substrate temperature at 880°C to 900°C, were
into the reaction tube through the L solenoid valve 102). The Eli, H, and gases introduced into the reaction tube are placed on a single crystal 84 substrate.
4. It decomposes into BinHrn, H@, and undergoes a surface reaction on the substrate surface to obtain a Si single crystal thin film. 50% Si layer
After forming a thin film of ~200A, G $ of (117)
GaT gas is introduced from the H4 gas cylinder in the same way as the 543H6 gas was introduced into the reaction tube. By using an appropriate gas mixture ratio, ai, -,
A G- mixed crystal thin film is formed. By repeating this operation many times, a superlattice semiconductor in which thin films of Bt and f3il-zGa are laminated can be obtained. Since the substrate temperature for forming this series of extremely thin films is as low as 880° C. to 900° C., the steepness of the composition at the interface is guaranteed. Figure 2 shows the G of the Si,541-cGaz interface formed in this example.
- It is a diagram showing the distribution of the concentration of elements in the film thickness direction. The measurements were performed using Auger electron spectroscopy. The solid line is s7. according to this embodiment. a.

を原料とした場合であシー破線が従来のs 4 H。The broken line is the conventional s4H.

を原料とした場合のG−元素の濃度分布である。This is the concentration distribution of G-element when using as the raw material.

a 4 H,を使った場合には基板温度が950℃以上
とな906M子の拡散が薄膜形成中に起こっている。
When using a 4 H, the substrate temperature is 950° C. or higher, and diffusion of 906M molecules occurs during thin film formation.

$8図には本実施例によシ製造したS<、5jl−cG
、超格子半導体の膜厚方向のs7とG、の原子濃度を示
す図であって、本発明により急峻な界面を持つ134.
85−zGazの超格子半導体が実現されたことを示す
Figure 8 shows S<,5jl-cG produced according to this example.
, is a diagram showing the atomic concentrations of s7 and G in the film thickness direction of the superlattice semiconductor 134., which has a steep interface according to the present invention.
This shows that a superlattice semiconductor of 85-zGaz has been realized.

(発明の効果〕 以上述べたように本発明によれば高次水素化シリコン(
BイnH,九十冨、?L=2,8膠・・・]をG#■番
を原料としたことによシ、熱OVDの基板温度を低温化
できそれによシ、界面の組成変化が急峻なat、85−
x(kaz半導体超格子を実現できるという効果を有す
る。そのことによシ、従来のa4単結晶よ)高いキャリ
ア移動度を持つ半導体が可能となシ、高速スイッチング
可能なトランジスター、およびそれらを集積した高速の
メモリー、演算素子が可能となる。更に、熱0’VD法
は大面積均一に成膜が可能であるため、安価に大量にこ
れらの素子の製造が可能である。更に、at、13t@
−wag超格子半導体は移動度の飽和速度が大きいため
、微細加工による特性の劣化がなく、大規模な集積化が
容易である。
(Effect of the invention) As described above, according to the present invention, higher-order hydrogenated silicon (
B in H, Kujutomi,? L=2,8 glue...] is made from G# ■ as raw material, the substrate temperature of thermal OVD can be lowered, and the composition change at the interface is abrupt.
It has the effect of realizing a KAZ semiconductor superlattice, which makes it possible to create semiconductors with high carrier mobility (compared to conventional A4 single crystals), high-speed switching transistors, and their integration. This enables high-speed memory and arithmetic elements. Furthermore, since the thermal 0'VD method enables uniform film formation over a large area, these devices can be manufactured in large quantities at low cost. Furthermore, at, 13t@
- Wag superlattice semiconductors have a high mobility saturation speed, so there is no deterioration in characteristics due to microfabrication, and large-scale integration is easy.

更に、Bt、Eli1−zGar:r半導体超格子は発
光素子としての可能性があり、安価で高信頼性の半導体
レーザを提供できる。
Furthermore, the Bt, Eli1-zGar:r semiconductor superlattice has potential as a light emitting element, and can provide an inexpensive and highly reliable semiconductor laser.

以上述べたように本発明による製造方法によtば種々の
デバイスを安価に大量に提供できるという効果を有する
As described above, the manufacturing method according to the present invention has the advantage that various devices can be provided in large quantities at low cost.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、本発明の超格子半導体製造方法による主要構
成図である。 第2図は、本発明の製造方法によシ製造したSt、5t
l−zGez層界面のGe原子濃度膜厚方同分布図であ
る。 第8図は、本発明の製造方法によシ製造したS(、B 
4l−zGaz超格子半導体の各元素膜厚方向濃度分布
図である。 (101)〜(106)、(111)〜(115)、(
181)00.電磁バルブ (107)〜(110)。。、マスフローコントローラ
(116)、、、高次水素化シリコンボンベ(117)
、、、水X化ゲルマニウムボンベ(118)、、、水素
ボンベ (119)、、、反応炉、(120)、、、高周波コイ
ル、(121)、、、高周波電源、(122) 、 、
 、Ei i単結晶基[、(128)、、、カーボンサ
セプタ−(125)、(128)、、ロータリーポンプ
(126ン00.廃ガス処理装置 以上 出願人 セイコーエプソン株式会社 ラ七j?づt、p羊よ轡しイ≧ト製Xツt、かムドJ/
シリml各i%xのtキ禮ぺ圀 第1図 第2図 練薄文燭凛■介目 第3図
FIG. 1 is a main configuration diagram according to the superlattice semiconductor manufacturing method of the present invention. FIG. 2 shows St, 5t manufactured by the manufacturing method of the present invention.
It is a distribution map of the Ge atomic concentration in the film thickness direction at the l-zGez layer interface. FIG. 8 shows S(, B) manufactured by the manufacturing method of the present invention.
FIG. 4 is a concentration distribution diagram of each element in the film thickness direction of a 4l-zGaz superlattice semiconductor. (101) to (106), (111) to (115), (
181)00. Electromagnetic valves (107) to (110). . , Mass flow controller (116), High-order hydrogenated silicon cylinder (117)
, ,Germanium hydroxide cylinder (118), ,Hydrogen cylinder (119), ,Reactor, (120), ,High frequency coil, (121), ,High frequency power supply, (122), ,
, Ei i single crystal group [, (128), , carbon susceptor (125), (128), , rotary pump (126 N00. Waste gas treatment equipment) Applicant: Seiko Epson Corporation ,p Sheep 轡し ≧ ト made
Shiri ml each i%

Claims (1)

【特許請求の範囲】[Claims] シリコン単結晶(以下Siと記す)薄膜とシリコンゲル
マニウム混晶(以下Si_xGe_1_−_xと記す)
薄膜を交互に繰り返し積層して成る超格子半導体を熱分
解化学気相成長法(以下熱CVD法と記す)により製造
する超格子半導体の製造方法において、Si単結晶層の
成長を高次水素化シリコン(以下Si_nH_2_n_
+_2と記す)気体を原料とし、更にSi_xGe_1
_−_x混晶層をSi_xH_2_n_+_2と水素化
ゲルマニウム(以下GeH_4と記す)、の混合気体を
原料として、前記熱CVD法により、交互に繰り返し製
造することを特徴とする超格子半導体の製造方法。
Silicon single crystal (hereinafter referred to as Si) thin film and silicon germanium mixed crystal (hereinafter referred to as Si_xGe_1_-_x)
In a method for manufacturing a superlattice semiconductor in which a superlattice semiconductor formed by alternately stacking thin films is manufactured by pyrolytic chemical vapor deposition (hereinafter referred to as thermal CVD method), the growth of a Si single crystal layer is performed by high-order hydrogenation. Silicon (hereinafter referred to as Si_nH_2_n_
+_2) gas is used as a raw material, and further Si_xGe_1
A method for manufacturing a superlattice semiconductor, characterized in that ___x mixed crystal layers are alternately and repeatedly manufactured by the thermal CVD method using a mixed gas of Si_xH_2_n_+_2 and germanium hydride (hereinafter referred to as GeH_4) as raw materials.
JP29121485A 1985-12-24 1985-12-24 Manufacture of superlattice semiconductor Pending JPS62150710A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP29121485A JPS62150710A (en) 1985-12-24 1985-12-24 Manufacture of superlattice semiconductor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP29121485A JPS62150710A (en) 1985-12-24 1985-12-24 Manufacture of superlattice semiconductor

Publications (1)

Publication Number Publication Date
JPS62150710A true JPS62150710A (en) 1987-07-04

Family

ID=17765940

Family Applications (1)

Application Number Title Priority Date Filing Date
JP29121485A Pending JPS62150710A (en) 1985-12-24 1985-12-24 Manufacture of superlattice semiconductor

Country Status (1)

Country Link
JP (1) JPS62150710A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01144617A (en) * 1987-08-27 1989-06-06 Texas Instr Inc <Ti> Method of continuous growth of super-lattice structure of distortion layer

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01144617A (en) * 1987-08-27 1989-06-06 Texas Instr Inc <Ti> Method of continuous growth of super-lattice structure of distortion layer

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