JPS62150425A - Operation lsi - Google Patents

Abstract

PURPOSE:To improve the arithmetic efficiency by selecting an input data from either an output terminal of an A register or the 2nd input terminal, storing an output of an arithmetic unit tentatively in a D register in using the data of the 2nd input terminal and outputting the result externally. CONSTITUTION:The input data from an input/output terminal 6 is selected by the 1st selection circuit via an input/output buffer 11 and inputted to the A register 3, the 2nd selection circuit 9 selects either an input data from the 2nd input terminal 8 or an output data of the register 3, and its output and an output of a B register 4 connected to the buffer 11 are inputted to the arithmetic unit 5. In using the input data from the terminal 8 for the purpose of the arithmetic operation, the output of the arithmetic unit 5 is stored in the D register 10 and its output is outputted from the 2nd output terminal 13 and the terminals 8, 13 are connected by a C register 7.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an arithmetic LSI in an arithmetic device, and more particularly to an arithmetic LSI that uses data held in external registers to improve the efficiency of arithmetic operations.

BACKGROUND ART Conventionally, in an LSI housing this type of arithmetic unit, registers within the LSI have been used to store arithmetic data and results. FIG. 2 shows a block diagram of a conventional arithmetic LSI. The programmable L811 includes an A register 3 that stores calculation data, a B register 4, an interpretation circuit 2 that selects data to be stored in the A register 3, a programmable L device 5, and input/output of data with the outside of the LSI. It consists of an input/output terminal 6 for carrying out operations, and a C register 7 is connected to the outside of the LSI. According to this configuration, data external to the LSI is stored in the A register 3 or B register 4 inside the LSI via the input/output terminal 6, and then is calculated by the arithmetic unit 5, and the result of the calculation is output to the selection circuit. 2, it is selected as input data to the A register 3 and stored in the A register 3. Data input into the LSI via the input/output terminal 6 includes read data from the main memory circuit, registers external to the LSI, and the like.

Now, if we consider the case where the data in the C register 7 and B register 4 outside the LSI are operated, the data stored in the C register 7 is transferred to the LSI via the input/output terminal 6 of the LSI.
The data is input into I, is selected by the selection circuit 2 as input data to the A register 3, and is stored in the A register 3 (first step).

Next, the data stored in the A register 3 and the B register 4 are operated on by the arithmetic unit 5, and the operation result is selected by the selection circuit 2 as the input data for the A register 3.

Stored in A register 3 (second step). Finally A
The data stored in the register 3 is output to the outside of the LSI via the input/output terminal 6 and stored in the C register 7 (
3rd step). In this way, when performing arithmetic operations on registers outside the LSI, three steps are required.
The disadvantage was that the efficiency of calculation processing was low.

Problems to be Solved by the Invention An object of the present invention is to provide an arithmetic LSI that solves the above-mentioned drawbacks, namely, that the number of steps in arithmetic processing using a C register external to the LSI increases, resulting in poor efficiency. There is a particular thing.

Means for Solving the Problems In order to solve the above-mentioned problems, the present invention provides a %A register and a B register, a first selection circuit that selects input data to the A register, and an arithmetic unit that performs arithmetic processing. and an input/output terminal for inputting and outputting data to and from the outside, a second input terminal, and either data input from the second input terminal or data from the A register. a second selection circuit that selects t-; a D register that temporarily holds the output of the arithmetic unit when data from the second input terminal is used; and a second selection circuit that outputs the output of the D register to the outside. This configuration employs a configuration in which an output terminal is provided.

Operation Since the present invention is configured as described above, when the LSI external KC register is connected between the second input terminal and the second output terminal and arithmetic processing is performed using the data of the C register and the data of the B register. , the result of the operation is temporarily held in the D register and then stored in the external C register, which has the effect of reducing the number of steps in the operation process. Note that operations using data in the A and B registers are processed efficiently as before.

Example Next, embodiments of the present invention will be described with reference to the drawings.

Referring to FIG. 1, which shows a block diagram of an embodiment of the present invention, the computation LS 11 of the present invention includes an input/output terminal 6, an input/output buffer 11, and an A register 3 and a B register 4 for storing computation data. , the data input from the first selection circuit that selects the input data of the A register 30 and the A register 3
A second selection circuit 9 selects any of the output data of B as the input data of the calculation, and the output of the second selection circuit 9 and B
an arithmetic unit 5 that inputs the output of the register 4 and performs an arithmetic operation;
A D register 10 stores the output of the arithmetic unit 5 when the data input from the second input terminal 8 is used for an operation, and a second output terminal 13 outputs the output of the D register 10 to the outside of the LSI. , a control circuit 12 that generates selection signals 71 to 76, and a C register 7 external to the LSI is connected between the second input terminal 8 and the second output terminal 13.

Next, FIG. 1 and the selection signal lines 71 to 7 from the control circuit 12
The operation of this embodiment will be explained with reference to Table 1 showing the relationship between the selection signal No. 6 and the circuit operation.

In Table 1, arithmetic LSI')j normally inputs and outputs data between an external circuit of the LSI and a bidirectional input/output terminal 6 via a line 51. Data input to the LSI from the bidirectional input/output terminal 6 enters the output buffer 11 via the line 61.
It is sent to the first o selection circuit 2 and the B register 4 via a62.

The first selection circuit 2 selects the input data sent via the line 62 when the selection signal sent from the control circuit 12 via @72 is logic O, and the selection signal is logic 1. The output data of the arithmetic unit 5 sent via the time line 68 is selected and sent to the A register 3 via the line 63. A
Register 3. B registers 4 each store input data when the write signal sent from control circuit 12 via line 75 and line 76 is a logic one. The output data of the A register 3 outputted via the line 64 is sent to the second selection circuit 9 and the human output buffer 11. Crowd count buffer-1
1 outputs the output data of the A register 3 sent via the line 64 to the input/output terminal when the output mode signal sent via the line 71 from the control circuit 12 is logic 1. 6 to the outside of the LSI.

As described above, normal operation data is input to the LSI via the input/output terminal 6 and stored in the A register 3 or B register 4 inside the LSI. After that, A register 3 and B
Performs calculations on the data in register 4. Second selection circuit 9
is sent via &164 when the selection signal sent from the control circuit 12 via line 73 is logic 0.
The output data of the register 3 is selected, and when the selection signal is logic 1, the input data sent from the input terminal 8 via the line 65 is selected. When calculating the data in the A register 3 and the B register 4, the selection signal 73°75.76 becomes logic 0, and the second selection circuit 9 selects the output data of the A register 3 and outputs it via @66. It is sent to the arithmetic unit 5. The arithmetic unit 5 receives the output data of the A register 3 sent through the line 66 and the output data of the B register 4 sent through the line 67, and performs calculations, and the calculation result is sent through the line 68. The signal is sent to the D register 10 and the first selection circuit 2.

When using the data in A register 3 for calculations, DI/
The write signal sent from register IOK control circuit 12 via line 74 is logical Orζ and no storage is performed in the D register. In the first selection circuit 2, the selection signal sent via the line 72 becomes logic 1, and the operation result is selected and sent to the A register 3 via the line 63. At this time, the input signal sent to the A register 3 via the line 75 becomes logic 1, so the operation result is stored. Furthermore, when a calculation is desired, the calculation is performed as described above, and when the calculation is completed, the calculation result stored in the A register 3 is sent to the human output buffer 11 via the line 64, and the input/output terminal 6 is It is output to the outside of the LSI via the LSI.

Next, when calculating the C register 7 and B register 4 outside the LSI, the output data of the C register 7 is sent to the second input terminal 8 via the line 52 and input to the LSI. Input data is sent from the second input terminal 8 to the second selection circuit 9 via a line 65. When this input data is used for an operation, the selection signal sent to the second selection circuit 9 via line 73 becomes logic 1, and the input data is selected and sent to the arithmetic operation unit via line 66. 5 for calculation. At this time, the write signal 74 of the D register 10 becomes logic 1, and the calculation result sent via M2S is stored. What is the operation result stored in D register 1o? It is sent to the second output terminal 13 via the IA 69 and output to the outside of the LSI. The data output to the outside of the LSI through the second output terminal 13' is sent to the C register 7 via the line 53, and the calculation result is stored in the C register 7. In other words, the execution of this operation consists of the steps of performing an operation on the data in the C register 7 and the data in the B register 4, and storing the result in the D register 10 (first step), and the operation result stored in the D register 10. This is performed by storing the data in the C register 7 (second step). In this way, the entire operation takes two steps, but since the second step does not use the arithmetic unit 5, the arithmetic operation can be performed using the arithmetic unit 5 at the same time as the step of storing the operation result in the C register 7. Yes, the arithmetic unit 5 is exclusively used for only one step.

Effects of the Invention As explained above, according to the present invention, data input from the C register external to the LSI can be directly input to the arithmetic unit for arithmetic processing, thereby reducing the number of exclusive steps of the arithmetic unit. , which has the effect of increasing the efficiency of arithmetic processing.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an arithmetic LSI according to an embodiment of the present invention.
FIG. 2 is a block diagram of a conventional example. 1... Arithmetic L8I, 2... First selection circuit, 3... A register, 4... B register, 5... Arithmetic unit, 6... Input/output terminal, 7... C register, 8... Second
input terminal, 9... second selection circuit, 10...
...D register, 11 °'°"Human output Huffer%
12...Control circuit, 13...°second output terminal, 51-53...External wiring, 61-6
9... LSI internal wiring, 71-76...
- Control circuit selection signal line. Agent Patent Attorney Kuri 1) Haru Yute:', :1-
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Claims (1)

[Claims] A register and B register, a first selection circuit that selects the input data of the A register, an arithmetic unit that performs arithmetic processing on the data of the A register and B register, and inputs and outputs data to and from external circuits of the LSI. In an arithmetic LSI that consists of input and output terminals for
a second input terminal; a second selection circuit that selects either the data input from the second input terminal or the output data of the A register and inputs the selected data to the arithmetic unit; A D register for temporarily holding an arithmetic unit output when data from the terminal is used, and a second output terminal for outputting the output of the D register to the outside of the LSI, and the second output terminal and a second input terminal, the C register is connected between the input terminal and the second input terminal.