JPH01287749A - Test circuit for digital signal processor - Google Patents

Abstract

PURPOSE:To output substantially the same test data as data on a bus with a small number of pins by fetching data selectively from an existent register which holds an arithmetic result in each arithmetic cycle and is connected to the bus. CONSTITUTION:A selector 23 is provided with the register 20 where the arithmetic result is held in each arithmetic cycle and the bus 19. This selector 23 is connected to the 1st pin T1 of an LSI chip and inputs a select signal SSEL and a selector 23 is connected to the 2nd pin T2 of the LSI chip and outputs data which is part of the output of the register corresponding to the select signal. Namely, the register 20 sends its output to the bus 21 each time arithmetic operation is performed and the output is substantially the same as the data on the bus 21. The selector 23 inputs the output of the register 20 and outputs it by m/n bit specified with the select signal SSEL at each other. Consequently, the number of pins of the LSI chip for the test can be decreased.

Description

[Detailed Description of the Invention] [Summary] Regarding a test circuit for a digital signal processor (DSP), the purpose is to reduce the dimensions of an LSI in which the DSP is formed and to reduce the number of pins of an LSI chip for testing. A selector is provided between the bus and the register in which the calculation result is held in each calculation cycle, and the selector is connected to the first pin of the LSI chip to input a selection signal, and the selector also connects to the first pin of the LSI chip. It is connected to a second pin and is configured to output part of the data output from the register according to the selection signal.

[Industrial Field of Application] The present invention relates to a digital signal processor (DSP), and more particularly to a test circuit for a custom DSP that is integrated into an LSI and is optimized for a specific application.

DSPs generally include customer-type DSPs that are specialized for filtering processing for switching equipment, for example, and general-purpose DSPs that are made for general purposes. Custom-made DSPs aim to improve signal processing speed for specific applications, while also reducing size and
Achieving low prices. The present invention particularly relates to such a customer type DSP, especially a DSP for LSI customers.

(Prior art and problems to be solved by the invention) FIG. 4 shows the configuration of a conventional LSI customer type DSP.

The DSP in FIG.
Program counter C or lower P counter) 1, which indicates the address of P counter L, μR,
The instruction register 5 stores the microinstructions output from the OM4, and the data ROM in the instruction register 5 (hereinafter referred to as D-
a data pointer 6 indicating the address of ROM) 7;
D-ROM 7 that stores multipliers, RAM 9 that stores data work areas, multiplier 10, accumulator 11,
A general-purpose register 13, an A register 14, a B register 15, and a bus 19 are connected as shown.

Similar to various computers, such DSPs require testing of individual component circuits and the overall configuration.

When testing a general-purpose DSP, various tests can be performed by connecting an external test circuit.

However, in the case of custom DSPs, tests similar to general-purpose DSPs are not possible due to the lack of LSI chip package pins for connecting external test circuits, insufficient memory to store test programs, etc. can't do it. A custom DSP reduces the microinstruction word length, simplifies the instructions, simplifies the hardware, and directly specifies RAM addresses.

Therefore, in such a custom DSP, one known method for testing writing to RAM and continuous writing from RAM is to store a test program corresponding to all addresses in RAM in μROM and sequentially change the addresses. It is being However, this method has the problem that the test program becomes large and the memory capacity of the μROM becomes large.

Another test method is to provide an instruction decoder for testing internally, apply test instructions one by one from the outside, have the instruction decoder decode them, and execute the instructions one by one for testing. However, this method requires the provision of a test instruction decoder, which increases the circuit scale and poses a problem in terms of LSI integration and cost reduction. In addition, since each command is given from the outside, the operation is cumbersome and the test time is considerably increased.

In particular, the performance of DSPs has recently improved from 16 bits to 32 bits. In this case, if you try to output 32-bit parallel test data through the pins of the chip, you will need 32 bins for testing, which makes it virtually impossible to test the DSP due to the limited number of pins. is occurring.

Furthermore, incorporating a test circuit into the LSI of a DSP is not only a matter of LSI integration and cost, as mentioned above.
A problem that arises with connecting test circuits to the bus is that the processing speed of the DSP is reduced. That is,
This is because connecting the test circuit to the bus increases the load on the bus. In that sense,
It is not preferable to connect the test input register 11 and output register 12 to the bus 19.

The present invention aims to solve the problems mentioned above.

That is, the present invention is intended to realize a test circuit for DSPs, especially LSI-based customer-type DSPs, which is compatible with higher bits, does not reduce the performance of the DSP, does not increase the size of the LSI chip, and is inexpensive.

[Means to solve the problem]

FIG. 1 shows a block diagram of the principle of a DSP test circuit according to the present invention.

A register 20 in which calculation results are held every calculation cycle.
A selector 23 is provided between the bus 19 and the bus 19. The selector 23 is connected to the first pin TI of the LSI chip and inputs the selection signal SSEL, and the selector 23 is connected to the first pin TI of the LSI chip.
It is connected to the second pin T2 of the I-chip and is configured to output part of the data output from the register according to the selection signal.

The register 20 is an existing one for a DSP. Therefore, the selector 23 is simply newly provided. Further, the selector 23 is not connected to the bus but to the register 20.

If the number of bits in register 20 is m, register 2 is
When attempting to output data of 0 via the selector 23, the number of first pins T1 is (2'-1)=n! The number of second pins T2 is m/n. For example, m=
32. If n=4, the number of first pins is two and the number of second pins is eight. This also reduces the number of pins on the chip.

[For production]

The register 20 outputs its output to the bus 21 each time it performs an operation. Therefore, it is substantially the same as the data on bus 21. The selector 23 inputs the output of the register 20 and receives a selection signal S. Output every m/n bits specified by L.

〔Example〕

FIG. 2 shows a circuit diagram of a DSP having a test circuit according to an embodiment of the present invention.

2 corresponds to the DSP of FIG. 4, but a driver circuit 24 is connected between the output of the accumulator 11 and the bus 19, and the accumulator 11 and the driver circuit 2 are connected.
A selector 23 is connected between 4 and 4. Selector 23
is the first signal for externally inputting the selection signal SSE+.
pin TI, general register 13 result SD? It is connected to the second pin T2 for outputting to the outside. If the number of bits in the accumulator 11 is 32 bits and one word of 32 bits of data is to be read out twice each time with 16 bits, the first
The second pin T1 is 1, and the second pin T2 is 16, total 17.
Use book pins. When reading one word of 32 bits of data in four 8 bits each, the first pin TI is set to 2.
A total of 10 pins, including 8 second pins T2, are used.

As an example of DSP processing, a case will be described in which digital filtering is performed using the following algorithm.

However, X: filtering result, :filtering coefficient X, :input data filtering coefficient k, are input to the A register 14,
Input data
The products are summed.

Here, unlike a normal microprocessor, the DSP always uses the registers 14 and 15 in each calculation cycle.
．． 11 and a multiplier. The feature is that the above filtering process is performed using IO. The output of accumulator 11 is output to bus 19 as a filtering result.

Therefore, viewing the output of accumulator 11 is the same as reading data on bus 19. Therefore,
Instead of directly outputting data from the bus 19, the data on the bus 19 can also be tested by taking out the output of the accumulator 11.

The selector 23 divides the data and outputs it.
The number of pins used for data output is reduced.

FIG. 3 shows a circuit diagram of a selector according to an embodiment of the present invention. The circuit shown in FIG. 3 has 32 bits of data Dffl-”I
) The case is shown in which o is selectively output in four parts of 8 bits each. In FIG. 3, the selector 23 includes a decoder 23a,
It consists of four selection gate circuits 23bl to 23b4 and an output gate circuit 23c. The decoder 23a receives a 2-bit selection signal 33! , and if, for example, 5SEL=3, a signal for selecting the selection gate circuit 23b1 is output.

Each selection gate circuit consists of 8 AND gates Al~
Consists of A8.

The selection gate circuit 23b1 outputs 8-bit data D31 to DZ3 to the output gate circuit 23c in response to the selection signal from the decoder 23a. The output gate circuit 23c is 8
It is composed of OR gates 23cl to 23c8, and one of the selection gate circuits 23b1 to 23b4
The selected 8-bit data is outputted to the outside via the second pin T2.

In FIG. 3, the selector 23 is operated with the same clock as the accumulator 11.

Therefore, in one calculation cycle, 1 of accumulator II
Outputs only 8 bits out of 32 bits of data. By repeating this four times, 32-bit data is output.

If 32 bits of data are to be output in one calculation cycle, a clock having a frequency four times that of the clock of the accumulator 11 may be used for the selector 23.

In the embodiment shown in FIG. 2, data is taken out from the accumulator 11, but it is not limited to the accumulator 11.
Data may be taken out from a register that always operates in one calculation cycle and is connected to the bus 19, for example, the general-purpose register 13.

[Effects of the Invention] As described above, according to the present invention, by selectively retrieving data from existing registers that hold calculation results and are connected to the bus in each calculation cycle, virtually no data can be stored on the bus. This has the effect that the same test data as the data can be output externally with a smaller number of pins. Further, in the present invention, even with such a test function, there is an effect that the processing speed of the DSP is not reduced and the LSI chip size is not increased too much.

[Brief explanation of the drawing]

FIG. 1 shows a digital signal processor (DS) of the present invention.
P) is a principle block diagram of the test circuit, FIG. 2 is a DSP test circuit diagram according to an embodiment of the present invention, FIG. 3 is a selector circuit diagram according to an embodiment of the present invention, FIG. 4 is a conventional DSP circuit diagram, It is. (Explanation of symbols) 10... Multiplier, 11... Accumulator, 13... General purpose register, 14... A register, 15... B register, 1
9...Bus, 23...Selector, 24.
...Driver circuit.

Claims (1)

[Claims] 1. In an LSI digital signal processor, a register (2
A selector (23) is provided between the bus (19) and the bus (19);
The selector (23) selects the first pin (T1) of the LSI chip.
) to input the selection signal (S_S_E_L),
The selector (23) also selects the second pin (T
2), and is configured to output part of the data output from the register according to a selection signal.