JP3474384B2 - Shifter circuit and microprocessor - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a shifter circuit provided in a logic LSI or the like, and a microprocessor equipped with this shifter circuit.

[0002]

2. Description of the Related Art In order to improve the performance of a logic LSI such as a microprocessor or a DSP, there is a method of performing parallel processing and shortening an operation cycle.
In order to shorten the operation cycle of the logic LSI, it is indispensable to shorten the operation cycle of the arithmetic circuit, which is one of its main constituent elements.

Conventionally, by making full use of semiconductor device technology and advanced circuit technology such as dynamic circuit,
The operation cycle of the arithmetic circuit has been shortened. But,
In order to meet market needs, even higher speeds are needed.

The shifter circuit is also one of the main circuits of the microprocessor, and is a circuit that has been required to operate at high speed.

FIG. 7 shows a block diagram of a conventional 32-bit left and right barrel shifter.

The barrel shifter is usually constructed by arranging selectors in series. What kind of selector is combined and configured is important, and the optimum configuration is searched for in consideration of design parameters and required performance at that time.

In the shifter circuit of FIG. 7, the block 20
Reference numeral 1 is a byte unit shifter for shifting left and right in byte units. That is, 8-bit, 16-bit, and 24-bit left and right shifts are performed. This byte unit shifter 201 is 0
Since there is a case of bit shift, it is composed of a 4-to-1 selector. The block 202 is an 8-bit left / right barrel shifter, and performs a shift operation for a shift amount smaller than 8 bits, that is, a shift amount of 7 bits, 6 bits, 5 bits, .... The 8-bit left / right barrel shifter 202 has a left / right shift function, and is therefore composed of a 15: 1 selector.

The byte unit shifter 201 and the 8-bit left and right barrel shifter 202 are connected to an input end 203 and an output end 204.
A 32-bit barrel shift function can be realized by connecting it in series between and.

Next, the operation of the 32-bit left and right barrel shifter having the above structure will be described with reference to FIG. Note that FIG.
[Fig. 7] is a diagram showing an example of a shift operation of a 32-bit left and right barrel shifter, and shows, for example, a 22-bit right shift operation.

When, for example, (a, 0, 2, b, c, f, e, 3: hexadecimal) is input to the input terminal 203 as the input data IN, the byte unit shifter 201 converts the input data into the input data. A 2-byte right shift is performed. as a result,
From the byte unit shifter 201, shift data (0,
0, 0, 0, a, 0, 2, b) is output and input to the left and right 8-bit shifter 202. Then, the right and left 8-bit shifter 202 shifts right by 6 bits.
As a result, the final shift data (0,0,0,0,0,2,8,0) is output from the output terminal 204 from the left and right 8-bit shifter 202. In order to increase the speed of such a shifter circuit, in recent years, it has been studied to shorten the operation cycle by implementing a pipeline (pipeline operation method). That is, this pipeline operation method divides the shift circuit into a plurality of stages and gradually performs the operation as the data moves between the stages, and different data can be processed in different stages. It is possible to input data one after another without waiting for the completion of the data calculation, and to perform the calculation to obtain the result.

[0011]

However, in the conventional shifter circuit described above, when pipelined, the processing throughput is improved by shortening the operation operation cycle, but the result is not obtained after the operation is started. There is a problem in that the usable time, that is, the calculation latency becomes large.

In addition, since there are a considerable number of processes in which the shift result is used in the calculation immediately after it in the normal processing, if the calculation latency is large, even if the circuit is pipelined and the operation cycle is shortened, from the viewpoint of performance. It is also pointed out that the effect is not so great.

The present invention has been made to solve the above-mentioned conventional problems, and an object thereof is to provide a shifter circuit having a short operation cycle and a small operation latency. Another object is to provide a microprocessor provided with this shifter circuit.

[0014]

In order to achieve the above object, the shifter circuit according to the first aspect of the present invention is characterized by a pipelined shifter that divides an input data into a plurality of stages and executes the shift operation. The circuit is provided with a specific shift output means for outputting a shift result for a certain type of shift amount at a stage earlier than the pipeline stage for outputting the final operation result.

According to the first aspect of the invention, paying attention to the fact that the distribution of the required shift amount is biased in the general program, the shift result for a certain specific type of shift amount is output as the final calculation result. Output at a stage earlier than the pipeline stage. As a result, it becomes possible to output the shift result for the shift amount having a high appearance frequency in the first stage of the pipeline stage, which makes it possible to shorten the operation cycle and reduce the operation latency.

The shifter circuit according to the second invention is characterized in that, in the first invention, the shift amount of the specific type is 8
The shift amount is a multiple of.

According to the second aspect of the present invention, the shift result for the shift amount which is a multiple of 8 and which frequently appears is output at the first stage of the pipeline stage.

A feature of the shifter circuit of the third invention is that in the first invention, the shift amount of the specific type is 8
The shift amount is smaller than the bit.

According to the third aspect of the invention, the shift result for the shift amount smaller than 8 bits, which frequently appears, is output in the first stage of the pipeline stage.

A feature of the shifter circuit according to the fourth aspect of the present invention is that the shifter circuit is a pipelined shifter circuit that divides an input data into a plurality of stages and executes the shift operation.
A byte unit shifter that shifts the input data left and right in byte units, a left small bit shifter that operates in parallel with the byte shifter, and shifts a predetermined small number of bits to the left of the input data, and the byte. A selector that selects and outputs one of the output of the unit shifter and the output of the left small bit shifter in the first stage of the pipeline stage, and a pipeline that holds the output of the byte unit shifter for the pipeline It is provided with a register and a right and left small amount bit shifter for shifting a predetermined small amount of left and right with respect to the output data of the pipeline register at the final stage of the pipeline.

According to the fourth aspect of the invention, when the input data is left-shifted by a shift amount smaller than 8 bits, which is a shift amount that frequently appears, the left small-quantity bit shifter shifts the shift amount to the left. And the selector selects and outputs the shift result at the first stage of the pipeline stage. Also, when shifting left and right in byte units, which is a frequently occurring shift amount, the byte shifter shifts left and right by the shift amount, and the selector selects and outputs the shift result in the first stage of the pipeline stage. To do. As a result, it is possible to accurately output the shift result for the shift amount having a high appearance frequency in the first stage of the pipeline stage, and it is possible to shorten the operation cycle and reduce the operation latency.

A feature of the shifter circuit of the fifth invention is that in the fourth invention, the predetermined small amount bit which is the shift amount of the left small amount bit shifter is a bit smaller than 8 bits.

According to the fifth aspect of the invention, since the shift amount of the left small bit shifter is configured to match the shift amount having a high frequency of appearance, the configuration is simplified.

The microprocessor of the sixth invention is characterized by a program counter for storing an instruction address to be executed, and an incrementer circuit for incrementing the instruction address read from the program counter.
An instruction storage unit for reading out an instruction specified by the instruction address output from the incrementer circuit, and an instruction decoder for decoding the instruction read out from the instruction storage unit,
A register file which holds data necessary for executing an instruction and whose read / write operation is controlled according to the decoding result of the instruction decoder, and a value read from the register file according to the decoding result of the instruction decoder In a microprocessor provided with an operation executing unit for executing an operation, the operation executing unit is arranged in parallel with the byte unit shifter and a byte unit shifter for shifting the operand from the register file to the left and right in byte units. The left small bit shifter that performs the operation and shifts the predetermined small number of bits to the left by the input data, and one of the output of the byte unit shifter and the output of the left small bit shifter is used in the first stage of the pipeline stage. Selector to output and select, for pipelined There is provided a shifter circuit having a pipeline register that holds the output of the byte shifter and a right and left small amount bit shifter that shifts the output data of the pipeline register by a predetermined small amount left and right at the final stage of the pipeline. .

According to the sixth invention, the shifter circuit in the microprocessor exhibits the same operation as that of the fourth invention.

A seventh aspect of the present invention is characterized in that, in the sixth aspect, the predetermined small amount bit of the left small amount bit shifter is smaller than 8 bits.

According to the seventh invention, the shifter circuit in the microprocessor exhibits the same operation as that of the fifth invention.

[0028]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a third embodiment according to the present invention.
It is a block diagram of a 2-bit left and right barrel shifter circuit. FIG. 2 is a shift amount distribution diagram showing the basic principle of the shifter circuit in this embodiment.

Before the detailed description of this embodiment, the basic principle thereof will be described.

The shifter circuit according to the present embodiment is a pipelined shifter circuit, and outputs a shift result for a certain type of shift amount at a stage earlier than a pipeline stage that outputs a final result. Is characterized by. In particular, as a shift amount of the above-mentioned specific type, paying attention to the fact that the shift amount distribution of each shift operation in a general program is extremely biased, and the shift amount is a multiple of 8 or 8
A shift amount having a high appearance frequency such as a shift amount smaller than a bit is applied.

The shift amount with high appearance frequency is, specifically,
Left shift within 8 bits, left / right shift by a multiple of 8, shift right to cut out the most significant bit of the operand (that is, in the case of 32-bit data, 31
Right shift of bits), and so on. In particular, the left shift within 8 bits is used when calculating the address of array type data. For example, if the array data is a word, after calculating the index, set the value to 2
The address is calculated by shifting to the left by one bit.
The multiple shift of 8 is used when handling byte data.

In order to clarify the above explanation about the shift amount having a high appearance frequency, the inventor has conducted a part (li, compre) of the benchmark program SPECint92.
(Part of ss, eqnott program execution trace)
When evaluated by using, the appearance frequency of the shift amount as shown in FIG. 2 was obtained. From this figure, it is understood that the shift amount of the shift operation of 90% or more is included in the above categories.

The above-mentioned SPECint 92 is a program selected as a representative of standard programs, and it can be inferred that such a tendency also applies to other programs.

Therefore, for the above-mentioned specific types of shift amounts, by outputting the shift results at an early stage of the pipeline, the shift operation for these shift amounts can output the results with a small latency. it can.

Next, the configuration and operation of this embodiment based on the above-mentioned basic principle will be described.

In the shifter circuit of FIG. 1, the block 10
Reference numeral 1 is a byte unit shifter that shifts the input operand to the left and right in byte units, and performs 8-bit, 16-bit, and 24-bit left and right shifts. The block 102 is a left and right 8-bit barrel shifter and has a shift amount smaller than 8 bits, that is, 7 bits, 6 bits, 5 bits, ...
The shift operation for the shift amount is performed.

The byte unit shifter 101 and the left and right 8-bit barrel shifter 102 are connected to the pipeline register 10.
Byte unit shifter 10 connected in series with 3 in between.
An input operand is supplied to the input end 101a of 1 and the output OUT2 of the second stage which is the final stage of the pipeline stage is sent from the output end 102a of the left and right 8-bit barrel shifter 102.

Similar to the conventional example, the byte unit shifter 101
Is a 4-to-1 selector, and the left and right 8-bit barrel shifter 102 is a 15-to-1 selector. The pipeline register 103 is composed of a flip-flop and is used to pipeline this shifter circuit.

Further, in this shifter circuit, a block 104 is added to the first stage which is the first stage of the pipeline stage. A block 104 is a left 8-bit barrel shifter, which is a byte unit left / right shifter 101.
, And performs a left shift with a shift amount less than 8 bits on the input operand. The left 8-bit barrel shifter 104 is configured by an 8-to-1 selector because it only shifts left by a shift amount smaller than 8 bits.

In the first stage, the selector 105 selects the result of the byte unit shifter 101 and the 8-bit left barrel shifter 104, and sends the selected result to the output end 105a as the output OUT1 of the first stage. .

As the operation of the 32-bit left and right barrel shifter circuit having the above configuration, examples (A), (B) and (C) of actual shift operation will be described with reference to FIGS. 3, 4 and 5.
3 is a diagram showing a calculation example of 2-bit left shift, and FIG. 4 is a diagram showing a calculation example of 16-bit left shift. In addition, FIG. 5 is a diagram illustrating a calculation example of 22-bit right shift.

(A) 2-bit left shift operation The left shift operation within 8 bits has been described as an operation of a shift amount having a high frequency of appearance as shown in the distribution chart of FIG. 2 above. A 2-bit left shift operation having a high appearance frequency will be described.

As shown in FIG. 3, at the input end 101a, (a, 0, 2, b, c,
f, e, 3: “hexadecimal”) is input, the left 8-bit barrel shifter 104 shifts the input operand by 2 bits to the left. As a result, the shift data (8, 0, a,
f, 3, f, 8, c) is output.

This data (8, 0, a, f, 3, f,
8, c) are selected by the selector 105 and output from the output end 105a as the output OUT1 of the first stage. The processing during this period is executed in one cycle.

As described above, with respect to the left shift operation within 8 bits, the shift result can be output in the early stage of the pipeline, so the operation latency becomes small.

(B) The 16-bit left shift operation The left and right shift operations that are multiples of the shift amount have been described as the operation of the shift amount having a high frequency of occurrence, like the left shift operation within 8 bits. For example, a 16-bit left shift operation will be described.

As shown in FIG. 4, at the input end 101a, for example, (a, 0, 2, b, c,
f, e, 3) is input, the byte unit shifter 101
Then, the input operand is left-shifted by 2 bytes. As a result, shift data (c, f, e, 3, 0, 0, 0, 0) is output from the byte unit shifter 101.

This data (c, f, e, 3, 0, 0,
0, 0) is selected by the selector 105 and is output from the output end 105a as the output OUT1 of the first stage. The processing during this period is executed in one cycle.

As described above, the left and right shift operations with a shift amount of a multiple of 8 can also output the shift result at an early stage of the pipeline, so that the operation latency becomes small.

(C) 22-bit right shift operation As a shift operation other than the above-mentioned left shift operation within 8 bits and right / left shift operation of a multiple of 8, for example, a 22-bit right shift operation will be described.

As shown in FIG. 5, at the input end 101a, for example, (a, 0, 2, b, c,
f, e, 3) is input, the byte unit shifter 101
Then, the input operand is right-shifted by 2 bytes. As a result, shift data (0,0,0,0, a, 0,2, b) is output from the byte unit shifter 101 and held in the pipeline register 103. The processing during this period is executed in one cycle.

In the next cycle, the data held in the pipeline register 103 (0, 0, 0, 0, a, 0,
2, b) is input to the left and right 8-bit shifter 102, and the held data is right-shifted by 6 bits. As a result, the final shift data (0,0,0,0,0,2,8,0) is output from the left and right 8-bit shifters 102, and the output end 102a is output as the output OUT2 of the second stage.
Is output from.

Further, in this embodiment, since the pipeline register 103 realizes two-stage pipeline processing, the byte unit shifter 101 or the left 8-bit shifter 104 is used simultaneously with the processing of the second stage. The next cycle of operations can be performed.

As described above, the shift circuit of this embodiment is
Since it is pipelined by the pipeline register 103, it can operate in a shorter cycle than before. The operation cycle time can be shortened by about 60 to 70% of that of the shifter circuit shown in the conventional example of FIG.

Further, in a general program, paying attention to the fact that the distribution of the required shift amount is biased, the shift result for the shift amount having a high appearance frequency is output in the first stage of the pipeline stage. , The result can be output in the first stage for 90% or more shift operation, and the average latency can be reduced.

FIG. 6 is a block diagram showing the structure of a microprocessor to which the shifter circuit of the present invention is applied.

The microprocessor 150 is an instruction execution unit to which the 32-bit left and right barrel shifter circuit of the above embodiment is applied, and is configured as a 32-bit RISC type microprocessor.

The main data flow is that the instruction address read from the program counter 152 is incremented by 1 in the incrementer circuit 151, and the instruction address is sent to the instruction cache 153 and the memory management unit 154.

When the instruction cache 153 hits, the instruction at the address is read and sent to the instruction decoder 155. If the instruction cache 153 does not hit,
Since it is necessary to read the instruction from the external memory, the external memory is accessed via the bus interface 156 to read the data.

The instruction sent to the instruction decoder 155 is converted into an appropriate control signal, and the register file 157 is converted.
And the value read from the register file 157 is sent to the operation execution unit 158 which performs an operation.

The arithmetic execution unit 158 includes the 32-bit left and right barrel shifter circuit 158a of the above embodiment and an ALU.
158b and the address calculation part 158c are provided.
For example, when calculating the address of array-type data (word), the address is calculated by calculating the index and then shifting the value by 2 bits to the left by the shifter circuit 158a.

The calculation result of the calculation execution unit 158 is written back to the register file 157 or used as an address for accessing the data cache 159. The data cache 159 executes load / store with the register file 157 for the input access address. When the data cache 159 misses, an external memory access is performed via the memory management unit 154 similarly to the instruction cache 153.

[0063]

As described in detail above, according to the shifter circuit of the first invention, it is possible to shorten the operation cycle and reduce the operation latency.

According to the shifter circuit of the second aspect of the present invention, in the first aspect of the present invention, the shift result for the shift amount that is a multiple of 8 that frequently appears can be output at the first stage of the pipeline stage. The calculation latency can be reduced more accurately.

According to the shifter circuit of the third aspect of the invention, in the first aspect of the invention, the shift result for a shift amount smaller than 8 bits that frequently appears can be output at the first stage of the pipeline stage, The calculation latency can be reduced more accurately.

According to the shifter circuit of the fourth invention, it is possible to realize a shifter function which has a short operation cycle and a small operation latency.

According to the shifter circuit of the fifth invention, the structure can be simplified in the fourth invention.

According to the microprocessor of the sixth aspect of the present invention, since the shifter circuit having the same effect as that of the fourth aspect of the present invention is mounted, the arithmetic performance can be improved.

According to the microprocessor of the seventh invention, the structure of the shifter circuit in the sixth invention can be simplified.

[Brief description of drawings]

FIG. 1 is a block diagram of a 32-bit left / right barrel shifter circuit according to an embodiment of the present invention.

FIG. 2 is a shift amount distribution diagram showing the basic principle of the shifter circuit in the embodiment.

FIG. 3 is a diagram illustrating a calculation example of 2-bit left shift.

FIG. 4 is a diagram showing a calculation example of 16-bit left shift.

FIG. 5 is a diagram illustrating a calculation example of 22-bit right shift.

FIG. 6 is a block diagram showing a configuration of a microprocessor to which the shifter circuit of the present invention is applied.

FIG. 7 is a block diagram of a conventional 32-bit left and right barrel shifter.

8 is a diagram showing an example of a shift operation of the 32-bit left and right barrel shifter shown in FIG.

[Explanation of symbols]

101-byte unit shifter 102 Left and right 8-bit barrel shifter 103 pipeline register 104 Left 8-bit barrel shifter 105 selector OUT1 First stage output OUT2 Second stage output 151 Incrementer circuit 152 program counter 153 instruction cache 154 Memory Management Unit 155 instruction decoder 158 Operation execution unit 158a shifter circuit 158b ALU 158c Address calculator

Claims (7)

(57) [Claims] 1. In a pipelined shifter circuit that divides a shift operation for input data into a plurality of stages and executes the shift calculation, a shift amount of a certain type is performed at a stage earlier than a pipeline stage that outputs a final calculation result. A shifter circuit comprising a specific shift output means for outputting a shift result for 2. The shifter circuit according to claim 1, wherein the specific type of shift amount is a shift amount that is a multiple of 8. 3. The shifter circuit according to claim 1, wherein the specific type of shift amount is a shift amount smaller than 8 bits. 4. A pipelined shifter circuit that divides a shift operation for input data into a plurality of stages and executes the shift operation. A byte unit shifter that shifts the input data left and right in byte units, and the byte unit. Operates in parallel with the shifter and shifts the input data by a small amount to the left by a small amount left bit shifter, and outputs either the byte unit shifter output or the left small amount bit shifter to the beginning of the pipeline stage. A selector for selecting and outputting at the stage, a pipeline register for holding the output of the byte unit shifter for the pipeline, and a predetermined small amount for the output data of the pipeline register at the final stage of the pipeline. It has a left and right small amount bit shifter that shifts Shifter circuit that. 5. The shifter circuit according to claim 4, wherein the predetermined small amount bit of the left small amount bit shifter is smaller than 8 bits. 6. A program counter for storing an instruction address to be executed, an incrementer circuit for incrementing the instruction address read out from the program counter, and an instruction designated by the instruction address output from the incrementer circuit is read out. An instruction storage unit, an instruction decoder that decodes an instruction read from the instruction storage unit, a register that holds data necessary for executing the instruction, and its read / write operation is controlled according to the decoding result of the instruction decoder. In a microprocessor including a file and an operation execution unit that executes an operation based on a value read from the register file according to a decoding result of the instruction decoder, the operation execution unit includes an operand from the register file. For left and right in bytes A byte shifter that performs a shift operation, a left small bit shifter that operates in parallel with the byte shifter, and shifts a predetermined small number of bits to the left for the input data, an output of the byte shifter, and a left small bit shifter Selector to output one of the outputs of the above in the first stage of the pipeline stage, a pipeline register that holds the output of the byte unit shifter for pipeline processing, and a pipeline register that holds the output in the final stage of the pipeline. A microprocessor provided with a shifter circuit having left and right small amount bit shifters for performing a predetermined small amount of left and right shifts on output data of a pipeline register. 7. The microprocessor according to claim 6, wherein the predetermined small amount bit of the left small amount bit shifter is smaller than 8 bits.