JPS6214866U - - Google Patents
Info
- Publication number
- JPS6214866U JPS6214866U JP1985105349U JP10534985U JPS6214866U JP S6214866 U JPS6214866 U JP S6214866U JP 1985105349 U JP1985105349 U JP 1985105349U JP 10534985 U JP10534985 U JP 10534985U JP S6214866 U JPS6214866 U JP S6214866U
- Authority
- JP
- Japan
- Prior art keywords
- delay
- circuit
- turned
- switching circuit
- power
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000003990 capacitor Substances 0.000 claims description 10
- 238000010586 diagram Methods 0.000 description 5
- 238000005259 measurement Methods 0.000 description 1
Description
第１図はこの考案の一実施例による映像出力遅
延回路を示す図、第２図は従来の映像出力遅延回
路を示す図、第３図は第１図の回路の等価回路を
示す図、第４図は第２図の等価回路を示す図、第
５図はＩＣ１の端子２７を測定箇所としたときの
第１図、第２図の回路の電圧特性を示す図である
。
図において、１はＩＣ、１ａはスイツチング回
路、２ａは外付け回路、２７は遅延端子、Ｃ１，
Ｃ２はコンデンサ、Ｄ１はダイオード、Ｒ１は抵
抗である。なお図中、同一符号は同一又は相当部
分を示す。
FIG. 1 is a diagram showing a video output delay circuit according to an embodiment of the invention, FIG. 2 is a diagram showing a conventional video output delay circuit, FIG. 3 is a diagram showing an equivalent circuit of the circuit in FIG. 4 is a diagram showing the equivalent circuit of FIG. 2, and FIG. 5 is a diagram showing the voltage characteristics of the circuits of FIGS. 1 and 2 when the terminal 27 of IC1 is used as the measurement point. In the figure, 1 is an IC, 1a is a switching circuit, 2a is an external circuit, 27 is a delay terminal, C1,
C2 is a capacitor, D1 is a diode, and R1 is a resistor. In the figures, the same reference numerals indicate the same or equivalent parts.
補正 昭６１．１．３１
実用新案登録請求の範囲を次のように補正する
。Amendment January 31, 1981 The scope of claims for utility model registration is amended as follows.
【実用新案登録請求の範囲】
(1) 映像出力機器に設けられ電源投入時に映像
の出力を遅延するための回路であつて、
映像出力機器の映像表示用デバイスへの映像信
号の送出を制御するためのスイツチング回路と、
該スイツチング回路に設けられこれに電源投入
時の遅延を与えるための遅延端子と、
該遅延端子と基準電位間に接続されたコンデン
サと、
電源オフ時に上記遅延端子を所定時間所定電圧
以上に保持する外付け回路とを備えたことを特徴
とする映像出力遅延回路。
(2) 上記コンデンサは、電源オン時に上記スイ
ツチング回路より上記遅延端子を介して流入する
該スイツチング回路の漏れ電流を充電し、該スイ
ツチング回路は該充電電圧が所定値に達した時オ
ン状態となり、上記遅延端子は電源オフ時上記コ
ンデンサを短時間に放電するものであることを特
徴とする実用新案登録請求の範囲第１項記載の映
像出力遅延回路。
(3) 上記外付け回路は、上記遅延端子にアノー
ドが接続されたダイオードと、該ダイオードに並
列に接続された抵抗と、上記ダイオードのカソー
ドと上記基準電位間に接続されたコンデンサとか
らなるものであることを特徴とする実用新案登録
請求の範囲該１項または第２項記載の映像出力遅
延回路。[Scope of Claim for Utility Model Registration] (1) A circuit provided in a video output device to delay the output of video when the power is turned on, which controls the sending of a video signal from the video output device to a video display device. a switching circuit for switching the switching circuit; a delay terminal provided in the switching circuit for applying a delay when the power is turned on; a capacitor connected between the delay terminal and a reference potential; A video output delay circuit comprising: an external circuit that maintains a voltage above a predetermined voltage. (2) The capacitor charges the leakage current of the switching circuit flowing through the delay terminal from the switching circuit when the power is turned on, and the switching circuit is turned on when the charging voltage reaches a predetermined value; 2. The video output delay circuit according to claim 1, wherein the delay terminal discharges the capacitor in a short time when the power is turned off. (3) The external circuit consists of a diode whose anode is connected to the delay terminal, a resistor connected in parallel to the diode, and a capacitor connected between the cathode of the diode and the reference potential. A video output delay circuit according to claim 1 or 2 of the utility model registration claim, characterized in that:
Claims (1)
の出力を遅延するための回路であつて、 映像出力機器の映像表示用デバイスへの映像信
号の送出を制御するためのスイツチング回路と、 該スイツチング回路に設けられこれに電源投入
時の遅延を与えるための遅延端子と、 該遅延端子と基準電位間に接続されたコンデン
サと、 電源オフ時に上記遅延端子を所定時間所定電圧
以上に保持する外付け回路とを備えたことを特徴
とする映像出力遅延回路。 (2) 上記コンデンサは、電源オフ時に上記スイ
ツチング回路より上記遅延端子を介して流入する
該スイツチング回路の漏れ電流を充電し、該スイ
ツチング回路は該充電電圧が所定値に達した時オ
ン状態となり、上記遅延端子は電源オフ時上記コ
ンデンサを短時間に放電するものであることを特
徴とする実用新案登録請求の範囲第１項記載の映
像出力遅延回路。 (3) 上記外付け回路は、上記遅延端子にアノー
ドが接続されたダイオードと、該ダイオードに並
列に接続された抵抗と、上記ダイオードのカソー
ドと上記基準電位間に接続されたコンデンサとか
らなるものであることを特徴とする実用新案登録
請求の範囲第１項または第２項記載の映像出力遅
延回路。[Scope of Claim for Utility Model Registration] (1) A circuit provided in a video output device to delay the output of video when the power is turned on, which controls the sending of a video signal from the video output device to a video display device. a switching circuit for switching the switching circuit, a delay terminal provided in the switching circuit to provide a delay when power is turned on, a capacitor connected between the delay terminal and a reference potential, and a capacitor connected to the delay terminal for a predetermined period of time when the power is turned off. A video output delay circuit comprising: an external circuit that maintains a voltage above a predetermined voltage. (2) the capacitor charges the leakage current of the switching circuit flowing through the delay terminal from the switching circuit when the power is turned off, and the switching circuit is turned on when the charging voltage reaches a predetermined value; 2. The video output delay circuit according to claim 1, wherein the delay terminal discharges the capacitor in a short time when the power is turned off. (3) The external circuit consists of a diode whose anode is connected to the delay terminal, a resistor connected in parallel to the diode, and a capacitor connected between the cathode of the diode and the reference potential. A video output delay circuit according to claim 1 or 2, characterized in that:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1985105349U JPH0513092Y2 (en) | 1985-07-10 | 1985-07-10 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1985105349U JPH0513092Y2 (en) | 1985-07-10 | 1985-07-10 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6214866U true JPS6214866U (en) | 1987-01-29 |
| JPH0513092Y2 JPH0513092Y2 (en) | 1993-04-06 |
Family
ID=30979696
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1985105349U Expired - Lifetime JPH0513092Y2 (en) | 1985-07-10 | 1985-07-10 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0513092Y2 (en) |
-
1985
- 1985-07-10 JP JP1985105349U patent/JPH0513092Y2/ja not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0513092Y2 (en) | 1993-04-06 |
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