JPS6181328U

JPS6181328U -

Info

Publication number: JPS6181328U
Application number: JP16368584U
Authority: JP
Priority date: 1984-10-31
Filing date: 1984-10-31
Publication date: 1986-05-30

Description

[Brief explanation of the drawing]

第１図は本考案の論理回路のリセツト回路の一
実施例を示した回路図、第２図は第１図の回路の
動作波形タイミング図、第３図は従来の論理回路
のリセツト回路の一例を示した回路図、第４図は
第３図の回路の動作波形タイミング図である。１，７…抵抗、２…コンデンサ、３，６…ダイ
オード、５…トランジスタ。 Fig. 1 is a circuit diagram showing an embodiment of the reset circuit of the logic circuit of the present invention, Fig. 2 is an operation waveform timing diagram of the circuit of Fig. 1, and Fig. 3 is an example of the reset circuit of the conventional logic circuit. FIG. 4 is an operation waveform timing diagram of the circuit shown in FIG. 3. 1, 7...Resistor, 2...Capacitor, 3, 6...Diode, 5...Transistor.

Claims

[Scope of utility model registration request]

a capacitor charged by a power supply that operates the logic circuit; and a first capacitor connected to this capacitor.
a time constant circuit consisting of a resistor; and a first circuit that becomes conductive when the terminal voltage of the capacitor exceeds the power supply voltage and becomes a discharge path for the charge charged in the capacitor.
a second resistor that generates a reset signal voltage by introducing current from the power supply when the power is on and from the capacitor when the power is off, and a second resistor that is turned on by the terminal voltage of the capacitor. , a transistor that is turned off and controls the flow of current to the second resistor, and a third diode that adjusts the on/off timing of this transistor. circuit.