JPS6214788B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for inspecting circuit boards such as printed circuit boards.

Methods for testing circuit boards such as printed circuit boards include an operation check method in which operation is confirmed by operating the circuit, and a DC check method in which the voltage at each measurement point is measured. Although the former method can be tested at low cost, it has the disadvantage of poor reliability because even if a circuit constant is abnormal when a different circuit element is inserted and connected to a board, it may not be recognized as an abnormality in circuit operation. In the latter DC check method, it is necessary to determine a standard voltage value for each check point, store it in a memory device, and then compare this stored data with measured data, which has the disadvantage of increasing the price of the device. There is. Furthermore, in order to convert measurement data into digital values, an A/D converter that operates at low speed is required, resulting in an increase in measurement time. Furthermore, an increase in the number of measurement points is unavoidable, which leads to a decrease in reliability due to poor contact of the contacts.

SUMMARY OF THE INVENTION An object of the present invention is to provide a highly reliable circuit board testing method with an extremely simple configuration.

In the testing method of the present invention, a reference circuit board having a circuit board to be tested and a circuit network to be standard for this board is prepared, and first and a second check point, connect the first check point of the circuit board to be inspected and the second check point of the reference circuit board at the common connection point, and connect the second check point of the circuit board to be inspected to the reference circuit board. A constant voltage V is applied between the first check point and the voltage at the common connection point is detected to be within V/2 (1±δ) (±δ indicates the error range). This is a method of inspecting the quality of a circuit board by sequentially switching the selection of the first and second check locations while determining the quality of the circuit between the first and second check locations of the circuit board, the method comprising: A plurality of circuit boards are prepared, and the first and second check points corresponding to the first and second check points of the circuit board to be inspected on any two circuit networks of these boards are selected, respectively, and the first and second check points of the reference circuit board are selected. and the second check point are connected at a common connection point, and a voltage V is applied between the second and first check points of both reference circuit boards to detect the voltage at this common connection point. While selecting the two combinations as appropriate, find the data corresponding to the maximum value of the error range ±δ in the voltage of the common connection point,
The present invention is characterized in that this data is used to set the error range ±δ when determining the quality of the circuit between the first and second check points of the circuit board to be inspected.

The present invention will be explained below based on the drawings.

FIG. 1 is a schematic diagram of the circuit network of the circuit board to be inspected, where Z ₀ to _{Z 11} indicate basic circuits or elements,
TP ₀ to TP ₅ are check terminals indicating check points. FIG. 2 is a schematic diagram of the circuit network of a reference circuit board that has a circuit network that should be the standard for this circuit board to be tested, that is, a good sample circuit board that has a normal circuit network _{. -Z11} ' indicate basic circuits or circuit elements, and _TP0 ' to _TP5 ' are check terminals indicating check points. In both figures, each check terminal TP ₀ ~ TP ₁₁ and TP ₀ ′ ~
It is assumed that TP ₁₁ ' are provided at corresponding and equal locations on the circuit network.

After preparing such two circuit boards, consider the operation of the connected state shown in FIG. 3, for example. That is, when determining the quality of the circuit between the first and second check terminals TP ₀ and TP ₁ of the circuit board to be inspected shown in FIG. 1, for example, a constant positive voltage +V is applied to the check terminal TP ₀ . The other check terminal TP ₁ is directly connected to the corresponding first check terminal TP ₀ ' of the reference circuit board, and the other corresponding second check terminal TP ₁ ' of the reference circuit board is grounded. . At this time, assuming that no power supply voltage is applied to the circuit networks of both circuit boards, the first and second check terminals _TP0 and
DC impedance component X ₁ between TP ₁ and the first and second check terminals TP ₀ ' of the reference circuit board
If _the DC impedance component X ₁ ′ between terminals TP _{1 ′} and
It is clear that V ₀ is V/2. In other words, short circuits due to solder bridges, open circuits due to pattern breakage, erroneous resistance, etc. occur between terminals TP ₀ and TP ₁ .
If there is a defect such as a missing item or reverse insertion of a semiconductor element, the potential V ₀ of the connection point will deviate from V/2, and as a result, by knowing the potential state of this connection point, the circuit between both terminals can be corrected. It can be seen that it is possible to determine the quality of the product. Here, since there naturally exists a certain range of variation between circuit elements, the potential V ₀ at the connection point fluctuates within a range of V/2 (1 ± δ). If the value is within the range, the circuit between both terminals may be determined to be good. Note that δ is a value indicating a certain error range and is determined by the circuit network and the like.

A general example of the principle shown in Figure 3 is shown in Figure 4.
1 is a schematic equivalent circuit diagram illustrating an embodiment of the present invention. FIG. A selection switch S1 is provided to selectively apply a constant voltage +V to one check terminal of the circuit board to be inspected, and a selection switch _S1 is provided to selectively apply _a constant voltage ₊ V to one check terminal of the circuit board under test. A selection switch _S2 is provided for selecting the check terminal _TP3 . and a check terminal corresponding to check terminal TP ₂ selected by switch S ₁ on the circuit board to be tested of the reference circuit board.
A switch _S3 is provided which selects TP2' and connects it to the check terminal _TP3 of the circuit board to be inspected selected by the previous switch _S2 , and also connects the check terminal _TP3 selected by the switch _{S2 .} A switch _S4 is provided for selecting and grounding the check terminal _TP3 ' of the reference circuit board corresponding to the reference circuit board.

In order to detect the potential V ₀ at the common connection point of switches S ₂ and S ₃ , first and second comparators 1 and 2 are connected.
is provided, and this potential V ₀ serves as one input. As the other inputs, the divided voltage outputs V ₁ and V ₂ of the voltage dividing circuit 3 that divides the reference voltage source +V are used, respectively. For example, as shown in the figure, this voltage dividing circuit 3 consists of resistors R ₁ , R ₂ and resistors R ₁₀ to _{R 1o} , and one of the resistors R ₁₀ to R _1o having different values from each other.
By selecting one using the switch _S5 , it becomes possible to determine the error range ±δ due to variations in circuit elements. By doing this, V/2(1
When a voltage V ₀ exceeding ±δ) is input to the comparators 1 and 2, the outputs OUT-1 and OUT-2 of either the comparators 1 and 2 change accordingly, making it possible to determine an abnormality. The comparators 1 and 2 constitute a so-called window comparator.

It is clear that the quality of the circuit between any two check terminals of the circuit board to be tested can be tested by appropriately controlling each of the switches _S1 to _S4 .

Note that a constant positive (or negative) voltage may be applied to one of the check terminals on the reference circuit board side.In short, a set of corresponding check terminals on both circuit boards is connected to the opposite check terminals. Of course, a constant voltage may be applied between TP ₃ and TP ₂ ' in FIG. 4, for example.

The switches S ₁ to _{S 4} and S ₅ can be controlled according to a program determined by a control device such as a microcomputer, and the outputs OUT-1 and 2 can also be determined by a microcomputer or other control device. If a processor makes processing decisions and visually displays them, it will become an extremely high-speed device. An example of the control mode by such a control device is shown in the fifth example.
It is shown in the figure as a block diagram, and in the figure, parts equivalent to those in FIG. 4 are designated by the same reference numerals.
Reference numeral 10 denotes a stylus for selecting and connecting check terminals, and includes switch control circuits 111 and 112 for controlling switching of switches S ₁ , S ₃ and S ₂ , S ₄ . Reference numeral 11 is a voltage detection unit that detects the voltage V ₀ at the common connection point of the check terminals, and a switch control circuit 113 that controls switching of the switch S ₅ that selects the resistors R ₁₁ to R _1o that determine the error range ±δ.
Contains. 12 is the switch control circuit 1
For example, it is a microcomputer that generates control signals 11, 112, and 113 according to a predetermined procedure, and includes a CPU (central processing unit) 114, RAM
(Random access memory) 115, P-ROM
(Programmable read-only memory) 116,
117 and a keyboard 118, and each of these units 114 to 118 and a switch control circuit 1.
I/O port 119 that connects with ports 11 to 113
It also has the following.

A method for setting the value of the error range ±δ in such a configuration will be explained using the flowchart shown in FIG.
In this example, the resistances _R10 to _R1o for generating the reference voltage in the voltage detection section 11 are _R10 to _R15.
Assuming that six resistances have different values, variable setting of ±δ is possible in six steps, but the invention is not limited to this. It is assumed that the resistor R is selected to have a larger value in order from ₁₀ and the values of ±δ become larger in order.

Prepare a plurality of standard circuit boards that are non-defective samples in advance, select any two of these boards, connect the check terminals of these boards in order with the stylus 10 through switches S ₁ to S ₄ , and set the voltage V. Perform an application test. For this purpose, if the start switch on the keyboard 118 is operated, the P-ROM 116
Detection of ±δ is performed by a program stored in the program according to the flowchart shown in FIG.

That is, the j-th check terminal TPj of the first reference circuit board and the k-th check terminal of the second reference circuit board.
A voltage V is applied between the reference circuit board TPk and the k-th check terminal TPk of the first reference circuit board and the j-th check terminal TPj of the second reference circuit board at a common connection point. The resistor R _1l that defines ±δ is then selected by the switch S ₅ . This step is indicated as a "detection level l" (l is an integer from 0 to 5). Output of comparators 1 and 2 at this time
OUT-1 and OUT-2 make a pass/fail judgment, and if it is OK, the check terminals TPj and TPk of the other two reference circuit boards stored at addresses j and k of the RAM 115 are checked. Data corresponding to the maximum error range ±δ is read out. This step is designated as "LOADjk". This read data, that is, the detection level (indicated as level jk) which is data corresponding to the maximum error range up to the previous time, is compared in magnitude with the detection level l detected this time. This step is shown as "level jk>l". If “NO” in this comparison step, the maximum error range ±δ between terminals TPj and TPk needs to be updated, so the RAM 115
The contents of addresses j and k are newly stored as level l. This step is designated as "STOREikl".

If ``YES'' at the step of ``level jk >l'', the maximum error range ±δ between terminals TPj and TPk does not need to be updated, so the next check terminal TPk+1 and
In order to perform a test with respect to Tj, the process proceeds to step "k=k+1".

The judgment result is “NG” in step “NG?”
If so, the error range is even larger, so the resistance R ₁ l
The same test as above is performed using the detection level (l+1) as the next resistor R ₁ (l+1). By performing this procedure on the two reference circuit boards and sequentially on the other two reference circuit boards, the check terminals TPj and TPk are
It can be seen that the maximum error range ±δ is set between.
Therefore, all the data indicating the maximum error range ±δ between the check terminals obtained in this way are stored in the RAM 11.
When stored in P-ROM1, this content is stored in P-ROM1.
17 using a P-ROM writer 120 or the like, and a normal inspection of the circuit board to be inspected is performed according to the flowchart shown in FIG.
The program shown in the flowchart is also P-
It is stored in the ROM 116.

The quality of each check terminal TPj, TPk is determined using the circuit board to be inspected and one reference circuit board. At this time, the voltage V ₀ at the common connection point between each check terminal TPj, TPk during checking is determined. The data indicating the maximum value of the error range ±δ of V/2 (1±δ) is read from addresses j and k of the P-ROM 117 (LOAD jk), the switch _S5 is switched, and the resistor R _1o selection has been made {detection level = (jk)}. At this time, the outputs OUT-1 and 2 of comparators 1 and 2 are judged (NG?), and RAM1
Data indicating the quality is stored at addresses j and k in 5. The measurement results are visually displayed on the display section of the keyboard, but this may be displayed on a lamp or CRT, or printed out, or a combination of both may be used.

Regarding the setting of the error range in the above-mentioned inspection method, by preparing a large number of non-defective samples, the value of the maximum error range set can be obtained with sufficient accuracy. However, in reality, because there is a limit to the number of non-defective samples, the value of the maximum error range cannot be obtained with sufficient accuracy, and as a result, there is a possibility that the circuit board to be inspected, which should originally be a non-defective product, will be judged as "NG". also occurs. A schematic diagram of another embodiment of the invention that overcomes these drawbacks is shown in FIG. In the figure, parts equivalent to those in FIG. 4 are designated by the same reference numerals.

In this example, a switch S ₆ , a resistor R 3 and a switch are connected across series resistors R ₁ and R ₂ of a voltage divider circuit 3 that generates reference voltages for comparators 1 and ₂ , respectively.
A series circuit of S ₇ and resistor R ₄ is installed in parallel to set the reference voltage.
It is designed to control V ₁ and V ₂ respectively.
Here, the error range ±δ when switches S ₆ and S ₇ are in the open state is determined. If the value of the resistor R _1l selected by the switch S ₅ is R _X , then V ₁ /V=1+ _δ /2, V ₂ /V _{=1 −} δ ₂ /R ₁ +R ₂ +R _X , and if R ₁ =R ₂ , then V ₁ /V=R _X +R ₁ /2R ₁ +R _X. Therefore, ±δ is given by the following equation.

_{± δ} =±R _{X / 2 /} R _{1 + R} All you have to do is replace it with +R ₃ (
R ₃ = R ₄ ), the error range ±δ' is given by the following formula.

±δ′=±R _X /2/R ₁・R ₃ /(R ₁ +R ₃ )+
R _x /2 (2) That is, it can be seen that δ' increases at a constant rate with respect to δ. Therefore, a plurality of non-defective sample circuit boards are checked according to the flowchart shown in Fig. 6 with both switches S ₆ and S ₇ opened, error range data is collected, and the circuit boards are inspected based on this. At this time, if switches S ₆ and S ₇ are closed and a check is performed according to the flow chart shown in Fig. 7,
Since the error range shown by equation (2) is set, it is advantageous that errors in error setting due to a small number of non-defective samples can be corrected.

As mentioned above, according to the present invention, since the optimum error range is set between the check terminals of the circuit under test and the check is performed, high accuracy and high accuracy can be achieved without using the standard deviation using an expensive system such as a minicomputer. Circuit boards can be inspected at low cost.

[Brief explanation of the drawing]

Figure 1 is a schematic diagram of the circuit network of the circuit board to be inspected, Figure 2 is a schematic diagram of the circuit network of a reference circuit board that is a good sample that should be the standard for the circuit board to be inspected in Figure 1, The figure is a schematic diagram for explaining the principle of the present invention, Figure 4 is a schematic diagram for explaining an embodiment of the invention, Figure 5 is a block diagram of an embodiment of the invention, and Figure 6 is a schematic diagram for explaining an embodiment of the invention. FIG. 7 is a flowchart for setting an error range in an embodiment of the present invention. FIG. 7 is a flowchart for testing a circuit board to be tested in an embodiment of the present invention. FIG. 8 is a flowchart for setting an error range in an embodiment of the present invention. FIG. 3 is a schematic diagram for explaining an example. Explanation of symbols of main parts TP ₀ to _{TP o} ...Test circuit board check terminal, TP ₀ ' to TP _o '...Reference circuit board check terminal, _S1 to _S4 ...Check terminal selection switch, _S5 ...Error range setting Resistance selection switch.

Claims (1)

[Scope of Claims] 1. Any corresponding first check points of each circuit network of a circuit board to be inspected and a reference circuit board having a circuit network to be a standard for this circuit board to be inspected. connect the first check point of the circuit board to be inspected and the second check point of the reference circuit board at a common connection point, and select the second check point of the circuit board to be inspected. and the first of the reference circuit board.
A constant voltage V is applied between the test point and the circuit board to be inspected, and it is detected that the voltage at the common connection point is within V/2 (1±δ) (±δ indicates the error range). An inspection method for inspecting the quality of a circuit board by sequentially switching the selection of the first and second check locations while determining the quality of the circuit between the first and second check locations of the reference circuit board. A plurality of circuit boards are prepared, and the first and second check points corresponding to the first and second check points of the circuit board to be inspected are selected on any two circuit networks of these boards, and the test points of these reference circuit boards are selected. The first and second check points are connected at the common connection point, and the voltage V is applied between the second and first check points of both reference circuit boards to detect the voltage at the common connection point. While appropriately selecting two combinations of reference circuit boards, data corresponding to the maximum value of the error range ±δ in the voltage of the common connection point is obtained, and using the data, the first and second combinations of the circuit boards to be tested are determined. 1. An inspection method characterized in that the error range ±δ is set when determining whether or not the check points are good or bad. 2 The detection of the voltage at the common connection point is V/2 (1
2. The inspection method according to claim 1, wherein the reference voltage (±δ) and the voltage at the common connection point are compared by a comparator. 3. The inspection method according to claim 2, wherein the value of ±δ of the reference voltage is configured to control the resistance value of a resistor for generating the reference voltage in accordance with the data. 4 The reference voltage is a first voltage that divides the constant voltage.
and a divided voltage output of a series connection circuit of a second voltage dividing resistor and an error range setting resistor that defines the error range. . 5. The inspection method according to claim 4, wherein the error range is set larger by controlling each resistance value of the first and second voltage dividing resistors to be small.