JPS62147758A - Semiconductor device - Google Patents

Abstract

PURPOSE:To independently check each logic block by setting the input of each logic block to only the internal bus and external input and also setting the output of each logic block to only internal bus and external output. CONSTITUTION:A device comprises an internal bus 13, logical blocks 1, 14, an external output 15 from logical block 1, an external input 16 to logical block 1, logical blocks 2, 17, an external output 18 from logical block 2, an external input 19 to logical block 2 and input/output changeover circuit 20 connecting internal bus 13, external bus output 21 and external bus input 22. Thereby, it is possible to independently and separately check each logic block forming logic IC.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a logic semiconductor integrated circuit (hereinafter referred to as logic IC) K having a common multiplier signal line (hereinafter referred to as bus) structure.

(Prior Art) In a logic IC having a bus structure, each logic block is connected to each other by an address bus, a data bus, a control signal bus, etc. to transmit signals.

FIG. 1 shows an example of the basic configuration of a bus structure logic IC. In Fig. 1, the internal bus is shown, 2 is the logic block 1, 3 is the output from the logic block 1 to the outside of the chip, 4 is the input to the logic block 1 from outside the chip, and 5 is the output from the logic block 2 to the logic block 1. , 6 is the output from logic block 1 to logic block 2, 7 is the output from logic block 2.8 is the output from logic block 2 to the outside of the chip, 9 is the output from logic block 2
These are inputs from outside the chip to the chip, and these are integrated on one chip, and the input/output (11, 12
) is now possible.

Inspection series (hereinafter referred to as
If the number of logic elements constituting the logic IC is G, then the test pattern is approximately G squared to 3
It is necessary to multiply Therefore, when a logic IC is divided into a plurality of logic blocks that can be independently tested, the number of test patterns is significantly reduced. As an example, if we divide N, the number of test patterns after division G' is assumed to be proportional to the square of the number of logic elements, and the number of test patterns after division is the number of test patterns before division. N of
It becomes 1/1.

However, in a conventional logic IC having a bus structure, as shown in FIG. 1, in addition to the input from the internal bus 1 and the input 4 from outside the chip, there is an input 5 from the logic block 2 as an input to the logic block 1.

Further, as outputs of the logic block 1, there is an output 6 to the logic block 1 in addition to an output to the internal path 1 and an output 3 to the outside of the chip. Therefore, logical block 1 and logical block 2 cannot be tested independently, and logical block 1
, 2 were not examined together, and -C was not obtained. This required many test patterns and was time consuming.

(Object of the Invention) An object of the present invention is to provide a semiconductor device having a circuit configuration that eliminates an increase in test patterns and an increase in inspection time.

(Description of Embodiment) As shown in FIG. 2, an embodiment of the present invention eliminates the signal line connecting logic block 1 and logic block 2, and makes the inputs of each logic block only internal paths and external inputs. It is characterized in that the outputs of each logic block are only internal paths and external outputs. This makes it possible to independently divide and test each logical block. In Figure 2, 1
3 is an internal path, 14 is logic block 1, 15 is an external output from logic block 1, 16 is an external input to logic block 1, 17 is logic block 2, 18 is an external output from logic block 2, 19 is logic External input to block 2, 2
0 is an input/output switching circuit that connects the internal path 13, the bus external output 21, and the bus external human power 22.

According to this invention, as shown in the figure, the logic IC
It becomes possible to independently divide and inspect each logical block that constitutes the system, and it is possible to provide a product that is easy to inspect.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a conventional bus configuration logic IC, and FIG. 2 is a block diagram of an easily testable bus configuration logic IC according to the present invention. 1.13... Internal path, 2,14...
Logical block 1.3, 15...Logic block 1
External output from 4.16...Logic block 2
External input to, 5... Output from logic block 2 to logic block l, 6... Output from logic block 1 to logic block 2, 7.17... Logic block 2.8.18...external output from logic block 2, 9,19...external input to logic block 2, 10.20...input/output switching circuit, 11
．． 21...Bus external output, 12.22...River...
Bus external input. \, l

Claims (1)

[Claims] In a logic semiconductor integrated circuit with a bus configuration, the input side of each logic block is connected only to the external input terminal and bus to that logic block, and the output side of each logic block is connected only to the external output terminal and bus of that logic block. A semiconductor device characterized by: