JPS62147026U - - Google Patents

Info

Publication number
JPS62147026U
JPS62147026U JP3132086U JP3132086U JPS62147026U JP S62147026 U JPS62147026 U JP S62147026U JP 3132086 U JP3132086 U JP 3132086U JP 3132086 U JP3132086 U JP 3132086U JP S62147026 U JPS62147026 U JP S62147026U
Authority
JP
Japan
Prior art keywords
memory card
signal line
data processing
processing device
interface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3132086U
Other languages
Japanese (ja)
Other versions
JPH0441403Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP3132086U priority Critical patent/JPH0441403Y2/ja
Publication of JPS62147026U publication Critical patent/JPS62147026U/ja
Application granted granted Critical
Publication of JPH0441403Y2 publication Critical patent/JPH0441403Y2/ja
Expired legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本考案の一実施例を示した斜視図、第
２図は第１図で示したコネクタ部を介して接続さ
れる入出力回路例を示した回路図、第３図は従来
のデータ処理装置とメモリカードのインタフエー
スを構成するコネクタ部の一例を示した斜視図で
ある。 １〜２０…雄型コネクタ（ピン）、５０…デー
タ処理装置、６０…メモリカード。 Fig. 1 is a perspective view showing one embodiment of the present invention, Fig. 2 is a circuit diagram showing an example of an input/output circuit connected via the connector shown in Fig. FIG. 2 is a perspective view showing an example of a connector section that constitutes an interface between a data processing device and a memory card. 1 to 20...Male connector (pin), 50...Data processing device, 60...Memory card.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] コネクタにより、メモリカードをデータ処理装
置に着脱するインタフエースにおいて、上記コネ
クタはデータ処理装置にメモリカードを逆差しし
た場合、データ処理装置側の信号線ライン及び電
源ラインが電気的破壊を惹起しないメモリカード
側の信号線ライン及び電源ラインに接続され、且
つ、メモリカードをイネーブルとする信号ライン
が開放状態となるように前記信号線ライン及び電
源ラインが割振られたインタフエース信号配置と
なる様に設定することを特徴とするメモリカード
インタフエース。 In an interface where a memory card is inserted into and removed from a data processing device using a connector, the connector is used to connect the memory card so that the signal line and power line on the data processing device side will not cause electrical damage when the memory card is inserted into the data processing device upside down. Set the interface signal arrangement so that the signal line and power line are allocated so that the signal line connected to the signal line and power line on the card side and the signal line that enables the memory card is in an open state. A memory card interface characterized by:
JP3132086U 1986-03-06 1986-03-06 Expired JPH0441403Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3132086U JPH0441403Y2 (en) 1986-03-06 1986-03-06

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3132086U JPH0441403Y2 (en) 1986-03-06 1986-03-06

Publications (2)

Publication Number Publication Date
JPS62147026U true JPS62147026U (en) 1987-09-17
JPH0441403Y2 JPH0441403Y2 (en) 1992-09-29

Family

ID=30836944

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3132086U Expired JPH0441403Y2 (en) 1986-03-06 1986-03-06

Country Status (1)

Country Link
JP (1) JPH0441403Y2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2022041281A (en) * 2020-08-31 2022-03-11 キオクシア株式会社 Memory system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2022041281A (en) * 2020-08-31 2022-03-11 キオクシア株式会社 Memory system

Also Published As

Publication number Publication date
JPH0441403Y2 (en) 1992-09-29

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