JPS6214697A - Musical sound signal generator - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a musical tone signal generating device, and more particularly, to a musical tone signal generating device that sequentially switches and generates a plurality of different musical sound waveforms to generate a musical tone signal whose spectral components change over time. The present invention relates to a musical tone signal generating device.

[Conventional technology]

Japanese Patent Application Laid-Open No. 58-95790 discloses a musical tone signal generating device that can generate musical tone signals whose spectral components change over time by sequentially switching and reading out a plurality of different musical waveforms stored in a waveform memory. There is. In this case, the tone waveform to be read from the waveform memory is switched when the same tone waveform is repeatedly read out for a predetermined number of cycles. Therefore, since the switching interval of the musical sound waveform is always fixed at a predetermined number of cycles,
There is a drawback that the switching interval of the musical sound waveform varies depending on the frequency of the musical tone to be generated, and the time required for interpolation also varies accordingly.

In order to eliminate such drawbacks, the patent application No. 59-266
No. 7 discloses that the waveform switching is performed according to a predetermined number of times, thereby making it possible to control the switching of the musical sound waveform without being influenced by the frequency of the musical sound to be generated.

[Problem that the invention seeks to solve]

However, in the above-mentioned Japanese Patent Application No. 59-2667, the waveform is switched immediately when the output of the counting means that generates the time function reaches a predetermined value, and the phase of the musical sound waveform that has been generated up to that point is changed. is not considered at all. Therefore, a situation may occur in which the musical sound waveform before switching is interrupted at a phase in the middle of one cycle, and the musical sound waveform after switching is generated continuously from the interrupted phase, resulting in unnatural waveform changes. This invention has been made in view of the above-mentioned points, and it is an object of the present invention to provide a musical tone signal generating device that prevents unnatural waveform changes from occurring when switching musical waveforms. That is.

[Means for solving problems]

A musical tone signal generating device according to the present invention includes a waveform storage means that stores waveform data of a plurality of different musical sound waveforms, and a reading means that reads out waveform data of a predetermined musical sound waveform from the waveform storage means according to a musical tone frequency to be generated. a waveform specifying means for temporally switching and specifying a musical sound waveform to be read from the waveform storage means; an interpolation means for weighting a waveform, a counting means for generating a time function for setting a time change in weighting in the interpolation means; and a count means for generating a time function for setting the time change of the weighting in the interpolation means, and an output of the counting means and the current reading by the reading means. The present invention is characterized by comprising a switching control means for controlling waveform switching in the waveform specifying means in accordance with information indicating the phase of the waveform data.

Further, the present invention is not limited to a system in which a musical tone signal is formed by reading out a musical sound waveform stored in a waveform storage means, but can also be applied to a system in which a musical tone signal is formed using parameters. . That is, the second
The musical sound signal generating device according to the invention includes a musical sound waveform forming means that forms a musical sound waveform having a shape determined by parameters and also forms the musical sound waveform in accordance with a phase specified by phase data; Concerning the musical sound waveform, parameter storage means stores the parameters that determine the shape of each musical sound waveform, and phase data that generates the phase data that changes according to the frequency of the musical sound to be generated and provides it to the musical sound waveform forming means. generating means and the musical sound waveform to be formed by the musical sound waveform forming means by temporally switching and specifying the same, and reading out the parameters corresponding to the designated musical sound waveform from the parameter storage means and providing the waveform designation to the musical musical sound waveform forming means. and an interpolation means for weighting both tone waveforms so as to smoothly transition from the preceding tone waveform to the next tone waveform when switching the tone waveform to be formed, wherein the weighting in the interpolation means is performed. a counting means for generating a time function for setting a time change of the waveform, and a waveform switching in the waveform specifying means according to the output of the counting means and information indicating the phase of the waveform data currently being read by the reading means. The present invention is characterized in that it includes a switching control means for controlling.

[Effect]

The counting means generates a predetermined time function, and the interpolation means sets a time change in weighting according to this time function. The switching control means controls waveform switching at a predetermined time point according to the output of the counting means, that is, the time function. The waveform designation means switches the designation of musical waveforms under the control of the switching control means. In this way, the switching and interpolation of musical waveforms is controlled according to a unique time function that is not proportional to the musical frequency, resulting in a time-varying effect of spectral components that is unaffected by changes in pitch, and smooth in any range. accurate interpolation (waveform transition) is guaranteed. Furthermore, the waveform switching control by the switching control means is performed by taking into account not only the output of the counting means, that is, the time function, but also the phase of the waveform data currently being read by the reading means. Therefore, even if the output of the counting means reaches a predetermined value, the waveform is not switched immediately, but a suitable phase is determined by referring to the phase of the musical waveform that has been generated up to that point (that is, the current phase of the waveform data). Waveform switching is performed when This can prevent unnatural changes from occurring when switching waveforms.

The way to refer to the phase is to refer to the phase of the preceding tone waveform (
It is preferable to detect that the current readout phase has reached its final phase, and to perform waveform switching based on this condition.

Alternatively, the waveform switching may be performed on the condition that the phase of the preceding tone waveform (the current readout phase) substantially matches the initial phase of the tone waveform to be switched next.

〔Example〕

Hereinafter, one embodiment of the present invention will be described in detail with reference to the accompanying drawings.

First, the principle of musical tone signal generation employed in the embodiment described below will be explained with reference to FIG. Figure 1 (
In a), the outline of the musical sound waveform that should be prepared in advance in the waveform memory is shown only as an amplitude envelope for convenience. Since the musical sound waveform of a predetermined period (attack portion) from the start of sound generation changes in a complicated manner, it is difficult to imitate a high-quality attack portion waveform by repeatedly reading out a one-cycle waveform. Therefore, it is assumed that the musical sound waveform of this attack section is obtained by directly sampling a continuous multi-cycle waveform and storing it in a waveform memory. Regarding the entire sound generation period after the attack portion, one cycle of a plurality of different tone waveforms is discretely sampled during the period, and each period is stored in a waveform memory. In FIG. 1(a), each one-period waveform sampled discretely in this manner is indicated by 5EG1 to 5EG5, and for convenience, these will be referred to as segment waveforms.

The basic method of reading out waveforms from the waveform memory that stores waveforms as described above is to first read out all the waveforms of the attack part continuously, and then read out the segment waveforms 5EG1 to 5EG1 at the timing according to a waveform switching command as described later. 5EG5 are selected in order, and one cycle of the selected segment waveform is repeatedly read out.

For example, after the readout of the attack portion waveform is completed, the first segment waveform 5BGI is repeatedly read out for a certain amount of time, then switched to the second 7' segment waveform 5EG2 and read out repeatedly, and thereafter the segment waveforms are sequentially switched.

When switching segment waveforms, interpolation techniques are used to provide a smooth transition from a preceding waveform to the next waveform. In addition to the basic readout method described above, at least the preceding segment waveform and the following segment waveform are read out in the interval where interpolation is to be performed, and both are weighted respectively according to an appropriate interpolation function. . - As an example, the entire switching interval of segment waveforms corresponds to the interpolation interval, and the first segment waveform 5EG1
When reading out the second segment waveform 5BG2, the second segment waveform 5BG2 is also read out, and at the next switching, the second and third segment waveforms 5EG2 and 5EG3 are read out together. read out.

FIG. 1(b) shows an example of an interpolation function.

The solid line indicates the interpolation function IPF1 for the first series, and the broken line indicates the interpolation function IPF2 for the second series. The first series corresponds to one of the two segment waveforms read out for interpolation as described above, and the second series corresponds to the other.

The interpolation functions IPF1 and IPP2 indicate the amount of weighting of the waveform amplitude of each series, and the minimum value is zero (indicating that the waveform is not output). In the attack section that does not perform interpolation, the first series interpolation function IPFI is maintained at the maximum value, and the second series interpolation function IPF2 is maintained at the minimum value. After the attack part ends, segment waveforms 5EG1 to 5E
Each interpolation function IPF1 in the period in which G5 interpolation is to be performed.
．． Each IPF'2 changes over time with predetermined characteristics. Both interpolation functions IPF1 and lPP2 change with opposite characteristics,
As the weighting of one series falls off, the other gradually increases, thereby achieving a smooth waveform transition. In Fig. 1(b), the interpolation functions IPF1, lPP
2 shows linear interpolation characteristics, but it is of course not limited to this.

t* t2r "S e t4 indicates separate interpolation intervals, and the slopes of the interpolation functions IPF1 and lPP2 of each series are switched alternately every time the interpolation interval is switched.Interpolation interval t1 , interpolation is performed to smoothly transition from segment waveform 5EG1 to segment waveform 5EG2. In this process, segment waveform 5EG1 is repeatedly read out in the first series, and segment waveform 5EG2 is repeatedly read out in the second series. While the interpolation function IPFI of the first series decreases from the maximum value, the interpolation function IPF2 of the second series gradually increases from the minimum value.The multiple cycles of the segment waveform 5BG1 repeatedly read out in the '1st series by this interpolation function IPF1 A segment waveform 5EG2 in which the waveform signal is weighted (amplitude controlled) and read out repeatedly in the second series by the interpolation function IPF2.
The multi-period waveform signals are weighted. Mixing both series of waveform signals weighted with opposite characteristics in this way (
From this, segment waveform 5EG1 to segment waveform 5
A musical tone signal whose waveform changes smoothly over time as EG2/> is obtained.

In the next interpolation section "," interpolation is performed to smoothly transition from the segment waveform 5EG2 to 5EG3. In this case, segment waveform 5E is used in the second series following the previous time.
G2 is repeatedly read out, while in the first series, the segment waveform is switched from 8BG1 to 5EG3 and this is repeatedly read out.

Then, the slopes of the interpolation functions IPF1 and IPF2 are respectively switched in the opposite direction from the previous time.

In the other interpolation interval "3 * t4, the segment waveform of one series is switched as well as the interpolation function PFI as described above.
, the slope of IPF2 is switched in the opposite direction. Figure 1(b)
The numbers of segment waveforms 8EG1 to 5EG5 used in each series in each interpolation interval t, to t4 are also written in i.

FIG. 2 shows an embodiment of an electronic musical instrument to which the musical tone signal generating device according to the present invention is applied.

In this electronic musical instrument, musical tone signals are generated according to the musical tone signal generation principle as described above with reference to FIG.

In FIG. 2, a keyboard 10 is provided with a number of solutions for specifying the pitches of musical tones to be generated. key assigner 11
detects the press or release of 6 keys.

A process of assigning a pressed key to one of a plurality of musical tone generation channels is performed. - For example, the maximum number of sounds that can be produced simultaneously is 12, and the key assigner 11 assigns the pressed key to any of the 12 channels. A key code KC that specifies the key assigned to each channel, a key-on signal KON that indicates whether or not suppression of that key continues, and a key-on pulse KONF that is instantaneously generated when suppression of that key starts The signal is output from the key assigner 11 in a time-division manner for each channel according to the time-division timing.

An example of time-division channel timing is shown in FIG. 3. Each channel timing 1 to 12 is formed in synchronization with the clock pulse φ.

A clock pulse φ with twice the frequency of the clock pulse φ,
1, the time slot of each channel timing is divided into two to form two subchannel timings 1 and 2. These subchannel timings 1 and 2 correspond to the first and second sequences in the interpolation described above. That is, in this embodiment, the time slot of one channel is divided into two, and the segment waveforms of the first series (subchannel 1) and second series (subchannel 2) for interpolation are read out in a time-division manner. CH2-CH
22 is a channel timing signal, which is generated corresponding to each channel timing 1-12. Each clock pulse φ8. φ, and signals CH1 to CI(12) are generated from the timing signal generator 12 and supplied to predetermined circuits in the electronic musical instrument shown in FIG. 2, respectively.

The phase generator 13 specifies a musical sound waveform to be read out from the waveform memory 14, and inputs address data MADR indicating the sample point to be read out at a musical sound frequency (corresponding to the musical sound frequency at which this musical sound waveform is to be generated). It is generated time-divisionally in a total of 24 time slots for each sub-channel 1 and 2 of channels 1 to 12.The correspondence with the structure of the present invention is as follows: 1. One cycle is generated from the waveform storage means according to the musical tone frequency to be generated. The phase generator 16 includes a readout means for repeatedly reading out waveform data, and a waveform designation means for temporally switching and designating the musical waveform to be read from the waveform storage means.The phase generator 13 includes a key assigner 11. From key code KC, key on pulse KONF,
A key-on signal KON is provided, and these specify the musical tone frequency to be generated and the timing for starting sound generation.

The waveform memory 14 stores a plurality of sets of the aforementioned attack section full waveform and a plurality of segment waveforms corresponding to each tone color.

Specifically, as is well known, each waveform is divided into a plurality of sample points, and corresponding waveform data (for example, waveform amplitude data of the sample point) is stored for each sample point. An example of the memory map in this waveform memory 14 is shown schematically in FIG. Regarding tone people,
The waveform data of the entire attack part waveform is stored in the address range from address A0 to address A0 to -1.

The first segment waveform 5 in the address range from A2-1
Waveform data for one cycle of EG1 is stored, and thereafter, each segment waveform 5EG2.5EG3 is stored in a predetermined address range.
... are stored in sequence. The same applies to the other tones B, C, and so on. AQ, A1. Man,
"" eBQ +B1, B, "" rCC, C...
・ is the start of each address range Or I
2 addresses, AQ, Bo, C6... are the start addresses of the attack part, person 1 w B1 + C
1... is the start address of the first segment waveform 5EG1, and A2, 32, C2... are the start addresses of the second segment waveform 5EG2. -As an example, one period waveform is sampled at 256 sample points,
Further, the maximum number of cycles of the entire waveform of the attack portion is set to 256 cycles. As shown in the figure, the number of cycles of the entire attack waveform differs depending on the tone. It should be noted that each sample point within one cycle (256 in total) can be expressed by just an 8-bit binary code. Therefore, each sample point within this one cycle is specified by the lowest 8 bits of address data MADR, and each start address A, , A,...
・1. Bt, Bt, . . . , C1, C, .

Returning to FIG. 2, the timbre selection circuit 15 outputs timbre selection information TC and provides it to the phase generator 13 and waveform memory 14:crossfade control circuit 16%-envelope generator 17. The cross-fade control circuit 16 is for generating an interpolation function for weighting musical waveform signals of two series (subchannels) related to the same tone generation channel with opposite characteristics. To show the correspondence with the configuration of the present invention, when switching the musical sound waveform to be read, a part of the interpolation means (% a counting means for generating a time function for setting the time change of weighting in the interpolation means, and a waveform switching in the waveform specifying means according to the output of the counting means. The cross-fade control circuit 16 includes a switching control means for controlling the cross-fade control circuit 16.

An attack end signal ATEND indicating that reading of all waveforms of the attack portion has been completed and an inverted attack signal X lower indicating that reading of the attack portion has not been performed are provided from the phase generator 13 to the cross-fade control circuit 16. When the cross-fade control circuit 16 confirms that reading out the waveform of the attack portion based on one of these signals is completed, it starts generating a predetermined interpolation function. The interpolation function is output from the circuit 16 as cross-fade curve data CF, and is applied to a multiplier 18 for weighting calculation. Further, a waveform switching instruction signal WCHG is output from the circuit 16 and applied to the phase generator 16.

A multiplier 18 for weighting calculation and a delay circuit 1 for its output.
An adder 20 that adds a signal delayed by one cycle of the clock pulse φ and a signal that is not delayed at 9 constitutes a part of the interpolation means. Musical waveform data is read out from the waveform memory 14 in a time-division manner corresponding to each sub-channel timing for each +yannel, and similarly from the cross-fade control circuit 16 in synchronization with each sub-channel timing for each channel. Cross-fade curve data CF is read out in a time-division manner. Therefore, in the multiplier 18, the musical waveforms read out in a time-division manner corresponding to each sub-channel of each channel are weighted according to the corresponding cross-fade curve data CF (i.e., interpolation function). . Weighted musical waveform data of two subchannels related to one sound collection generation channel are added by an adder 20. That is, the musical waveform signal of the first sub-channel is delayed and transferred from the delay circuit 19 to the adder 20.
, the tone waveform data of the second subchannel of the same channel is added to the other input of the adder 20. In this way, in the latter half of the time slot of one channel (the time slot corresponding to one period of the clock pulse φ!), the two weighted tone waveform data for that channel are mixed.

The envelope generator 17 generates an amplitude envelope waveform signal for each channel in a time-division manner according to the key-on signal KON and key-on pulse KONP given from the key assigner 11. This envelope waveform maintains a constant level while the key is pressed, and exhibits a decay envelope characteristic in response to the key release. Since the entire waveform of the attack portion stored in the waveform memory 14 has been given the attack envelope characteristic in advance, it is not necessary to give the attack envelope characteristic by the envelope generator 17. The outputs of the adder 20 and the envelope generator 17 are input to a multiplier 21, and step width envelopes corresponding to key presses and key releases are applied to the musical sound waveform data of each channel in a time-sharing manner.

The output of the multiplier 21 is applied to data inputs of latch circuits 22-1 to 22-12 provided in parallel corresponding to each channel. For latch control of each of the latch circuits n-1 to 22-12, an AND circuit 23-1 performs AND logic between the corresponding channel timing signals CH1 to CH12 and an inverted signal φ of the clock pulse φ.
Outputs 23-12 are given respectively. thus.

In the second half time slot 7) of the time-division time slot of each channel, the output of the multiplier 21 corresponds to the latch circuit 22-
1 to 22-12.

As mentioned above, in the adder 20, each channel timing 1
The weighted 2 for that channel in the second half of ~12 time slots (timing of subchannel 2)
Since the two tone waveform data are added, the data corresponding to the addition result is sent to each latch circuit 22-1 to 22-12.
latched to.

In this way, the time division of the musical waveform data of each channel is canceled.

The outputs of the latch circuits 22-1 to 22-12 are input to the latch circuits 24-1 to 24-12.

Pitch synchronization pulses PSF1 to P8P12 output from the phase generator 13 are applied to the latch control inputs of each of the latch circuits 24-1 to 24-12.

The pitch synchronization pulses PSP1 to PSPj2 are pulses synchronized with the frequency i of musical tones assigned to each channel, and by latching the musical waveform data in accordance with these pulses, nonharmonic or locking components are removed. The output of each latch circuit 24-1 to 24-12 is sent to an adder 25.
After being summed, the signal is converted into an analog signal by a digital/analog converter 26 and sent to a sound system 27.

Next, details of the second figure section will be explained.

FIG. 5 shows an example of the phase generator 16, with reference numeral 28.
The part indicated by corresponds to a reading means for repeatedly reading one cycle of waveform data.

The key code KC of each channel given from the key assigner 11 in a time-sharing manner is transmitted to the latch circuits 29-1 to 29-1.
2, and channel timing signals CH1 to CH
A latch circuit 29- corresponding to each channel according to No. 12.
1 to 29-12, respectively. Variable starters 60-1 to 30-1 provided independently for each channel
2 are latch circuits 29-1 to 29-1 corresponding to each
Note clock pulses N (1 to NCI2) corresponding to the musical tone frequency of the pressed key assigned to each channel according to the key code KC given from 2 are generated.The note clock pulses NCI to NC12 are sent to the time division control circuit 61. are applied, time-divisionally sampled and multiplexed according to channel timing signals CHI-CH12, and time-division multiplexed outputs are taken out via line 32.

An example of the time division control circuit 61 is shown in FIG.
Set the RS flip-flops 33-1 to 33-12 to the note clock pulse NC of each channel.
1 to NC12 are respectively input. The AND circuits 64-1 to 34-12 have flip-flops 33-1 to 33-
12 output Q and channel timing signals CHI~CH
12 are input, respectively, and their outputs are multiplexed by an OR circuit 650, guided to a line 62, and returned to the reset holes of the corresponding flip-flops 66-1 to 33-12. In addition, the flip-flops 36-1 to 33-
12 output Q is pitch synchronization pulse PSF1~PSP12
As mentioned above, the latch circuit 24- in FIG.
1 to 24-12. flip flop 66
-1 to 33-12 are set at the rising edge of the signal from the set human power S, and reset at the falling edge of the signal from the reset input hole. FIG. 7 shows an example of the input/output signals of the part shown in FIG. As is clear from the figure, the note clock pulse NC of the key assigned to each channel
1 to NC12 are asynchronous to the channel timing,
At the rising edge of these pulses NC1 to NC12, flip-flops 33-1 to 33-12 are set to enable the corresponding AND circuits 34-1 to 34-12, and then corresponding to the first channel timing signals CH1 to CH12 are set. The AND circuits 34-1 to 34-12Th output pulses, and at the fall of this output pulse, the flip-flop 3
6-1 to 33-12 are reset. Then, a new note clock pulse synchronized with the channel timing signals CH1 to CH12 at the same frequency as the note clock pulses NC1 to NC12 is applied to each AND circuit 64-1 to 3.
4-12. In this way, a note clock pulse corresponding to the musical tone frequency of the key assigned to each channel (an integral multiple thereof) is outputted to the line 32 in accordance with the time division timing of the corresponding channel.

Returning to FIG. 5, each channel's note clock pulse applied to line 32 is output to adder 35. Gate 36. A counter 38ζ consisting of a shift register 37 receives the pulses, and counts the number of pulses for each channel in a time-division manner. The shift register 37 has 24 stages/8 bits, and is shift-controlled by a clock pulse φ11 synchronized with the subchannel timing. shift register 37
The output of is provided to adder 65 and summed with the note clock pulse on line 62. The addition output is gate 36
The data is stored in the shift register 67 via. The 24 stages of shift register 67 have two stages in each of the 12 channels.
It supports subchannels, and the count value for one channel is stored in two stages (corresponding to two subchannels).

The gate 66 is instantaneously closed by the key-on pulse KONF just before the start of the tone sound, and the memory of two corresponding stages in the shift register 37 is cleared.

Since the shift register 37 has a capacity of 8 bits per stage, the counter 38 counts modulo 256 for 24 channels (actually 12 channels) in a time-division manner. The output of gate 36 is taken out as the count output of counter 68, and is applied to waveform memory 14 as the lowest 8 bits of address data MADR. By the count output of the counter 68, each sample point of a one-period waveform consisting of 256 sample points can be sequentially read out. Count is note clock pulse NC1~N
Since the reading is performed according to C12, the reading is performed in accordance with the musical tone frequency to be generated.

Address data MAD for reading waveform memory 14
R is N+8 bits (N>8).

As described above, the lowest 8 bits specify the sampling point within one cycle of the waveform, and the upper N bits specify the waveform for one cycle.

The upper N-bit address data for waveform designation is given via an adder 41 from a start address generation circuit 40 corresponding to waveform designation means. The start address generation circuit 40 generates the start addresses A, B, of all waveforms of the attack portion described above.

C0... and the start address of each segment waveform,
, At... is generated. An attack section period number counter 39 is provided to specify each one-cycle waveform within the entire attack section waveform.

An adder 41 is used to add and synthesize the output of the counter 69 and the start addresses A, B, C, . is provided.

The hardware configuration of the artack section period number counter 39 is similar to that of the counter 38 described above, including an adder 43, a gate 44.
It includes a shift register 45.

This counter 69 counts the carry signal CRY from the most significant bit of the adder 65 in a time-division manner for each channel. This carryout signal CRY is a channel consisting of a counter 38 which carries 25 note clock pulses.
Every 6 counts (that is, every time one period of the waveform is read out)
By counting this, the number of cycles of the attack section can be counted.

The output of the counter 39 is applied to a gate 42, and the gate 42 is opened only during reading of the entire waveform of the attack section by an attack signal AT, which will be described later, and the counter output is applied to the adder 41. The lowest 8 bits of the N-bit start address data generated by the start address generation circuit 40 are input to the other input of the adder 41. Of the N-bit start address data, the 8-bit output data of the adder 41 is located below the most significant N-8 bit data that was not input to the adder 41, and the most significant N of the address data MADR is Bits are configured. The count value of the counter 69 indicates the number of cycles counted from the first cycle of the entire waveform of the attack section, while the start address A (1°B, , C, . . .
The first pair address of the entire waveform of the attack part is shown in FIG.

Therefore, by adding the two, it is possible to specify the first absolute address for each period of the attack section full waveform (that is, specify each one-period waveform).

The attack end detection circuit 46 counts the carry signal CRY applied from the counter 68 to check whether reading of all waveforms of the attack portion has been completed, an example of which is shown in FIG.

In FIG. 8, the attack part cycle number memory 47 stores the number of cycles of the entire attack part waveform for each timbre, and the cycle number data TN is read out in accordance with the timbre selection information TC. A counter 52 consisting of a subtracter 48, a gate 49° selector 50, and a 24-stage/8-bit shift register 51 counts down the number of cycles each time one cycle of the attack waveform is read. The down count is performed in time division. The selector 50 selects the cycle number data ATN read from the memory 47 when the key-on pulse KONF is generated via the B input,
The data is taken into the shift register 51. At other times, data to be applied to the A input of the selector 50 is selected from the final stage of the shift register 51 via the subtracter 48 and is applied to the shift register 51. The carry signal CRY output from the adder 35 in FIG. The gate 49 is enabled during the attack by the attack signal T, and the carry signal CRY is enabled by the subtractor 4.
Give to 8. In the subtracter 48, the carry signal CR
When Y is given, 1 is subtracted from the output data of the shift register 51. thus.

Initially, data indicating the number of cycles of the entire attack section waveform is entered in the shift register 51, and thereafter, this data is subtracted by 1 each time one cycle of the attack section waveform is read, and finally, when the reading of the entire attack section waveform is completed. The data is all ″″
It becomes Om.

The output of the counter 52 is taken out from the selector 50 and applied to the all 10m detection circuit 520.

The all 10m detection circuit 520 detects whether the count output data given from the selector 50 is all "O'", and outputs the signal °1m when all is "0".The output signal of this detection circuit 520 is inverted. It is output as an attack signal T, and a signal inverted by the inverter 56 is output as an attack signal T. Therefore, during an attack, the attack signal AT is "1" and the inverted attack signal AT is "1".
02, but when the attack ends, it is reversed and AT becomes 10" and AT becomes 11". The delay circuit 54 generates a clock pulse φ8×12 with a period 12 times that of the clock pulse φ.
This sets a signal wander for one cycle of time-division channel timing, and delays the attack signal AT and supplies it to the AND circuit 55.

An inverted attack signal AT is given to the other input of the AND circuit 55, and when the signal AT switches from "0" to "1", one time slot (
AND circuit 5 between subchannel 2 timesloft minutes)
The output of 5 becomes l'', which is the attack end signal AT
Output as END. Furthermore, when the attack is completed, the gate 49 is closed by "0" of the attack signal AT, and no further down-counting is performed.Therefore, the count value of the counter 52 is all "0" except at the time of attack.
maintain. The operation example of FIG. 8 for one channel is shown in FIG. U (a).

Returning to FIG. 5, the start address generation circuit 40 selects a set of start addresses in response to the tone selection information TC, generates a start address for the attack section in response to the key-on pulse KONF, and outputs the start address to the waveform switching command signal WCHG. The start address of each segment waveform is sequentially switched accordingly. An example of this start address generation circuit 40 is shown in FIG.

9, the start address memory 56 stores a plurality of sets of start addresses A, A1, . A,---BB.

1 0 @! B2..., C,, C,, C2... are stored in advance, respectively, and a set of stars 1-
Address (for example, A for a tone., A1, A2...
・) is selected. The end address memory 200 stores end addresses (final phase addresses) of each segment waveform corresponding to each tone color A, B, C, etc., and stores a set of end addresses according to the tone color selection information TC. address(
For example, in the case of timbre A, the corresponding end address of each segment waveform is selected.

24 stage shift register 57, selector 58.5
9.60, the loop including the adder 61 and the gate 62 constitutes a counter, and the count value taken out from the gate 62 in this loop is stored in the star 1-address memory 56.
and the input of the end address memory 200.

The start address memory 56 sequentially reads out a selected set of start address data (for example, A., A1.A2, . . .) according to the count value applied to the address input. That is, when the count value given from the gate 62 is "0", the start address 80 of the attack part is read out, and when it is "1", the first segment waveform 5EG is read out.
Read the start address 80 of I, and if it is "2", read the start address A2 of the second segment waveform 5EG2.
Read out. In this way, the start address data read from the start address memory 56 specifies the waveform to be read from the waveform memory 14 (FIG. 2).

On the other hand, the end address memory 200 contains tone selection information TC.
A set of end address data selected by is sequentially read out according to the count value given to the address input. That is, end address data EADR regarding the segment waveform specified by the start address data read from the start address memory 56 is read from the end address memory 200.

The read end address data EADR is input to the comparator 201 in FIG. Address data MADR generated from phase generator 13 in FIG. 5 is applied to the other input of comparator 201.

Comparator 201 checks whether address data MADR indicating the phase currently being read matches end address data EADR indicating the final phase of the segment waveform.

Returning to FIG. 9, the gate 62 is enabled by the inverted signal KONP of the key-on pulse KONP, and the gate 62 closes in the channel where the key-on pulse KONP is generated, and the stored contents of the shift register 57 corresponding to that channel are cleared. be done. The output of the final stage of the shift register 57 is applied to the C input of the selector 58, and is also applied to the input and B inputs of the selector 58 via delay circuits 63 and 64, respectively. The delay circuit 63 is delay-controlled by a clock pulse φl×23 having a period corresponding to 23 cycles of the clock pulse φmin, and the delay circuit 64 is delay-controlled by a clock pulse φ1. selector 58
The output of the AND circuit 65 which takes the AND logic of the clock pulse φ2 and the waveform switching command signal WCI (G) is given to the A selection manual SA.The B selection input SO is supplied with the inverted signal of the clock pulse φ2 and the signal WCHG. The output of an AND circuit 66 that performs AND logic is applied.A signal obtained by inverting the signal WCHG by an inverter 67 is applied to the C selection input SC.

The output of selector 58 is given to the input of selector 59. The B input of the selector 59 has the numerical value ``1''.

The numerical value "2" is given to each C input. selector 59
A signal obtained by inverting the attack end signal ATEND by an inverter 68 is applied to the input signal SA.

B selection input 8B receives clock pulse φ and signal ATEN.
The output of an AND circuit 69 that performs an AND logic on D is given, and an AND circuit 70 that performs an AND logic on an inverted signal of the clock pulse φ and a signal ATEND is applied to the C selection manual SC.
The output of is given. .

The output of selector 59 is given to adder 61.

The other input of the adder 61 is a waveform switching command signal WCHG.
is given, and 1 is added to the output data of the selector 59 every time the command signal WCHG becomes 1". The output of the adder 61 is given to the B input of the selector 60. The A input of the selector 60 is given the output of the sequence return destination memory 71.The output of the adder 61 is also given to the final segment detection circuit 61A, and the output signal of this detection circuit 61A is given to the selection power 8A of the selector 60. , the output signal of which is inverted by an inverter 72 is applied to the B selection input SB.

The output of selector 60 is applied to shift register 57 via gate 62.

Since the shift register 57 has 24 stages and the operating clock pulse is φ, the counting operation is performed in a time-division manner in a total of 24 time slots for each subchannel of each channel 1 to 12.

The counting operation will be explained below regarding one channel JL/J. First, as mentioned above, the key-on pulse KON
When P occurs, the gate 62 is closed and the contents of the two stages of the shift register 57 corresponding to the channel are cleared to all @O''. As will be described later, the waveform switching command signal WCHG is not generated during the attack. Therefore, the selector 58 always selects the C input. Also, during the attack, the attack end signal ATEND is 01,
Selector 59 selects the A input. Furthermore, the output signal of the final segment detection circuit 61A is ``0'' until the readout of the segment waveform of the most i/[-order is completed, and the selector 60 selects the B input. Therefore, the contents of the cleared shift register 57 are input to the C input of the selector 58, 5
9, the adder 61, the B input of the selector 60, and the gate 62, the signals circulate in synchronization with the same channel timing with a delay of one channel timing cycle.

Therefore, the count value given from the gate 62 to the start address memory 56I remains "0", and data indicating the start address of the attack section (for example, □) is read out in response to the count value.

When the attack is finished, as mentioned above, the attack end signal man TEND is sent from the attack end/production circuit 46 in FIG.
occurs only once at the channel timing (time slot for two subchannels). This enables the AND circuit 69.70, and the first half time slot (
That is, clock pulse φ! At the timing of sub-channel 1 when the value becomes ``11'', the selector 59 selects B person S, and numerical data ``1'' is stored in the shift register 57. Furthermore, the C input of the selector 59 is selected in the latter time slot (that is, the timing of subchannel 2 when clock pulse φ2 becomes 0"), and the
2'' is stored in the shift register 57.

In this way, when the attack ends, a numerical value "1" is initially set corresponding to subchannel 1, and a numerical value "2" is set corresponding to subchannel 2. As a result, data indicating the start address (for example, A8) of the first segment waveform 5EG1 corresponding to subchannel 1 is read out from the start address memory 56. Data indicating the start address (for example, At) is read. This state is maintained until the next waveform switching command signal 'vV CHG is applied. An example of changes in the count value for one channel (two subchannels) output from the gate 62 is shown in FIG. 11(b).

The waveform switching command signal W CHG is generated by being alternately switched in response to one of two subchannels related to one channel, as will be described later. As shown in FIG. 11(b), initially the subchannel I
The signal is generated in correspondence with subchannel I, then generated in correspondence with subchannel 2, and thereafter alternately generated. Horsefly, No. 9
In the circuit shown, the counting operation in response to the waveform switching command signal WCHG is performed on one of the two subchannels.

Assuming that the switching command signal WCHG is generated corresponding to the first half channel time slot, that is, subchannel 1,
AND circuit 65 corresponding to 11" of clock pulse φ2
is enabled, but AND circuit 66 is not enabled.

So in that case.

The output of the delay circuit 66 is selected via the selector 58, and the digital calculator 61 outputs the signal W for this data.
1 is added by CHG. The delay 1 circuit 66 outputs data 23 time slots ago at subchannel timing, which is the count data of subchannel 2 of the previous cycle regarding the same channel ζ.

The value added by 1 to the count value of subchannel 2 becomes the new count value of subchannel 1. In this case, subchannel 2 is greater than the count value of subchannel 1 by 1, and therefore, the count value of subchannel 1 is essentially the same as being added by 2. If you line up,
As mentioned above, when the count value of subchannel 1 is "1" and the count value of subchannel 2 is "2", when the first waveform switching command signal WCHG is given corresponding to subchannel 1, the subchannel At timing 1, 1 is added to the count value "2" of subchannel 2 in the previous cycle (that is, the output of the delay circuit 66), and the count value of subchannel 1 changes to "3".

In this case, at the timing of subchannel 2, selector 5
The output of the shift register 57 is selected as is through the C input of 8, and the count value is not increased. Therefore,
The count value of subchannel 2 remains "2".

In this way, the first waveform switching command signal WCHGI changes the read address of subchannel 1, and the third
Data indicating the start address (for example, A3) of the segment fi$5gG3 is read from the memory 56.

On the other hand, the start address of the sub-cell channel 2 does not change, and the start address data of the second segment waveform 5EG2 is still read out.

When the waveform switching command signal SV CHG is generated corresponding to subchannel 2, contrary to the above, the AND circuit 66
is enabled, the output of the delay circuit 64 is set to B of the selector 58.
The data is selected via the input, and 1 is added to this data by the adder 61 in response to the signal WCHG. The delay circuit 64 outputs the count f of the subchannel one time slot before, that is, the subchannel 1 of the same channel.
Adding 1 to this count value becomes the new count value for subchannel 2. In this case, subchannel 1
The count value of subchannel 2 is 1 more than the count value of subchannel 2.
Therefore, the count value of subchannel 2 is essentially the same as 1+2 added. For example, as mentioned above, when the count value of subchannel 1 is "3" and the count value of subchannel 2 is "2", the signal WCH
When C) occurs corresponding to subchannel 2, the count value of subchannel 2 changes to "4" while the count value of subchannel 1 remains unchanged at "3".

As described above, each time the waveform switching command signal WCHG is generated alternately corresponding to one of subchannels 1 and 2, the count value of the corresponding subchannel increases by 2, and correspondingly, each subchannel The order of segment waveforms specified by is "1" and "2", "3" and r2J, r3J
and “4”.

Segment waveforms are captured for every second subchannel (1.2) alternately, such as "5" and "4".

When a predetermined number of waveform switching command signals WCHG are applied and the output of the adder 61 reaches a value specifying the final segment waveform, the output signal of the final segment detection circuit 61 becomes 1.
It becomes 1'. Note that this detection circuit 61A stores, for each tone color, a numerical value that designates the last segment waveform among the plurality of segment waveforms stored for each tone color in the waveform memory 14, and uses the tone color selection information TC.
Compares the numerical value 1 direct data read from this memory with the output data of the adder 61, and outputs a ``1'' signal when ``output data value > numerical data value''. It consists of a comparator and a comparator.

When the output signal of the detection circuit 61A becomes '1'', the selector 60 switches to adult power selection.As a result, the return destination and rank data read from the sequence return destination memory 71 are selected by the selector 60, and the shift Stored in register 57.

Sequence return destination memory 71 (This is where the return destination order data that instructs which segment waveform should be returned to and read after reading the last order segment waveform is stored for subchannels 1 and 2 for each tone. are stored, and tone color selection information TC and clock pulse φ,
Predetermined return destination order data is read in accordance with the above. If the pronunciation continues even after the segment waveform of the final rank has been extracted, the purpose is to return to the segment waveform of the 1@ position corresponding to the return destination rank data and wait for and celebrate the start of the play. In this case, the sequence return destination memory 71 is used. In this case, the return destination order data stored in the sequence return destination memory 71 is the sequence waveform 8EG1 stored in the waveform memory 14.

For tones whose copy number is a low number of 5EG2..., the numerical value i indicating the order of the segment waveform 5FSGi that is actually returned and read out corresponds to the subchannel 1i, and the numerical value i indicating the order of the segment waveform 5FSGi corresponding to the subchannel 2 corresponds to the segment waveform 5Eoi. A numerical value i+1 indicating i@stand of the next segment waveform S B C) i -)-1 is stored, respectively.

On the other hand, for tones with odd numbers in the sequence waveform, contrary to the above 4J case, the number i corresponds to subchannel 2, and the number i corresponds to subchannel 1! 1ifi
+ 1 is given respectively.

For example, if timbre A is selected and the number of segments of the segment waveform related to this timbre person is "6", and the order of the segment waveform to return to is "3", the count 1 of subchannel 1 is "0". → “1” → “3” → “5” → “3” →
The count value of subchannel 2 changes as "5" → "3" → "5", etc., while the count value of subchannel 2 changes as "0" → "2" → "4" → "
6” → “2” → “6” → “2” → “6” and so on. From this 1, for subchannel 1, segment waveform 5EG1.5BG3.5EG5 is primarily specified, and then segment virtual form 5BG3°5EG5. '1il
A return is specified, while for subchannel 2, segment waveforms 5EG2, 5gG4, 5EG6 are jli1
The next specified segment waveform 8gG4, 5EG6 is 4
It will be specified in return.

Next, referring to FIG. 10, crossfade 11 [open circuit 1
61 Let me explain.

The counting means 76 has four
The first counter 7 is used to generate the number A.
3A and a $2 counter 73B. Both counters 76 and 76B are adders 74A and 74B, and gate 7.
The outputs of the shift registers 76A, 76B are circulated through the adders 74A, 74B and the gates 75A, 75B, respectively. It is possible to perform counting on a time-sharing basis for each channel. The first counter 73A is for counting the number of times segment waveforms are switched. The change rate memory 77 stores change rate data corresponding to the number of times of switching in advance for each timbre, and one set of change rate data is selected according to the timbre selection information TC.
One change rate data D is generated from the selected data according to the number of switchings counted by the first counter 73A.
TkaS is read out. Note that the output of the gate 75λ is the first
This is taken out as the count output of the counter 73 and inputted to the memory 77. The counter 75 and the change rate memory 77 correspond to counting rate control means.

The second counter 75B changes the count from the first predetermined value (for example, 0) to the second predetermined value (for example, the maximum value) read from the memory 77, and the second counter 73B This data DT is accumulated at predetermined time intervals. Gate 75B receives inverted attack signal AT
This is enabled except when attacking. Therefore, the count content of the counter 73B during the attack is "O".
The data DT is cleared when the attack ends.
Start counting.

The count output of the second counter 73B is taken out from the gate 75B, and a function conversion circuit 78 consisting of an exclusive OR circuit
is input. This function conversion circuit 78 separately inputs the lower n-1 bits of the n-bit count output to exclusive OR circuits, and inputs the most significant bit MSB in common to each exclusive OR circuit, so that the MSB is "0". It passes through the first n-1 bits as they are, but when it is °1'', the lower n-1 bits are inverted and output.In this way, the count value increasing from the minimum value O to the maximum value 2n is 2n-1. turns around and increases from 0 to 2n-1, then from 2n-1 to 0
Convert to a triangular wave-like function that decreases to .

The output of the ry5 number conversion circuit 78 is used as the basic interpolation function IPF2 for the second series (subchannel 2).

The inversion circuit 79 inverts each bit of this interpolation interval aIPF2 to form a function with inverse characteristics, and this function with inverse characteristics is used as the basic interpolation function IPFI for the first series (subchannel 1).

These interpolation functions IPF1. An example of IPF2 is shown in FIG. 11(C). During the attack, the output of the second counter 73B is all bits "0", so the output of the function conversion circuit 78 is all bits "0", and the value of the second series interpolation function IPF2 is the minimum value (0). is maintained, and the value of the first series interpolation function IPF1 is maintained at its maximum value.

The selector 8Q is for time-division multiplexing of the interpolation functions IPFM and lFF2 in accordance with the timing of each subchannel 1.2, and lFF2 is added to the A input, IPFl is added to the B input, and the clock pulse φ , is “1”
” (subchannel 1 time slot and IB
When large input IPFl is selected and φ is @0'' (time slot of subchannel 2), A input lFF2
Select.

The switching control means 81 responds to the output ζ of the counting means 73 by controlling the waveform specifying means, that is, the start address generation circuit 4 of FIG.
It controls the waveform switching operation at 0, and the interpolation functions IPF1 and lFF2 output from the selector 80
All” to detect whether the value of is all bits @0”
It includes a "0" detection circuit 82 and an AND circuit 86 into which the output of this detection circuit 82 and an inverted attack signal AT are input. The AND circuit 86 is enabled by the signal AT at times other than 7, and outputs the output signal "°1" of the all "0" detection circuit 82 as the waveform switching preparation signal WCHG. Interpolation of two subchannels/1 number lFF1, lF
When one of F2, which gradually decreases over time with a negative slope, becomes all bits "0", the output of the all @0 detection circuit 82 becomes "1" at the timing corresponding to that subchannel, corresponding to this. and waveform switching 7<1! Preparation signal WC
HG'' is generated.The interpolation function IP of both subchannels
The slopes of FI and lFF2 change every interpolation interval, so
The waveform switching preparation signal WCHG' is generated by switching alternately corresponding to one subchannel every time one interpolation is completed (see FIG. 11(b)). Note that when the waveform is switched, the gate 202 is closed and the counting operation of the counter 73B is stopped, and the interpolation function IPF1. IPF2 all #
Since the O# state is maintained, the waveform switching preparation signal WCH is output only in the first cycle when all "Ou"
In order to output G', the all "0" detection circuit 82 outputs an all "0'" detection signal which is differentiated at the rising edge according to the clock pulse φ.

The waveform switching preparation signal WCHG' is input to the shift register 205 via the OR circuit 203 and the AND circuit 204. A signal obtained by inverting the output signal EQ of the comparator 201 by an inverter 206 is applied to the other input of the AND circuit 204. As mentioned above.

Field 1! Inner υ1 Ritsu 11-1 Sunda lr Detachi Tetsugyoshi East 1.7#
The sum/thousands7 trace data MADR and end address data EADR are input, and when they match, that is, when the current read phase becomes the final phase, the output signal EQ becomes 1''.Current read If the phase is not at the final phase, the signal EQ is II O++,
The AND circuit 204 is enabled and the waveform switching preparation signal W
The signal 111 ++ of CHG' passes through the circuit 1 to 204 and is input to the shift register 205, and is input to the OR circuit 20.
3 and the shift 1 to register 2 via the AND circuit 204
It is held in circulation at 05. The shift register 205 has 24 stages and is shift-controlled by a clock pulse φ, and its output is given to the OR circuit 203. When the signal EQ becomes "1", the AND circuit 204 is disabled, and the signal 0 based on the signal W CHG
1 ++ memory is cleared. On the other hand, AND circuit 20
7 is input with the signal EQ and the output of the OR circuit 203, and when the output signal EQ of the comparator 201 becomes II I ++, the condition of the AND circuit 207 is satisfied at the timing of the subchannel where the signal WCHG' is generated. do. The output signal rr 1 ++ of this AND circuit 207 is output as the waveform switching command signal WCHG. In this way, even if it is detected that the waveform should be switched based on the count contents of the counting means 73 (even if the waveform switching preparation signal WCHG' is generated), the waveform switching command signal WCHG is not immediately generated, and the current segment It waits until the waveform readout phase matches the final phase of the segment waveform, and when a match is detected, a waveform switching command signal WCHG is generated.

Interpolation function I I outputted from selector 80 in a time-division manner
) F1 and IPF2 exhibit temporally linear characteristics, but the cross-fade curve memory 84, which corresponds to supplementary function storage means, is provided to convert these interpolation functions into arbitrary characteristics.

For example, various interpolation characteristic curves (weighting curves) as shown by solid lines in FIG. The selector 80 selects the interpolation characteristic curve according to the information TC (or selection operation using a dedicated switch, etc.).
The interpolation functions IPFI and IPF2 are read out as addresses. As mentioned above, the interpolation functions IPF1 and IPF2 (so to speak, these are the basic interpolation functions) of both subchannels have opposite characteristics. (when one direction is in the opposite direction, the other is in the opposite direction), and curves with mutually opposite characteristics are read out from the memory 84 in a time-division manner. For example, if one subchannel corresponds to
When the interpolation characteristic curve shown by the solid line in FIGS. 2(a) to 2(d) is read out, the interpolation characteristic curve shown by the broken line in the same figure is read out corresponding to the other subchannel.

The interpolation characteristic curve data corresponding to each sub-channel for each channel read out in a time-sharing manner from the memory 84 as described above is given to the multiplier 18 in FIG. 2 as cross-fade curve data CF, and its characteristics are The corresponding segment waveform data is weighted (amplitude side m) according to. Note that since the functions IPF1, . . . IPF2 are used as address signals for the memory 84, the counting means 73 and the function conversion circuit 78 correspond to address generation means for the memory 84.

By using the memory 84 in this manner, it is possible to set the interpolation characteristic to an arbitrary curve ζ. Also.

Since two series of interpolation characteristics are obtained by reading arbitrary interpolation characteristic curves in opposite directions, it is possible to set an arbitrary interpolation characteristic curve, but as a result (interpolation synthesis of two series) ), symmetrical interpolation is always performed, and smooth interpolation without bias can be performed. By the way, to explain the characteristics shown in Fig. 12, (a) the volume level increases at the midpoint of interpolation (midpoint of musical waveform change), and (b) the waveform changes significantly at the beginning. However, the change is gradual in the middle, and then there is a big change again at the end. In (C), the waveform changes slowly at the beginning and end, and changes greatly in the middle. In (d), the waveform changes while fluctuating.

Returning to FIG. 10, the all 60" and all @1# detection circuit 85 outputs the switching synchronization signal CHGS in synchronization with the waveform switching timing, and inputs the output of the function conversion circuit 78, that is, the interpolation function IPF2, It is detected whether the value is all pids '0'' or all bits 11117. For the same reason as the all 110 I+ detection circuit 82 described above, the all 110 I+ or all '1'' detection signal is differentiated at the rising edge by the clock pulse φ4, and the result is output as the switching synchronization signal CHGS. This signal CHGS is “L 11 ” in the time slot of both subchannels, that is, the time slot of one channel corresponding to one cycle of clock pulse φ2.
becomes.

This signal CHGS is applied to the clock pulse φ by the delay circuit 86.
2x12, the time division channel timing is delayed by one cycle, and the counter 73A is output via the gate 87.
is applied to the adder 74A.

The output of the adder 74A is applied to 76 12-stage shift registers via a gate 75A, delayed by one cycle of the time division channel timing, and returned to the input of the 74 adders. 75A is controlled by a signal i obtained by inverting the attack end signal ATEND, and is instantaneously closed only when the attack end signal ATEND is generated, and the shift register 7 for the corresponding channel is
Clear the memory of 6A. The output of the gate 75A is fed to the change rate memory 77 as described above, and all 1s are output.
1" detection low 88. The all '1m detection circuit 88 outputs a signal @"1 when the count values of the counters 76 reach all bits "1", that is, the maximum value. This output is inverted by an inverter 89 and is applied to the control input of the gate 87.

The count value of the counter 73A maintains the maximum value during the attack, and the gate 87 is closed. When the attack is completed and the count value is cleared by the attack end signal TEND, the output of the all "1# detection circuit 88 becomes 0" and the gate 87 is opened or reduced. Thereafter, each time the switching synchronization signal 0 (field) occurs, the count value of the counter 73A increases, and the number of waveform switching is counted.

When the count value reaches the maximum value (all 111), gate 8
7 closes and the counting operation stops. Note that the delay circuit 8
Reference numeral 6 is provided to delay the timing at which the signal CHG3 is input to the counter 76A by the time difference between the input and output of the shift registers 76. An example of the switching synchronization signal CHGS and the number of switching times counted by the counter 76A is shown in FIG. 11(C).

As mentioned above, the change rate memory 77 stores the counter 73A.
Predetermined change rate data DT is read out corresponding to the count value. Depending on the value of this change rate data DT, the second
The increase rate of the count value of the counter 73B is determined, and the slopes of the interpolation functions IPF1 and IFF2 are determined.
The temporal length of the interpolation interval is tl, t2 in Figure 1 (b). t
3. t4...) is determined. In the memory 77, the change rate data DT can be arbitrarily set according to the number of waveform switching (that is, for each interpolation interval). The first counter 73 can be set completely arbitrarily.
Once A reaches its maximum value, it will be maintained thereafter, so
The change rate memory 77 continuously reads out the change rate data DT corresponding to the maximum value. Of course, like the other counters, the first counter 73A performs the counting operation on a time-division basis for each channel, so the above-mentioned reading of the waveform switching count I~ and the change rate data DT is performed on a time-division basis for each channel. It will be done.

All '0'' and all II I I+ detection circuit 85
The output (g CHG S) is also given to the shift register 210 via the OR circuit 208 and the AND circuit 209.

The shift register 210 has 12 stages and is shift controlled by clock pulse φ2.

The output is given to OR circuit 208. AND circuit 2
The output signal EQ of the comparator 201 inverted by the inverter 211 is applied to the other input of the comparator 09. A signal obtained by inverting the output of the AND circuit 209 by an inverter 212 is used as a control signal for the gate 202.

As mentioned above, when the segment waveform should be switched, the switching synchronization signal CHGS becomes 111 I+, and this signal "1" is stored in the shift register 210 until the coincidence output signal EQ of the comparator 201 becomes 1'1. While the memory is being held, the AND circuit 209 outputs a signal "1" at the corresponding channel timing.
Gate 202 is closed. As a result, the change rate data DT is prohibited, and the counting operation of the counter 73B is temporarily stopped. As a result, the state of all "0" or all "1" of the output signals of the function conversion circuit 78 is maintained. When the current readout phase of the segment waveform becomes the final phase,
The signal EQ becomes 11171, the AND circuit 209 is disabled, the storage of the signal "1" in the shift register 210 is cleared, the gate 202 is opened, and the counting operation of the counter 73B is restarted.

In the example A explained above, the basic interpolation functions IPF1 and IPP2 (address signals of the memory 84) change in a triangular waveform as shown in Figure 1 (b), so that the two segment waveforms are always weighted. However, the present invention is not limited to this, and the weighting of the two waveforms may be performed only during the transition period of waveform switching.

Further, in the above embodiment, two streams (subchannels) for interpolation are time-divisionally processed, but they may be processed in parallel. In addition, in Fig. 2, two series of music waveform signals weighted for interpolation are digitally added in an adder 20 and then D/A converted, but each series is D/A converted independently and then mixed or independent. You may also choose to pronounce it.

Further, although the waveform memory 14 shown in FIG. 2 stores the amplitude value data of each sample point of the waveform as is, it is not limited to this, and various storage methods may be employed. for example,
A method of obtaining amplitude data of each sample point by memorizing the difference value of shooting@m between each sample point and 2, reading these and accumulating them, or a method of obtaining the amplitude data of each sample point by dividing the real number of the amplitude value of each sample point into the mantissa and the exponent. There are various methods, such as storing the data in parts and performing arithmetic processing after reading it out to obtain the real number of each sample point value.

In addition, in the above embodiment, the segment waveform (SEGl, 5E
G2. ...), one cycle of the waveform is stored as it is in the waveform memory 14, but this is not the only option, and only a half cycle of the waveform may be stored, and in this case, the read half cycle waveform Positive and negative polarities may be added alternately to the waveform to form one period waveform. Further, the segment waveform stored in the waveform memory 14 is not limited to one period waveform, but may be a waveform for a plurality of periods (for example, two periods).

In the above embodiment, the attack portion of the musical tone signal is generated by storing a continuous multi-cycle waveform as it is in the waveform memo IJ14 and reading it out as it is, but instead of this.

Regarding the attack section, according to the present invention, a plurality of segment waveforms may be stored in the waveform memory 14 and read out by switching from time to time, and the above-mentioned interpolation processing may be performed when changing the waveform to generate a musical tone signal. Of course it's a good thing.

In the above embodiment, the musical tone signal generating device according to the present invention is used in a multitone electronic musical instrument.

Of course, it can also be used for single-note electronic musical instruments.
Furthermore, it is applicable not only to electronic musical instruments but also to all devices that generate musical sounds.

In the example of FIG. 10, the final interpolation function, that is, the cross-fade curve data CF is obtained from the memory
However, without providing the memory 84, lPE1,
lPP2 is directly supplied to the multiplier 18 (FIG. 2) as a weighting coefficient, or.

It is also possible to provide the multiplier 18 with modified lPP1 and lPP2 by appropriate logical operations.

In addition, in the above embodiment, each segment waveform 5BGI
, 5BG2, . . . are stored in the waveform memory 14.
are prepared in advance, and by reading these, each segment waveform (and by extension, the waveform of the attack portion) is generated. However, the present invention is not limited to this, and the valley segment waveform is created using a musical sound waveform forming means that forms a desired musical sound waveform based on parameters (harmonic relative amplitude coefficients and filter coefficients) such as a harmonic synthesis method or a digital filter method. may be generated. An embodiment of the present invention using such a parametric tone waveform forming means will be described below with reference to FIG.

In FIG. 8, circuits or devices having the same functions are denoted by the same reference numerals as those shown in FIG. 2, and a description thereof will be omitted.

The one-cycle phase data generation circuit 100 generates phase data λ that sequentially specifies each phase (each sample point) within one cycle of the musical sound waveform.
This is for generating DR, and the same configuration as the reading means 28 in FIG. 5 can be used.

The tone waveform forming circuit 101 forms a tone waveform having a shape determined by the parameters by a predetermined calculation using the parameters, and also generates a tone waveform having a shape determined by the parameters.
This musical sound waveform is formed in accordance with the phase (sample point) specified by the phase data ADR given from .

As this tone waveform forming circuit 101, for example, one that forms a desired tone waveform by harmonic synthesis calculation can be used. Musical waveform forming circuits using such a harmonic synthesis calculation method are disclosed in Japanese Patent Publication No. 52-16363 (a type that generates each harmonic signal in parallel) and Japanese Patent Application Laid-Open No. 48-90.
Since this system is already well known in Publication No. 217 (a type in which each harmonic signal is generated in a time-division manner), the details will be omitted, but the outline is as shown in FIG. 15. In the case of the harmonic synthesis calculation method, the parameters used for calculation consist of relative amplitude coefficients of each harmonic including the fundamental wave. The harmonic generation circuit 107 in FIG. 15 generates each harmonic signal (including the fundamental wave) according to the phase data input, and the multiplier 108 converts the relative amplitude of each harmonic signal into the corresponding relative amplitude coefficient. (parameters), and the addition and synthesis circuit 109 adds and synthesizes them to obtain a tone waveform with desired characteristics.

The parameter memory 102 stores a plurality of different musical sound waveforms, ie, segment waveforms, sampled discretely from the start to the end of musical tones.

Parameters that determine the characteristics (particularly the shape) of each segment waveform are stored. In this embodiment, it is assumed that the segment waveform is sampled discretely as appropriate even in the attack portion, without distinguishing between the attack portion and other portions. As described above, each segment waveform is distinguished by adding numbers 1, 2, 3, . . . to the code SBG to indicate the order of generation. In the parameter memory 102, the ``th plan''≠Yo≠→Koraku segment waveform 5BG1.5E
G2,... rank 1, 2. Parameters corresponding to 'i `` 1 @ `` 2 '''', bl, b2-
--1c1゜C2... are stored for each tone color person, B, C..., and a parameter group corresponding to a predetermined tone is selected by the tone selection information TC, and among the selected parameter groups. Parameters corresponding to the segment rank data generated from the segment rank data generation circuit 106 are read out and output to the musical waveform forming circuit 1011. Note that symbols an, a2-. bl, b2-. cl.

The individual parameters indicated by C2... correspond to one set of parameters consisting of a plurality of parameters necessary to form a desired segment waveform. For example, C2 corresponds to a set of parameters necessary to form the second segment waveform 5EG2 regarding timbre A, and for example,
It consists of a set of relative amplitude counts corresponding to each harmonic.

The segment ranking data generation circuit 103 corresponds to a waveform specifying means, and outputs segment ranking data specifying the ranking of segment waveforms for each subchannel 1 and 2 in a time-division manner, and provides it to the parameter memory 102 as described above. . A detailed example of this circuit 1.3 is shown in the 14th example, and is similar to the start address circuit 40 shown in FIG. 9, but the start address memory 56 and end address memory 200 are not provided. . Further, circuits corresponding to 58, 59, 63 to 70 in FIG. 9 are omitted, and the output of the shift register 57 is directly input to the adder 61. In addition, a gate 99 is provided,
Every time the waveform switching command signal WCHG is given, the value “2”
” is applied to the adder 61 via the gate 99. Therefore, when the waveform switching command signal WCHG is generated corresponding to one subchannel, the numerical value "2" is added to the count value output from the shift register 57 at the timing of that subchannel. In this way, the count value of the corresponding subchannel increases by two in response to the waveform switching command signal WCHG. That is, in the example of FIG. 9, in order to increase the count value (segment waveform ranking data) of the subchannel consisting of 2,
By taking the count value of the other subchannel and increasing it by 1, the calculation is equivalent to incrementing it by 2. In contrast, in the example in Figure 14, the count value of the subchannel is directly added. I am trying to add 2.

In FIG. 14, a selector 104 is provided between the selector 60 and the shift register 57 in place of the gate 62 in FIG. This selector 104 is a key-on pulse K
When ONP is "1" (at the start of sound generation), the first half period of clock pulse φ2, that is, subchannel 1, selects the numerical value "1", and the second half period, that is, subchannel 2, selects the numerical value "1".
2". When the key-on pulse KONP is "0", the output of the selector 60 is selected. In this way, when a key is pressed, the numerical value "1" is initially set for sub-channel 1, and the numerical value "2" is initially set for sub-channel 2.
Every time the waveform switching command signal WCHG is given, the signal W
The number corresponding to the subchannel given CHG is 2
Increase by increments. The output of selector 104 is given to parameter memory 102 as segment ranking data. Therefore, the segment order of each subchannel 1 and 2 is "1" and "2" at first, and thereafter, the waveform switching command signal W
Every time CHG is given, r3J+r2J→r3J, r
4J→r5J, r4J→r5J, r13J→・
... alternately changes by 2.

Cross-fade control circuit 105 is basically the same as cross-fade control circuit 16 of FIGS. 2 and 10. The difference is that this crossfade control circuit 105 interpolates the segment waveform even in the attack section, so the crossfade curve data CF is formed and output immediately from the start of sound generation. . Therefore, the details of this cross-fade control circuit 105 are as follows: In FIG. 10, a signal obtained by inverting the key-on pulse KONP is added to the control inputs of the gates 75A and 75B, and the counters 73A and 73B are cleared at the start of sound generation. , corresponds to a modification in which the AND circuit 83 in the switching circuit 81 is omitted and the output signal of the all "0" detection circuit 82 is directly used as the waveform switching preparation signal WCHG'. There is no need for a circuit to do this, and the carry h signal CRY (outputted from the adder 35 in FIG. Since the carry signal CRY is generated every time one cycle of waveform reading is completed, it indicates that the current read phase has become the final phase, similar to the coincidence detection signal EQ.

The envelope generator 106 is basically the same as the envelope generator 17 shown in FIG. 2, except that it generates an envelope waveform signal including attack characteristics.

When a digital filter method is used as the calculation method in the musical sound waveform forming circuit 101, the musical sound waveform forming circuit 101 digitally generates a predetermined sound source waveform signal according to the phase data ADR, as shown in FIG. It includes a generation circuit 110 and a digital filter circuit 111 that filters and controls this sound source waveform signal. In this case, filter coefficients are used as parameters, and the parameter memory 102 stores filter coefficients corresponding to each segment waveform 5EGI, 5EG2, 5EG3, . . . for each tone color A, B, C, . . . .

In addition to the above-mentioned harmonic synthesis method and digital filter method, the musical sound waveform forming circuit 101 is capable of using any para-motor calculation type musical sound waveform forming method, such as the frequency modulation (FM) method and the amplitude modulation (AM) method. In short, it is sufficient if the shape of the musical sound waveform to be formed can be controlled by parameters. In that case, it goes without saying that the types of parameters stored in the parameter memory 102 will change depending on the tone waveform forming method in the tone waveform forming circuit 101.

Alternatively, the entire waveform of the attack portion may be generated by an appropriate means. In order to generate a full attack waveform, for example, predetermined parameters are stored in the parameter memory 102 for each cycle of the full attack waveform, and the tone waveform forming circuit 1
01, it is preferable to use these parameters for each cycle to form each tone waveform of the attack section.

Of course, it can be used.

Similarly to the cross-fade control circuit 105 of FIG. 13 described above, the cross-fade control circuit 16 in the embodiment of FIG. It is possible to use the carry signal CRY generated in .

In addition, without waiting until the readout phase of the preceding segment waveform reaches the final phase (end address), if even an intermediate phase matches the initial phase of the next segment waveform, the waveform switching command signal WCI-I G is sent. may be generated. For example, when one segment waveform consists of multiple periodic waveforms.

Since there are some phases (for example, zero phase) that are the same as the initial phase or the final phase in the segment waveform, the waveform switching may be performed on the condition that that phase is reached.

〔Effect of the invention〕

As described above, according to the present invention, the interpolation function is generated according to a unique time function, and the waveform switching is controlled according to this time function. In addition to obtaining the spectral time-varying effect, there is no compression of interpolation time in the high frequency range.
Smooth interpolation (waveform transition) is guaranteed in any range.

Moreover, in this case, the waveform switching control is performed by considering not only the above time function but also the phase of the waveform data currently being read, so that the phase of the waveform before switching is the initial phase of the waveform after switching. It is possible to perform waveform switching when the phases substantially match, and it is possible to prevent unnatural waveform changes when switching waveforms.

[Brief explanation of drawings]

FIG. 1 is a schematic diagram for explaining the principle of musical tone signal generation in an embodiment of the present invention, FIG. 2 is an electrical block diagram showing an embodiment of an electronic musical instrument to which the musical tone signal generation device according to the present invention is applied, 3 is a timing chart showing an example of clock pulses and channel timing signals and an example of time-division channel timing used in the same embodiment;
The figure shows an example of the memory map of the waveform memory in the same embodiment, Figure 5 is an electrical block diagram showing an example of the phase generator of Figure 2, and Figure 6 is an example of the time division control circuit of Figure 5. 7 is a timing chart showing an example of each part signal of FIG. 6, FIG. 8 is an electrical block diagram showing an example of the attack end detection circuit of FIG. 5,
9 is an electrical block diagram showing an example of the start address generation circuit of FIG. 5, FIG. 10 is an electrical block diagram showing an example of the cross-fade control circuit of FIG. 2, FIG. FIG. 9 is a timing chart showing an example of each part signal in FIG. , FIG. 13 is an overall block diagram of an electronic musical instrument showing another embodiment of the present invention, FIG. 14 is an electrical block diagram showing an example of the segment order data generation circuit of FIG. 13, and FIG. FIG. 16 is a block diagram schematically illustrating an example of a tone waveform forming circuit constructed using a harmonic synthesis method. FIG. 16 is a block diagram schematically showing an example of the tone waveform forming circuit constructed using a digital filter method. 10...keyboard, 11...key assigner, 13...
Phase generator, 14... Waveform memory, 16... Cross-fade control circuit, 18, 19.20... Weighting arithmetic circuit which is part of interpolation means, 28... Reading means, 40 . . . Start address generation circuit corresponding to waveform specifying means, 73 . . . Counting means, 81 . . . Switching control circuit. , 100...1-cycle phase data generation circuit, 101...
・Tone sound waveform forming circuit, 102...parameter memory,
103...Segment rank data generation circuit, 200...
...End address memory, 201...Comparator.

Claims (1)

[Scope of Claims] 1. Waveform storage means that stores waveform data of a plurality of different musical sound waveforms; reading means that reads out waveform data of a predetermined musical sound waveform from the waveform storage means according to the musical sound frequency to be generated; waveform specifying means for temporally switching and specifying a musical sound waveform to be read from the waveform storage means; Interpolation means for weighting, counting means for generating a time function for setting the time change of weighting in the interpolation means, and the output of the counting means and the phase of the waveform data currently being read by the reading means. and switching control means for controlling waveform switching in the waveform specifying means according to information. 2. The switching control means detects that the time function generated by the counting means changes to a predetermined value, and based on this detection, the reading phase of the musical sound waveform by the reading means becomes its final phase. The musical tone signal generating device according to claim 1, wherein a waveform switching command signal is given to the waveform specifying means on the condition that the waveform switching command signal is given to the waveform specifying means. 3. The switching control means detects that the time function generated by the counting means changes to a predetermined value, and based on this detection, the reading phase of the musical sound waveform by the reading means changes to the next musical tone to be switched to. 2. The musical tone signal generating device according to claim 1, wherein a waveform switching command signal is given to said waveform specifying means on the condition that the waveform has almost the same initial phase as the initial phase of the waveform. 4. a tone waveform forming means that forms a tone waveform having a shape determined by the parameters and also forms the tone waveform in accordance with a phase specified by phase data; parameter storage means that stores the parameters that determine the shape; phase data generation means that generates the phase data that changes according to the frequency of the musical tone to be generated and supplies it to the musical sound waveform forming means; and the musical sound waveform forming means. a waveform switching control means for temporally switching and specifying a musical sound waveform to be formed by the musical sound waveform, reading out the parameters corresponding to the specified musical sound waveform from the parameter storage means and applying them to the musical sound waveform forming means; When switching waveforms, interpolation means weights both tone waveforms so as to smoothly transition from the preceding tone waveform to the next tone waveform, and a time function is generated for setting the time change of the weighting in the interpolation means. and switching control means for controlling waveform switching in the waveform specifying means according to the output of the counting means and information indicating the phase of the waveform data currently being read by the reading means. Device. 5. The switching control means detects that the time function generated by the counting means changes to a predetermined value, and based on this detection, the reading phase of the musical sound waveform by the reading means changes to the next musical tone to be switched to. 5. The musical tone signal generating device according to claim 4, wherein a waveform switching command signal is given to the waveform specifying means on the condition that the waveform substantially matches the initial phase of the waveform.