JPS62146489A - Dynamic memory - Google Patents

Abstract

PURPOSE:To reduce a peak current at the time of operation and the ratio of change by time and to obtain noiseless and stable operation by dividing a bit line sensing amplifier in each memory cell array and operating respective arrays with the interval of a delay time. CONSTITUTION:When an external driving signal, the inverse of RAS, is turned from 'H' to 'L' and a memory is activated, precharge signals phiP1, phiP2 are turned from 'H' to 'L', a low recorder 1-i is selected, a signal phiA is turned from 'L' to 'H', and each word line from memory cell arrays 1, 2 is turned from 'L' to 'H' and selected. The information of a memory cell CS connected to the selected word line is transmitted to a bit line and sense amplification is executed in accordance with the change of activated signals, the inverse of phi and the inverse of phi', from 'H' to 'L'. In this case, a control circuit 4 to be a delay control means controls the application of each activated signal to any memory cell array on the basis of address information phiadd.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field to Which the Invention Pertains] The present invention relates to a large-capacity dynamic memory.

[Prior art]

Figure 1 shows a large capacity random access memory (RAM).
That's what it means. ) is known as 64° dynamic °R
FIG. 2 is a schematic block diagram of an AM memory cell array.

This RAM has two memory cell arrays 1 and 2 each consisting of 128 row decoders and word lines in the column direction and 256 bit lines and bit line sense amplifiers in the row direction. In this conventional RAM, in order to complete refreshing of all memory cells in 1281J7 retrieval cycles, one word line is selected from both blocks in one access cycle, and 512 bit line sense amplifiers are selected. It is configured to operate.

An outline of the operation of this RAM will be explained using FIG. 2. When the external drive signal RAS changes from @H# level to ``L# level and the memory is activated, the precharge signal φ is first activated.
P1 changes from ``H'' to ``L'', and then the row address signal is transmitted to the row decoder, and the node of the row decoder of the non-selected word changes from ``H'' to L#. Then, φA goes from “L” to ‘H’ and the selected word changes from “L” to @H#
Therefore, unselected words remain 'L', and one of the 128 words in each cell array is selected. Information in the memory cell C8 connected to the selected word line is transmitted to the bit line, Amplified by a bit line sense amplifier.

The waveform order at this time is that the precharge signal φP2 is “H”
After the information in the memory cell is sufficiently transmitted to the bit line, φ changes from ``H'' to ``L'' and bit line sense amplification is performed (fk-).

In such a conventional RAM, the above-mentioned row decoder discharge and 512 bit line sense amplifiers are activated simultaneously in two memory cell arrays. That is, the current waveform has two peaks as shown by a and b.

On the other hand, when RAS goes from @L to 'H' and the memory enters the precharge state, the row decoder is activated by φP1.
The bit line is precharged from ``L'' to ``H'' and then the bit line is precharged by φP2. The current waveform has peaks such as c and d corresponding to the precharging of 256 row decoders.

Since charging and discharging must be performed rapidly for high-speed operation, the peak current and the time rate of change of current at that time are quite large.

Now, let's calculate the amount of current assuming a memory with a single 5V power supply. If the parasitic capacitance of the bit line is o, spF' on one side of the bit line sense amplifier, then the charge charged to 5V is 3Q.
In order to discharge to Ov in a time of about ns, as shown in the following formula, an average current of 40 mA flows, and the peak current is 2 to 3 times the average current, so it is about 100 mA.The time rate of change of current is also It is expected that it will be 10 mA/ls or more.

When configuring a device using a plurality of memories, care must be taken in designing the power supply line or ground line in order to deal with noise due to peak current.

Furthermore, when designing the memory itself, it is necessary to pay attention to the impedance design of wiring, etc., in order to deal with noise due to peak current or the time rate of change of current.

By the way, if the time rate of change of the current is I QmA/ns and the wiring impedance is 20nH, then the voltage is 200mV.
noise occurs. In the case of a multi-address type RAM, there is a possibility that the latch timing of the row address coincides with the operating timing of the bit line sense amplifier. In that case, the 200 mV noise reduces the operating margin of the address buffer and causes malfunction.

We have considered the case of discharging above, but the same noise occurs when charging during precharging.Since the output during precharging of RAS is controlled by a different drive signal CAS, the output level may drop to a malfunction level due to noise or It will rise.

In DRAM, the normal output llL# level is 400mV or less, but by design it is set to 9200mV.
``L# level may exceed 400mV due to 200mV of noise.

That is, in the conventional dynamic memory, a large peak current having a large time change rate due to rapid charging and discharging of charges when activating a bit line sense amplifier or precharging a row decoder and bit line, This method has the drawback of generating noise and causing memory malfunction.

[Purpose of the invention]

An object of the present invention is to eliminate the above-mentioned drawbacks, thereby reducing the magnitude of the peak current based on charging and discharging as well as the magnitude of its time change rate compared to the conventional l! The object of the present invention is to provide a dynamic memory that operates more stably by making t, pl very small, less than 1/2.

[Structure of the invention]

The dynamic memory of the present invention is a dynamic memory having a plurality of memory cell arrays, and has a delay control means that divides the bit line sense amplifier, row decoder, and bit line M into each memory cell array, and operates each one with a delay time. It consists of

[Explanation of Examples]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 3 is a schematic block diagram showing the main parts of the first embodiment of the present invention. In this embodiment, the present invention is applied to the dynamic RAM 64 of the conventional example, and the same circuits as the conventional example of FIG. 1, such as each memory cell array and row decoder, are shown using the same symbols.

In this embodiment, the bit line sense amplifier activation signal φ shown in the conventional example of FIG. The difference from the conventional example is that the bit line sense amplifier group of the memory cell array 2 is operated after a delay time.

Here, the operation of this embodiment will be explained with reference to a time chart shown in FIG. 4 for explaining the operation of this embodiment.

When the external drive signal RAS goes from 'H' to 'L' and the memory is activated, φP1. The precharge signal such as φP2 changes from “H” to “L”, one of the row decoders is selected and remains at 9H”, and φA changes from “L” to 1H, resulting in 1 from each of memory cell arrays 1 and 2. Words for each book will be selected from 1L'' to 1H#. The information of the memory cell C8 connected to the selected word line is transmitted to the bit line, and from 'H' of φ and φ' to @L
Sense amplification is performed according to the change to ``.

As a result of dividing the bit a sense amplification for each memory cell, the current flowing through the memory is as shown in FIG.

It is divided into two small peaks as shown in b'.

In the conventional memory shown in FIG. 1, since the activation signal φ starts discharging once or twice in the memory cell array, the current has a peak that is about twice as large as that in the embodiment of the present invention.
The time rate of change of the current is also approximately doubled. That is, according to this embodiment, the magnitude of the peak current of the memory generated during the operation of the bit line sense amplifier and its rate of change over time can be reduced to about 1/2 of that of the conventional memory. Therefore,
A stably operating dynamic memory without noise disturbances based on peak currents is obtained.

FIG. 5 is a schematic block diagram showing the main parts of the second embodiment of the present invention. This embodiment is obtained by adding a control circuit 4 as delay control means to the circuit of the embodiment shown in FIG. Here, the control circuit 4 is for controlling to which memory cell array the activation signal f and the activation signal v' are applied, using address information φadd.

Therefore, according to this embodiment, it is possible to solve the problem of the increase in access time due to the division operation of the bit line sense amplifier group, which was considered to be a problem in the first embodiment. That is, 1
Because it is known from the address information, especially in the case of multi-address memory, the row address information, that the memory cell whose information is to be read or written in by being selected in one access cycle exists in either of the two memory cell arrays. To prevent an increase in access time by first operating the bit line sense amplifier group on the side of the memory cell array where the memory cell exists, and then operating the bit line sense amplifier group belonging to the other memory cell array. I can do it. In this case, it goes without saying that even if the cycle is a fresh cycle due to the internal address signal, the design can be made so that the operation order can be appropriately determined. No. 61 is a schematic block diagram showing main parts of a third embodiment of the present invention. This example is the third
The configuration is such that the row decoder precharge and bit line precharge of the first embodiment shown in the figure can be performed by dividing into each block of memory cell arrays 1 and 2.

Since the load on the row decoder or bit line is large in a high-density memory, when the memory cell arrays 1 and 2 are charged at once as in the first embodiment, large peak currents c and d as shown in FIG. 4 occur. I end up. In the embodiment of the present invention, this is divided into two parts, so c and c in FIG.
The current peak waveforms are as shown in ', d, and d', and the current noise can be halved.

In the fourth embodiment of the present invention, the order of dividing and precharging in the 8g3 embodiment is controlled by address information. Since this is a direct analogy of the relationship between the first and second embodiments, illustration thereof is omitted.

That is, if the memory cell selected at the time of activation immediately before precharge mode is in memory cell array 1, memory cell array 2 is operated after a certain delay time, so RAS
As the activation time of the memory cell array 1 becomes shorter, a difference occurs between the activation time of the memory cell array 1 and the activation time of the memory cell array 2, resulting in a difference in operating margin. This is set as φPl, φP1' or φP2 depending on the address information. φ
The purpose is to reduce it by controlling P2'.

In the third and fourth embodiments, the row decoder precharging and bit line precharging are performed together to divide the memory cell array, but it is clear that they are effective even if they are performed independently.

Although the above explanation has been made regarding the N-channel MO8, it is clear that the same applies to the P-channel MO8 or the complementary MO8K. In addition, although the explanation has been given assuming that the charging and discharging current is divided into two, it is also possible to divide it into multiple divisions such as three, and the magnitude of the peak current and the magnitude of its time change rate are also small corresponding to the number of divisions. Become.

〔Effect of the invention〕

As described above in detail, the dynamic memory of the present invention has a delay control section means that divides the bit line sense amplifier and row decoder for each memory cell array and operates each with a delay time. All sense amplifiers or row decoders do not operate simultaneously, but operate in a time-division manner, so the magnitude of the peak current flowing during operation and the magnitude of its time change rate can be reduced to less than half of the conventional one. This has the effect of providing stable operation without noise interference.

[Brief explanation of drawings]

FIG. 1 is a schematic block diagram of a memory cell array of a conventional 64 type dynamic RAM, FIG. 2 is a time chart for explaining the operation of the conventional example, and FIG.
FIG. 4 is a time chart for explaining the operation of the first embodiment of the present invention, and FIG. 5 is a schematic block diagram showing the main parts of the second embodiment of the present invention. FIG. 6 is a schematic block diagram showing main parts of the third embodiment of the present invention, and FIG. 7 is for explaining the operation of the third embodiment of the present invention. This is a time chart. 1.2-...Memory cell array, 3,5.6-
...Delay circuit, 4...Control circuit, 1-1
, 1-2, 1-3, 2-1.2-2.2-3...
...Row decoder, 1-4.1-5゜1-6, 2-
4, 2-5, 2-6...Bit line sense amplification, PAS, φP1. $P1', φA, φP2. φP2'
, φ, φ' ・−・− signal.

Claims (6)

[Claims] (1) A dynamic memory having a plurality of memory cell arrays, characterized in that it has a delay control means that divides a bit line sense amplifier into each memory cell array and operates each one with a delay time. (2) The dynamic memory according to claim (1), wherein the operation start order of the bit line sense amplifiers which are divided and operated for each memory cell array is controlled by address information. (3) A dynamic memory having a plurality of memory cell arrays, characterized in that it has a delay control means that divides the row decoder into each memory cell array and precharges each one after a delay time. (4) The third aspect of the present invention is configured such that the precharge start order of the row decoder, which is divided and precharged for each memory cell array, is controlled by address information.
Dynamic memory described in section ). (5) A dynamic memory having a plurality of memory cell arrays, characterized in that it has a delay control means that divides a bit line into each memory cell array and precharges each one after a delay time. (6) The dynamic memory according to claim (5), wherein the precharge start order of bit lines that are divided and precharged for each memory cell array is controlled by address information.