JPS62145449A - Information transfer system - Google Patents

Abstract

PURPOSE:To improve the processing efficiency of information transfer by setting a data buffer information area storing a final information address and a transfer information area storing transfer information. CONSTITUTION:An equipment 20 of a layer 3 writes transfer information on a data buffer of a common memory 40, e.g., a transfer information area 44-0 of a buffer 41-0. When the transfer information is long and it is required to provide a chain, chaining information C is brought to 1 in a chaining information area 42-0 and an idle data buffer to write the succeeding transfer information, e.g., DBNO:1 of 41-1 is written on an information area 43-0. Then the device 20 informs a reception request SRQ, in this case, DBNO:0 written at first on the transfer information to a device 10a of layer 2 via an input port 17. The device 10a reads the informed data DBNO:0 and reads the chaining information C of the buffer 41-0.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to an information transfer method in two devices 111, such as a communication IIIall device and its L-equipped device using a high-level data link control procedure. It is.

(Prior art) Conventionally, high-level data link control procedures (HDLC
) is used to transfer information between a communication control device (layer 2 device) and its upper device a (layer 3 device), which uses a common memory (hereinafter referred to as shared memory) between both devices. ), and the shared memory is accessed from both layer 2 devices and layer 3 devices.

As a description of such an information transfer method, Densui et al.
I (Microprocessor Peripheral LSI Series No. 8)
” (Nikkei Electronics, 1984, 10.8,
P131-158). This will be explained below.

FIG. 2 shows an example of a system configuration in a conventional information transfer method. In the figure, 10 is a layer 2 device (L2),
20 is a layer 3 device (L3), 30 is a shared memory, and the layer 2 device 10 includes a serial data interface (801) 11, a processor (CPU) 12, a read only memory (ROM) 13, and a random access memory. (RAM) 14 and a direct memory access controller (DMAC) 15.

Further, FIG. 3 shows an example of the internal configuration of the shared memory 30 and the contents of the register 151 in the DMACl3. That is, the shared memory 30 stores a transmission lookup table (T) that stores information necessary for transmission and reception operations.
18 bytes x 8〉31 in LOO, and look for reception.
It has an up table (RLOO: 8 bytes x 8) 32, and separately from this, it has a plurality of transmit data buffers 33 and receive data buffers 34 for storing actual transfer information.

The data buffers 33 and 34 are common memories partitioned into fixed sizes, and when the transfer information exceeds one data buffer, the subsequent transfer information is transferred to other free data.
By accumulating the information in the buffer 33 (or 34) (hereinafter referred to as forming a chain), long transfer information can be handled.

When the chain is assembled, the information displayed is:
A transfer address indicating the address of the next data buffer 33 (or 34) is placed at the end of the data buffer 33 (or 34).

Next, the operation will be described using information transfer from the layer 3 device 20 to the layer 2 device 10 as an example.

(1) The layer 3 device 20 writes transfer information to the transmission data buffer 33 of the shared memory 30. If it is necessary to form a chain, write transfer information one after another while writing the transfer address.

(2) The layer 3 device 20 writes the start address of the data accumulated in the transmission data buffer 33 and the length of the transmission data to segment 0 of TLOQ 31, and sets the transmission data buffer ready flag to “1”. Make it ゛.

(3) The layer 3 device M20 notifies the layer 2 device 10 of a transmission request by setting the bit for transmitting the information frame to °1''.

(4) DMACl3 in the layer 2 device 10 is TLOO
Read the contents of segment O of 31.

(5) After confirming that the transmission data buffer ready flag is 1'', the DMACl 3 sends the information frame to the SD 111 while putting the transfer information in the transmission data buffer 33 into the information field. Then, it is further transmitted to the ray A'1 device constituting the device l!l!m such as a modem.

(6) The DMAC 15 counts the number of bits of the transfer information, compares it with the length of the transmission data written in segment 0, and checks the end of the transfer.

(7) When the information in one transmission data buffer 33 has been transferred, if the transfer is not completed, that is, the length of the transmission data and the count number do not match, the information is concatenated according to the transfer address. The information in the transmitted data buffer 33 is transferred.

(8) In this way, the operations of (6) and (7) are repeated until the transfer is completed.

(Problem to be Solved by the Invention) However, in the above-mentioned information transfer method, since the start address of the transfer data and the length of the data must be given, 1) The longer the data is chained, the shorter the length of the data becomes. Long information requires a large number of bits to notify the length of the data. 2) In order to know when data transfer is complete, a counter is required to count the number of bits throughout, and the bits of this counter 3) If the information does not end within one data buffer, determining whether the data continues in the next data buffer is as follows:
Since this is done by comparing the count value of the counter with the length of the data, there are problems such as the need to compare a large number of bits.

SUMMARY OF THE INVENTION An object of the present invention is to provide an information transfer method that eliminates the above-mentioned problems and provides efficient processing related to information transfer.

(Means for Solving the Problems) In order to solve the above problems, the present invention provides the above-mentioned information transfer method for transferring information between two devices via a shared memory accessible by the two devices. The shared memory is configured with at least a plurality of data buffers, and means is provided for transmitting and receiving a transfer request consisting of information without indicating the location of the data buffer storing transfer information between the two devices, and each of the data buffers A chaining information area that stores chaining information indicating whether or not there is a data buffer that stores continuation information in the buffer, and a chaining information area that stores chaining information that indicates whether or not there is a data buffer that stores continuation information. Data that stores next data buffer information that indicates the position, and if there is no data buffer that stores the continuation information, stores the final information address that indicates the address where the most corrupted transfer information is stored in the data buffer. A buffer information area and a transfer information area for storing transfer information are set.

(Operation) According to the present invention, a transfer request can be issued simply by sending information indicating the position of a data buffer that has accumulated transfer information, without reading the chaining information in the chaining information area of the data buffer. By this, it is possible to determine whether or not there is a data buffer that has stored continuation transfer information, and if there is a continuation data buffer, the next data buffer is stored based on the next data buffer information in the data buffer information area. When the buffer can be accessed and there is no continuation data buffer, check whether the transfer is complete by comparing the count value from the start of reading the data buffer with the final information address in the data buffer information area. I can do it.

(Embodiment) FIG. 1 shows an embodiment of the system of the present invention, in which the same components as those in FIG. 2 are denoted by the same reference numerals. That is,
10a is a layer 2 device, 20 is a layer 3 device, and 40 is a shared memory.

The layer 2 device 10a has a serial data interface (SDI>11), a processor (CPU) 12, a read-only memory (ROM) 13, a random access memory (RAM) 14, and a direct memory access controller (to DM8) 15. , an output boat 16 , and an input boat 17 .

The output boat 16 and the input boat 17 are for directly exchanging commands between the layer 2 device 10a and the layer 3 equipment 20, and each receives a reception request RR.
Q to the Layer 1 F3 device 20, and receives the transmission request SRQ notified from the Layer 3 device 20. The received request RRQ.

The contents of the transmission request SRQ include information such as an address and a number indicating the location of the data buffer in the shared memory 40 in which the transfer information is stored. Note that if the data buffers are chained, the position of the first data buffer, for example, the number, is notified.

FIG. 4 shows the contents of the shared memory 40, which has the same capacity and is distinguished by data buffer numbers (DBNOs) 0.1.2. - Multiple data buffers 41-0.41-1.41-2 given -n
．． ...41-n is provided. Each data buffer 41-0 to 41-n is connected to a chaining information area 42.
-O to 42-n and data buffer information area 43-O
43-n and transfer information areas 44-0 to 44-n.

Chaining information C is stored in the chaining information areas 42-O to 42-n, and the chaining information C is “OII
When it is "1", it indicates that there is no next chained data buffer, and when it is "1", it indicates that there is a next chained data buffer. The contents of the data buffer information areas 43-0 to 43-n differ depending on the value of chaining information C, and in the case of C-0, the final information indicating the 7th address of the last transfer information in the data buffer. An address is stored, and in the case of C-1, next data buffer information indicating the location of the next data buffer, for example DBNO, is stored. In addition, transfer information area 44-
Transfer information is stored in 0 to 44-n.

Next, the operation will be explained using an example of information transfer from layer 3 device @ 20 to layer 2 device 10a.

(1) The layer 3 device 20 stores transfer information in the transfer information area 44-0 of an empty data buffer, for example 41-0.
It's crowded. If the transfer information is long and it is necessary to form a chain, use the chaining information C in the chaining information area 42-0.
is set to "1", and then an empty data buffer for writing the subsequent transfer information, for example, the DBNO of 41-1, that is, "1" is written to the data buffer information area 43-0.

(2) All the transfer information is stored in the data buffer 41-1.
If the layer 3 device 20 has completed the data buffer 41, the layer 3 device 20
The chaining information C in the chaining information area 42-1 of -1 is set to 0', and the transfer information area 44-1
The address where the transfer information was last written is written in the data buffer information area 43-1.

(3) The layer 3 device M20 has the following information for the layer 2 device 10a:
Here, the reception request 5RQ1 is notified of the first written DBNorOJ of the transfer information via the input port 17.

(4) The layer 2 device 110a receives the notified DBNO “
0'' is read, and then the chaining information C of the data buffer 41-0 is read.

(5) At this time, since the chaining information C is "°1", the transfer information area 44-0 of the data buffer 41-0
The information frame is sent to the layer 1 device (not shown) via the 5D 111 while inserting all the information in the information field into the information field.
Send to.

(6) When all the transfer information in the data buffer 41-0 has been sent, select the data buffer 41-1 in which the next information is stored from the content D1 of the data buffer information area 43-0, that is, DBNOrIJ. , the contents of the chained information C are checked.

(7) At this time, since C="0", the final information address in the transfer information area 44-1 is recognized from the contents of the data buffer information area 43-1, and the final information address in the transfer information area 44-1 is recognized. The information frame is sent to the layer 1 device while inserting the information of layer 1 into the information field. At this time, while counting the number of bits of the sending information, it is compared with the final information address to check whether the transfer has been completed.

In addition, in operation (6), if C = "゛1", operation (5)
, repeat (6), and in operation (4) C-"O"
In this case, the process moves to operation (7).

In this way, according to this embodiment, whether information is closed within one data buffer or whether it is chained and continues to the next data buffer can be determined only by the 1-bit chaining information. Completion checking simply requires counting the number of bits of information for the last part of the chained data buffer and comparing this with the final information address, which can contain up to one data buffer. Since it is for a buffer, there is no need to count and compare the number of bits in all of the transfer information, as in the past, and to notify the length data, which does not represent the total number of pits. In addition, the chain information and the final information address are data
Since the table is stored in a buffer and the transfer request is made by directly sending the DBNO, there is no need to provide a table in the shared memory as in the conventional case, and the shared memory can be used effectively.

Note that in the embodiment described above, the transfer request is sent via the input (or output) port, but the present invention is not limited to this. Furthermore, the arrangement of the chained information area, data buffer information area, and transfer information area within each data buffer can be arbitrarily determined, and is not limited to what is shown in the drawings.

FIG. 5 shows another embodiment of the present invention, in which a page memory is used as the shared memory. That is,
In the figure, page memories (PM) 50-0 to 50-n are composed of a plurality of (n in this case) memories each having a fixed storage capacity that is independent of each other. In addition, each PM50-0
~50-n has a number # to identify each
0 to #n are assigned. In addition, 11 is a serial data interface (SDI), and 12 is a processor (CPU).
), 18.19& as the input/output port (portO, por
tl). The input/output ports 18 and 19 are a combination of the output port and the input port in the embodiment described above, and are respectively connected to two layer 3 devices (not shown). Further, 11a, 12a, 18a, 19a are data buses of each device, and data buses 11a, 18a, 19a are data buses of each device.
9a are all connected to the data bus 12a. Also,
The CPU 12 independently (like a 0-tally switch) controls which of the PMs 50-1 to 5O-nG, t and the data buses 11a, 12a, 18a, and 19a to operate under. It has become.

Next, the operation will be explained using an example of information transfer from a layer 3 device to a layer 2 device.

(1) The layer 3 device that has requested the information transfer transfers the information to the available port via the connected input/output port, for example 18.
1IJ1[IL, writes the information to be transferred so that, for example, 50-0 can operate under the data bus 18a. In this case, if the transfer information cannot fit in one page memory, a chain is formed according to the present invention.

(2) When the layer 3 device finishes writing the information, it notifies the CPU 12 via the input/output port 18 of a transfer request, that is, the number of the page memory where the information is written, here "#0". If a chain is formed, it is sufficient to notify only the number of the first page memory in which transfer information is written.

(3) When the CPU 12 receives a notification from the input/output boat 18, the CPU 12 transfers the page memory 50-0 to the data bus 1 of its own device.
Switch to operate under 2a.

(4) The CPU 12 processes the contents of the PM 50-0 according to the present invention.

In this way, the present invention is effective not only when the transfer means between the layer 2 device and the layer 3 device is based on DMAC, but also when other means are used, and the transfer processing can be made independent in units of one data buffer. For this reason, it is particularly effective when each data buffer is independent, such as in the transfer method using the page memory described above.

Up to now, we have explained information transfer between layer 2 devices and layer 3 devices, but information transfer between layer 2 devices and below and layer 3 devices and above, or between layer 3 devices and below and layer 4 devices and above. It is also effective in information transfer and can be applied to all other devices.

(Effects of the Invention) As explained above, according to the present invention, 1 data buffer?
It is only necessary to judge whether the information is closed in the chained data buffer or whether it is chained and continues to the next data buffer.In addition, checking the completion of the transfer can be done by checking the chained data buffer. All you need to do is count the number of bits of information for the last part of the buffer and compare it with the final information address.Furthermore, since this final information address is for a maximum of one data buffer, it is not necessary to transfer it as before. It eliminates the need to count and compare the number of bits of all information and to notify the length of data representing the total number of bits, and has the advantage that it is possible to have a configuration in which transfer operations are independent in units of one data buffer. .

[Brief explanation of drawings]

FIG. 1 is a system configuration diagram showing an embodiment of the information transfer method of the present invention, FIG. 2 is a diagram showing an example of a system configuration using a conventional information transfer method, and FIG. 3 is a diagram showing the configuration of a conventional shared memory. FIG. 4 is a diagram showing the configuration of a shared memory according to the present invention, and FIG. 5 is a system configuration diagram showing another embodiment of the present invention. 10a... Layer 2 device, 11... Serial data interface, 12... Processor, 15... Direct memory access controller, 16... Output port, 17... Input port, 20... Layer 3V
R location, 40...Shared memory, 41-0 to 41-n...
- Data buffer, 42-O to 42-n... Chaining information area, 43-0 to 43-n... Data buffer information area, 44-0 to 44-n... Transfer information area. Patent Applicant Oki Electric Industry Co., Ltd. Representative Patent Attorney Furu 1) Sei Takamoto Kinmei's Shared Memory A Wei Concave No. 4 [

Claims (1)

[Claims] An information transfer method in which information is transferred between two devices via a shared memory accessible by the two devices, wherein the shared memory is configured with at least a plurality of data buffers; Means is provided for transmitting and receiving a transfer request consisting of information indicating the location of a data buffer storing information between the two devices, and determining whether or not each of the data buffers has a data buffer storing continuation information. If there is a data buffer that stores the next data buffer, stores the next data buffer information that shows the location of the next data buffer, and stores the next data buffer. If there is no data buffer, a data buffer information area is set to store the final information address indicating the address where the last transfer information is stored in the data buffer, and a transfer information area is set to store the transfer information. An information transfer method characterized by: