JPS6214542U - - Google Patents

Info

Publication number
JPS6214542U
JPS6214542U JP10458685U JP10458685U JPS6214542U JP S6214542 U JPS6214542 U JP S6214542U JP 10458685 U JP10458685 U JP 10458685U JP 10458685 U JP10458685 U JP 10458685U JP S6214542 U JPS6214542 U JP S6214542U
Authority
JP
Japan
Prior art keywords
memory
data
computer system
performs
dma controller
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10458685U
Other languages
English (en)
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP10458685U priority Critical patent/JPS6214542U/ja
Publication of JPS6214542U publication Critical patent/JPS6214542U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Bus Control (AREA)
JP10458685U 1985-07-09 1985-07-09 Pending JPS6214542U (US20080293856A1-20081127-C00127.png)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10458685U JPS6214542U (US20080293856A1-20081127-C00127.png) 1985-07-09 1985-07-09

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10458685U JPS6214542U (US20080293856A1-20081127-C00127.png) 1985-07-09 1985-07-09

Publications (1)

Publication Number Publication Date
JPS6214542U true JPS6214542U (US20080293856A1-20081127-C00127.png) 1987-01-28

Family

ID=30978218

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10458685U Pending JPS6214542U (US20080293856A1-20081127-C00127.png) 1985-07-09 1985-07-09

Country Status (1)

Country Link
JP (1) JPS6214542U (US20080293856A1-20081127-C00127.png)

Similar Documents

Publication Publication Date Title
JPS6214542U (US20080293856A1-20081127-C00127.png)
JPS63179548U (US20080293856A1-20081127-C00127.png)
JPS6214541U (US20080293856A1-20081127-C00127.png)
JPH0337543U (US20080293856A1-20081127-C00127.png)
JPS63109808U (US20080293856A1-20081127-C00127.png)
JPH01106949U (US20080293856A1-20081127-C00127.png)
JPS6174148U (US20080293856A1-20081127-C00127.png)
JPS63159440U (US20080293856A1-20081127-C00127.png)
JPH0344737U (US20080293856A1-20081127-C00127.png)
JPS6142649U (ja) デ−タ転送装置
JPH0276787U (US20080293856A1-20081127-C00127.png)
JPH01155553U (US20080293856A1-20081127-C00127.png)
JPS62192449U (US20080293856A1-20081127-C00127.png)
JPS6034651U (ja) Dma制御装置
JPS6353151U (US20080293856A1-20081127-C00127.png)
JPS63163543U (US20080293856A1-20081127-C00127.png)
JPH0330191U (US20080293856A1-20081127-C00127.png)
JPH0181795U (US20080293856A1-20081127-C00127.png)
JPS60107896U (ja) 表示メモリ制御回路
JPS6380603U (US20080293856A1-20081127-C00127.png)
JPS6392971U (US20080293856A1-20081127-C00127.png)
JPH0284964U (US20080293856A1-20081127-C00127.png)
JPS5897605U (ja) マルチプロセツサによるバツチプロセス用コントロ−ラ
JPH0374051U (US20080293856A1-20081127-C00127.png)
JPH0196061U (US20080293856A1-20081127-C00127.png)