JPS62143472A - Semiconductor device - Google Patents

Abstract

PURPOSE:To decrease the short-channel effect, the leak in a junction layer, and the junction capacity and resistance, by covering totally or partially a contact region where a semiconductor is contacted with a metal or with an alloy of metal and semiconductor, with an insulator. CONSTITUTION:A gate oxide film 2 is formed in a predetermined region on an Si substrate 1 and a gate electrode 3 is formed thereon. Oxygen ions 4 are implanted, using the gate electrode 3 as a mask. The substrate is then heat treated in the atmosphere of nitrogen. The Si substrate is exposed and oxidized, whereby an oxide film 6 is formed. Subsequently after W is deposited, the substrate is heat treated in the atmosphere of hydrogen so that a silicide is formed only on the region where Si single crystals are exposed, and unreacted W on the SiO2 is removed while only the silicide 9 is left. Arsenic ions are then implanted and the substrate is heat treated. In this manner, it is possible to form an impurity diffusion layer 8 having a gentle concentration gradient only in the ends thereof to become source and drain.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a semiconductor device, and particularly to a semiconductor device equipped with an impurity junction layer and an electrode suitable for a fine MO5 type device.

[Background of the invention]

Generally, MOS (Metal-Oxide-S
An impurity diffusion layer of an em1conductor type Si semiconductor device is provided in a Si single crystal substrate, and is used as a source, drain, or wiring. MO5VLSI (V
ery Large 5cale engineering tagged
High integration of semiconductor devices such as C1rcuit.

As speed increases, the elements constituting these devices are being miniaturized. However, in addition to the advantages associated with miniaturization, problems have also emerged. Among these, the following four problems are caused by the miniaturization of the diffusion layer.

(1) Fine MO8h run transistor It is easy to manufacture devices with a desired threshold voltage with good reproducibility.

This is because the channel length dependence of the threshold voltage drops sharply in a short channel region of approximately 1 μm or less of channel length. This phenomenon is called short channel effect.
This occurs because the depletion layer from the source and drain extends to the center of the channel region. One method of reducing the short channel effect is to make the source and drain shallower. However, as a result of this, the resistance of the diffusion layer has increased, resulting in a decrease in the mutual conductance of the transistor, which has become an obstacle to the current drive ability and high speed ratio of the operation. As a countermeasure to this problem, a method of lining the upper surfaces of the source and drain with a compound of metal and Si (silicide) to lower the resistance has been widely studied. However, it has become clear that forming silicide has the drawback of increasing leakage current in the diffusion layer.

(2) In a short channel MOS transistor, the electric field strength at the drain end becomes strong, so the energy of carriers becomes high, and the so-called hot carrier resistance, in which carriers are injected into the gate oxide film and the threshold voltage fluctuates, becomes low.

(3) With the increase in integration, alpha rays generated when radioactive impurities contained outside semiconductor devices or in the materials used in the devices decay enter the semiconductor substrate, causing electrons and holes due to ionization. The problem of soft errors that cause equipment to malfunction has become prominent. These carriers generated by ionization also flow into the diffusion layer, causing soft errors.

(4) In highly laminated MO5VLSIs, signal delays due to junction capacitance formed between the impurity diffusion layer and the semiconductor substrate have become noticeable.

Related prior art includes, for example, IE Transactions on Electron.
Devices (IEEE Transactions
Electron Devices), ED-
28, pp. 10413-1087, &9. September 1981.

[Purpose of the invention]

An object of the present invention is to provide an MO8 type semiconductor device in which the above-mentioned defects caused by miniaturization of elements are reduced by covering the entire or part of the contact area between a metal or metal-semiconductor compound layer and a semiconductor with an insulating layer. It's about doing.

[Summary of the invention]

The drawback (1) mentioned above is that as a result of making the diffusion layer shallow to reduce the short channel effect, leakage current increases due to defects and trace amounts of metal diffusion due to the reaction between the electrode and the diffusion layer, which were not a problem in the past. It is something. Therefore, by providing an insulating layer between the metal or compound layer and the semiconductor substrate, increase in leakage current can be suppressed. (2) In order to prevent a decrease in hot carrier resistance, the electric field at the drain end may be lowered. The most effective method for this is to make the concentration gradient of the impurity at the drain end gentle.

For this purpose, as shown in FIG. 1(a), the gate electrode 3
is processed to have a trapezoidal cross section, and using the gate electrode 3 as a mask, ions of an element 4 such as oxygen, nitrogen, or carbon that reacts with the semiconductor substrate material to form an insulator are implanted. The implanted elements are implanted deeply into the substrate in areas where there is no gate electrode, and are implanted shallowly under the electrodes according to the shape of the sidewalls. After that, if arsenic, phosphorus, or boron 7 is implanted or diffused, trace impurities such as oxygen, nitrogen, and carbon are distributed near the surface at the drain end, so that the concentration gradient of the diffusion layer can be made gentle. Thereafter, by replacing the region into which the element forming the insulator is deeply implanted with a metal-semiconductor compound layer 9, the resistance of the source, drain, etc. can be reduced. In addition, the impurity diffusion layer that becomes the source and drain contacts the channel region only near the channel surface, and the other parts are covered with an insulating film formed by ion implantation, so the channel region of the depletion layer It is possible to suppress the spread and reduce the short channel effect.

Next, the soft error caused by α rays shown in (3), which is a drawback of the conventional structure, is difficult to occur because the bonding layer is covered with an insulating film. As shown in (4) above, Si semiconductor MO3
In VLSI, signal delays due to junction capacitance formed between a diffusion layer and a substrate have become significant.

However, if a Si oxide or nitride layer is provided between these,
Capacity can be reduced to a fraction of the conventional capacity. This is because the dielectric constant of these insulating films is a few times lower than that of Si.

Although the case where the insulating film is formed by ion implantation has been described above, as shown in FIG. 2, an insulating layer having exactly the same effect can be formed without using the ion implantation method.

Note that conventional MOS transistors are formed on an insulating substrate, so-called SOI (Semiconductor on
Insulator) structures have been widely studied. However, with this method, it is difficult to form a high-quality single crystal on an insulating layer, and characteristics equivalent to those of an MO8 transistor formed in a single-crystal Si substrate have not yet been obtained. Further, since the channel region is also located on the insulating layer, it is easily influenced by external influences, and the potential becomes unstable, resulting in unstable characteristics.

Therefore, it is preferable to have a structure in which the channel region is in direct contact with the semiconductor substrate or is provided within the substrate, and only the bonding layer is covered with an insulating layer.

[Embodiments of the invention]

Example 1 As shown in FIG. 1(a), a p-type (100) Si substrate 1
A gate oxide film 2 with a thickness of 20 nm is formed on a predetermined region of the gate oxide film 2, and polycrystalline Si containing phosphorus is formed on the gate oxide film 2, which is then processed by dry etching to have a trapezoidal cross section. Next, using this electrode as a mask, 2×10 ions of oxygen 4 were implanted at 120 K e V in a length of 70 m, and then heat treatment was performed at 1000° C. for 30 minutes in a nitrogen atmosphere. Next, 5iOz around the gate electrode
After removing the single crystal Si substrate to expose the single crystal Si substrate, it was oxidized again in an oxidizing atmosphere containing moisture. At this time, even if a thick oxide film 6 of 200 nm and 8 degrees is formed on the polycrystalline portion, the single crystal Si surface will only be formed with a thickness of several tens of mmPj. After removing the SiOz film on the single crystal Si surface again.

W was deposited to a thickness of 50 mm, followed by heat treatment at 750°C for 30 minutes in a hydrogen atmosphere to form silicide only on the exposed Si single crystal, and unreacted W on the SiO12 was removed with hydrogen peroxide to form silicide 9. 6th order As with only part remaining
Implant a 70m silicide layer at 80 K eV and then 950°C.

When the heat treatment was performed in a nitrogen atmosphere for 30 minutes, As was diffused in the silicide, and an impurity diffusion layer 8 having a gently sloped concentration gradient was formed only at the end portions that would become the source and drain. In the MOS)-transistor obtained in this way, since the impurity junction shoulder part of the conventional method is composed of silicide, its resistance is low even when used as a wiring, about one order of magnitude higher than that when it is formed only with an impurity diffusion layer. A low sheet resistance of 4Ω/hole was obtained.

Furthermore, since the drain end is shallow, the short channel effect is improved as shown in FIG. 3 (compared to the conventional method). Furthermore, since the impurity concentration distribution at the drain end became gentle, the time required for the threshold voltage to change by a certain amount due to hot carriers, so-called lifetime, became longer by about 1.5 to 2.0 orders of magnitude. In addition, even when the pure AQ electrode 11 was used, the leakage current of the diffusion layer was 10'''1 sA or less at an applied voltage of 20 V, and good characteristics were obtained.

Example 2 Example 2 of the present invention will be described using FIG. 2.

The steps up to the formation of the gate electrode are the same as in Example 1. However, as shown in FIG. 2(a), the ends of the electrodes were processed to have as little slope as possible. Note that the 5iOz film 14 was used as a mask in processing the gate electrode. Next, chemical vapor deposition (CVD)
SiOx film 15 is deposited to a thickness of 0.3 pm using the
After deposition, this 5iOz15 was left only on the side walls of the gate electrode using an anisotropic dry etching technique (second
Figure (b)). Next, as shown in FIG. 2(c), the Si substrate 1 exposed around the gate electrode 3 is etched to a depth of 0.1 μm using the anisotropic etching technique again.
A Si nitride film 16 was deposited to a thickness of 0.2 μm using the VD method, and anisotropic etching was performed to leave the Si nitride film 16 on the side walls of the Si substrate and the side walls of the gate electrode. Using a directional etching technique, the exposed portion of the Si substrate is etched by 0.5 μm, and then the exposed portion of the Si substrate is oxidized in an oxidizing atmosphere containing moisture to form an etching layer of about 0.4 μm as shown in Figure 2(d).
A 5iOz5 film with a thickness of m was formed. After this.

The Si nitride film 16 on the side wall portion was removed with hot phosphoric acid.

Subsequently, as shown in FIG. 2(e), polycrystalline 5i17 containing phosphorus was formed.

At this time, the polycrystal 5iL7 in the grooved region is depressed as shown in the figure. When photoresist 18 is applied to the entire surface of the wafer in this state, the resist film thickness will be thicker in the recessed areas than in the flat areas. Next, etching is performed in Ar plasma until the resist on the flat portions is removed, leaving only the recessed portions of the resist 18.

Using this resist 18 as a mask, the polycrystal 5i17 was etched, leaving polycrystalline Si only in the portions that would become the source and drain, as shown in 21M(f).

Next, the resist 18 is removed and heat treatment is performed at 900° C. for 30 minutes, whereby phosphorus in the polycrystalline Si is diffused into the Si substrate at the source and train ends, forming an impurity diffusion layer 8 with a gently sloped concentration gradient. did it.

Thereafter, 80 nm 4+ of Ti was deposited and heat treated in a nitrogen atmosphere at 680° C. to convert the polycrystalline Si into Ti silicide 9 as shown in FIG. 2(g). Note that unreacted Ti was removed using an etching solution. After this, the interlayer insulating film 1.0. AQ electrode 11. A passivation film 12 was formed, and a MOS transistor was formed. According to this embodiment, the same effects as in embodiment 1 are obtained, and the source and
Since the drain is made of Ti silicide, the resistance can be further reduced to one-half.

[Effects of the Invention] According to the present invention, it is possible to reduce the short channel effect, junction layer leakage, junction layer capacitance and resistance of a MOS transistor, and to obtain a semiconductor device that is resistant to hot carriers and soft errors.

In the embodiments of the present invention, only the case of a polycrystalline Si gate electrode is shown, but it can also be applied to a MOS type semiconductor device having a gate electrode of a high-melting point metal such as tungsten or molybdenum, or a gate electrode in which silicide and polycrystalline Si are stacked. Needless to say, it can also be applied.

[Brief explanation of drawings]

FIGS. 1 and 2 are process diagrams showing embodiments of the present invention, and FIG. 3 is a diagram showing the effects of the present invention. DESCRIPTION OF SYMBOLS 1...Si substrate, 2...gate oxide film, 3...gate electrode, 4...0. C, N, etc. implanted ions, 5...
Insulator layer, 6... Gate electrode coating Si0g film, 7...
- Implanted ions such as As and P, 8... Slowly gradient concentration impurity diffusion layer, 9... Silicide layer, 10... Interlayer insulating film, 11... An electrode, 12... Passivation film, 13... Isolation between elements S i Oz, 14-... 5jO2 for gate electrode processing, film, 15... Side wall 5iOz
l! ll, 16... sidewall nitride film, 17... polycrystalline ¥
1 Country ↓ Jar ↓ ↓ ↓4 Figure Z (C) (
1) (C) ('r) (I)

Claims (1)

[Claims] 1. A connecting portion between a metal and a semiconductor in a semiconductor device, or
1. A semiconductor device comprising a metal-semiconductor compound layer or a portion composed of the compound and an impurity diffusion layer provided on an insulating layer. 2. The semiconductor device according to claim 1, characterized in that part or all of the lower and side surfaces of the compound and impurity diffusion layer are covered with an insulating layer. 3. The semiconductor device according to claim 1 or 2, wherein the insulating layer is provided within a semiconductor substrate of the semiconductor device.