JPS62143469A - Thin-film transistor - Google Patents
Thin-film transistorInfo
- Publication number
- JPS62143469A JPS62143469A JP60282801A JP28280185A JPS62143469A JP S62143469 A JPS62143469 A JP S62143469A JP 60282801 A JP60282801 A JP 60282801A JP 28280185 A JP28280185 A JP 28280185A JP S62143469 A JPS62143469 A JP S62143469A
- Authority
- JP
- Japan
- Prior art keywords
- gate electrode
- shielding film
- light shielding
- film transistor
- data line
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims description 27
- 239000010408 film Substances 0.000 claims description 53
- 239000004065 semiconductor Substances 0.000 claims description 12
- 239000000758 substrate Substances 0.000 claims description 5
- 239000004020 conductor Substances 0.000 claims description 3
- 238000010030 laminating Methods 0.000 claims 1
- 230000007423 decrease Effects 0.000 abstract description 7
- 239000002184 metal Substances 0.000 abstract description 4
- 229910052751 metal Inorganic materials 0.000 abstract description 4
- 238000010276 construction Methods 0.000 abstract 1
- 239000011159 matrix material Substances 0.000 description 11
- 230000000694 effects Effects 0.000 description 3
- 239000004973 liquid crystal related substance Substances 0.000 description 3
- CURLTUGMZLYLDI-UHFFFAOYSA-N Carbon dioxide Chemical compound O=C=O CURLTUGMZLYLDI-UHFFFAOYSA-N 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 229910004205 SiNX Inorganic materials 0.000 description 1
- 229910002092 carbon dioxide Inorganic materials 0.000 description 1
- 239000001569 carbon dioxide Substances 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136218—Shield electrodes
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Liquid Crystal (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は例えば液晶フラットディスプレイのスイッチン
グ素子に用いて好適な薄膜トランジスタに関するもので
ある。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a thin film transistor suitable for use as a switching element of, for example, a liquid crystal flat display.
近年、陰極線管（ＣＲＴ）に代る表示装置として、種々
のフラットディスプレイの開発がさかんに行われている
。その代表的なディスプレイの一つにドツトマトリクス
液晶ディスプレイがある。このドツトマトリクス液晶デ
ィスプレイの場合、表示できる情報量を増すため、ある
いは画像の精細度を増すためにドツト（画素）の数を増
すと、クロストークと呼ぶ現象が生じて画像のコントラ
ストが著しく悪化する。これを防止するためには、１つ
１つの画素に薄膜トランジスタ等の能動素子を付設した
、いわゆるアクティブマトリクス方式が有効である。In recent years, various flat displays have been actively developed as display devices to replace cathode ray tubes (CRTs). One of the representative displays is the dot matrix liquid crystal display. In the case of this dot matrix liquid crystal display, when the number of dots (pixels) is increased in order to increase the amount of information that can be displayed or to increase the definition of the image, a phenomenon called crosstalk occurs and the contrast of the image deteriorates significantly. . In order to prevent this, a so-called active matrix method in which an active element such as a thin film transistor is attached to each pixel is effective.
なお、この種のディスプレイの構成は、例えば日経エレ
クトロニクス１９８４年９月１０日号Ｐ２１１に記載さ
れている。The configuration of this type of display is described, for example, in Nikkei Electronics, September 10, 1984 issue, page 211.
このよう々アクティブマトリクスディスプレイにおいて
は、各画素に、付設された薄膜トランジスタのスイッチ
機能を利用し、スイッチＯＮのとき画像情報を書き込み
、スイッチ０ＦＦｔ７）ときその情報を保持させるよう
にしたものである。In this way, in the active matrix display, the switch function of the thin film transistor attached to each pixel is used to write image information when the switch is ON, and to retain that information when the switch is OFF.
ところで、この薄膜トランジスタにおいて、半導体膜と
して、ａ−８ｉのように光導電性の大きい半導体を用い
た場合は、半導体膜への光照射の有無によってソース、
ドレイン電極間の抵抗値が異る。アクティブマトリクス
の場合は、特にＯＦＦ抵抗の変化が問題となり、光が照
射されてＯＦＦ抵抗が低下すると、画素に書き込まれた
情報の保持が困難となる。By the way, in this thin film transistor, when a semiconductor with high photoconductivity such as a-8i is used as the semiconductor film, the source and
The resistance value between the drain electrodes is different. In the case of an active matrix, changes in OFF resistance are particularly problematic, and when the OFF resistance decreases due to irradiation with light, it becomes difficult to retain information written in pixels.
本発明の目的はＯＦＦ抵抗の低下を確実に防止すること
ができる薄膜トランジスタを提供することにある。An object of the present invention is to provide a thin film transistor that can reliably prevent a decrease in OFF resistance.
本発明の他の目的は、ＯＦＦ抵抗を低下させることによ
って生じる浮遊容量の発生を防止した薄膜トランジスタ
を提供することにある。Another object of the present invention is to provide a thin film transistor in which stray capacitance caused by lowering the OFF resistance is prevented from occurring.
本発明の一実施例によれば、遮光膜とゲート電極とを電
気的に接続し同電位とすることによシ、ＯＦＦ抵抗の低
下を確実に防止しかつ浮遊容量の発生を防止した薄膜ト
ランジスタが提供される。According to an embodiment of the present invention, a thin film transistor is provided in which a light shielding film and a gate electrode are electrically connected and have the same potential, thereby reliably preventing a decrease in OFF resistance and preventing the generation of stray capacitance. provided.
次に図面を用いて本発明の実施例を詳細に説明する。 Next, embodiments of the present invention will be described in detail using the drawings.
第１図は薄膜トランジスタを示す図であり、同図Ａは平
面図、同図Ｂは同図ＡのＩＢ−ＩＢ断面図である。これ
らの図において、１はガラス板などからなる絶縁基板、
２はＣｒ、ＩＴＯ等の導電性材料で形成されたゲート電
極、３はＳ ％０＠ 、 Ｓ ｉＮｘ等からなる絶縁膜
、４け” Ｓｉ、ｐｏｌｙ ｓ、等からなる半導体
膜、５および６はＣ，、ＩＴＯ等の導電性材料で形成さ
れたソース電極およびドレイン電極である。FIG. 1 is a diagram showing a thin film transistor, in which FIG. 1A is a plan view and FIG. 1B is a sectional view taken along line IB--IB in FIG. In these figures, 1 is an insulating substrate made of a glass plate or the like;
2 is a gate electrode made of conductive material such as Cr or ITO; 3 is an insulating film made of S%0@, SiNx, etc.; 4 is a semiconductor film made of Si, polys, etc.; 5 and 6 are The source and drain electrodes are made of a conductive material such as carbon dioxide, ITO, or the like.
このような薄膜トランジスタは、ゲート電極２とソース
電極５との間に加える電界の大きさを変化させることに
よって、ソース電極５とドレイン電極６との間の電気抵
抗を変化させることができる。すなわち、スイッチング
機能をもたせることができる。In such a thin film transistor, the electric resistance between the source electrode 5 and the drain electrode 6 can be changed by changing the magnitude of the electric field applied between the gate electrode 2 and the source electrode 5. That is, it can have a switching function.
しかしながら、このような薄膜トランジスタをアクティ
ブマトリックスディスプレイに用いると、半導体膜４に
光が照射されてソース、ドレイン間のＯＦＦ抵抗が低下
し、画素に書舞込まれた情報の保持が困難とガることか
ら、ゲート電極２．ソース電極５及びドレイン電極６を
遮光性材料を用いて形成すると、基板１側から入射する
光に対しては第２図に斜線部Ａで示す半導体が露光し、
その反対側から入射する光に対しては第３図に斜線部Ｂ
に示す半導体が露光されることになる。However, when such a thin film transistor is used in an active matrix display, the semiconductor film 4 is irradiated with light and the OFF resistance between the source and drain decreases, making it difficult to retain information written in pixels. From the gate electrode 2. When the source electrode 5 and the drain electrode 6 are formed using a light-shielding material, the semiconductor shown by the shaded area A in FIG. 2 is exposed to light incident from the substrate 1 side.
For light incident from the opposite side, the shaded area B is shown in Figure 3.
The semiconductor shown in will be exposed.
このような問題を解決する手段として第４図Ａ。Figure 4A is a means to solve such problems.
Ｂに示すような薄膜トランジスタが提案されている。す
なわち、同図に示すようにゲート電極２の下に絶縁膜Ｔ
を介して半導体膜４を完全に覆う下部遮光膜Ｂを形成し
、ソース電極５及びドレイ／電極６の上には絶縁膜９を
介して上部遮光膜１０を形成する。この場合、絶縁膜７
，９を介在させる理由は、遮光膜８，１０を絶縁性材料
で形成することが困難なためであざ。A thin film transistor as shown in B has been proposed. That is, as shown in the figure, an insulating film T is formed under the gate electrode 2.
A lower light-shielding film B is formed to completely cover the semiconductor film 4 via an insulating film 9, and an upper light-shielding film 10 is formed on the source electrode 5 and the drain/electrode 6 with an insulating film 9 interposed therebetween. In this case, the insulating film 7
, 9 are interposed because it is difficult to form the light shielding films 8 and 10 from an insulating material.
このように構成される薄膜トランジスタは、基板１側及
びその反対側から入射する光に対して半導体膜４を遮光
でき、前述したＯＦＦ抵抗の低下を防止できる。The thin film transistor configured in this manner can shield the semiconductor film 4 from light incident from the substrate 1 side and the opposite side, and can prevent the above-mentioned decrease in OFF resistance.
しかしながら、このように構成される薄膜トランジスタ
では、ゲート電極２と下部遮光膜８との間およびソース
電極５及びドレイン電極６と上部遮光膜１０との間に浮
遊容量が発生し、スイッチング速度が低下するのみなら
ず、画素に誤った情報を書き込んだυ、ＯＦＦ時に情報
を保持できないといった問題が生じる。However, in the thin film transistor configured in this manner, stray capacitance occurs between the gate electrode 2 and the lower light shielding film 8 and between the source electrode 5 and drain electrode 6 and the upper light shielding film 10, reducing the switching speed. In addition, there arises a problem that υ writes incorrect information to a pixel, and the information cannot be retained when the pixel is turned off.
ところで、アクティブマトリックスにおいては、薄膜ト
ランジスタは通常第５図Ａ、Ｂに示すような配置に形成
される。すなわち、データライン２′は横一列の薄膜ト
ランジスタのゲート電極２に共通となるように配線され
、信号ライン５′は縦一列の薄膜トランジスタのゲート
電極５に共通となるように配線される。ドレイン電極４
は各画素電極１１に個別に接続され、絶縁膜３はゲート
電極２゜ソース電極５の電極端子部２ａ、Ｓｍを除く全
面に形成される。また半導体膜４は島状に形成される。Incidentally, in an active matrix, thin film transistors are usually formed in the arrangement shown in FIGS. 5A and 5B. That is, the data line 2' is wired so as to be common to the gate electrodes 2 of the thin film transistors arranged horizontally, and the signal line 5' is wired so as to be common to the gate electrodes 5 of the thin film transistors arranged vertically. drain electrode 4
are individually connected to each pixel electrode 11, and the insulating film 3 is formed over the entire surface except for the electrode terminal portions 2a and Sm of the gate electrode 2 and the source electrode 5. Further, the semiconductor film 4 is formed in an island shape.
そして、ゲート電極端子部２ａに信号を入力し、横一列
の薄膜トランジスタがオン状態のときにソース電極５か
ら各画素１１に画像情報を書き込む機能を有してる。It has a function of inputting a signal to the gate electrode terminal portion 2a and writing image information from the source electrode 5 to each pixel 11 when the thin film transistors in a horizontal row are in an on state.
このようなアクティブマトリックスに本発明による薄膜
トランジスタを適用する場合には、薄膜トランジスタは
第６図に示すように下部遮光膜８および上部遮光膜１０
がゲート１！極２のデータラインτ側をほぼ覆う形状の
大きさに形成され、第７図に示すようにデータライン２
′上の絶縁膜３゜７．９にスルーホール１２を設けてこ
のスルーホール１２内に例えばＮｉ ＋ＴＩ 、ＡＬ、
Ｃ１、Ｍｏ等の導電性金属１３が形成されて下部遮光膜
８とデータライン１と上部遮光膜１０とが導電性金Ｍ１
３により電気的に接続されている。When applying the thin film transistor according to the present invention to such an active matrix, the thin film transistor has a lower light shielding film 8 and an upper light shielding film 10 as shown in FIG.
is gate 1! It is formed to a size that almost covers the data line τ side of pole 2, and as shown in FIG.
A through hole 12 is provided in the insulating film 3°7.9 on top of the insulating film, and in this through hole 12, for example, Ni + TI, AL,
A conductive metal 13 such as C1 or Mo is formed so that the lower light shielding film 8, the data line 1, and the upper light shielding film 10 are made of conductive gold M1.
It is electrically connected by 3.
このような構成によれば、下部遮光膜８および上部遮光
膜１０は常にゲート電極２．データライン２′と同電位
となるので、浮遊容量は全く発生しなくなる。また、こ
のような構成において、上部遮光膜１０はデータライン
２′に接続されて表面に露出する構成となるので、ノイ
ズ等の印加によりゲート電極２がオンされる恐れがある
が、このゲート電極２は図示しないが、電源ラインに接
続されているので、ノイズが印加されても容易に吸収さ
れる。さらにこのデータライン２′を電源ラインのアー
ス側として使用することができる。したがって、ゲート
電極２がオンされる心配は全くなくなる。また、下部遮
光膜８および上部遮光膜１０がゲート電極２のデータラ
イン２′側までカバーしているので、遮光性がさらに向
上できる。According to such a configuration, the lower light shielding film 8 and the upper light shielding film 10 are always connected to the gate electrode 2. Since it has the same potential as the data line 2', no stray capacitance is generated. In addition, in such a configuration, the upper light shielding film 10 is connected to the data line 2' and exposed on the surface, so there is a risk that the gate electrode 2 may be turned on due to the application of noise or the like. 2 is connected to the power supply line, although it is not shown, so that even if noise is applied, it is easily absorbed. Furthermore, this data line 2' can be used as the ground side of the power supply line. Therefore, there is no fear that the gate electrode 2 will be turned on. Further, since the lower light shielding film 8 and the upper light shielding film 10 cover the gate electrode 2 up to the data line 2' side, the light shielding property can be further improved.
第８図は本発明による薄膜トランジスタをアクティブマ
トリックスに適用した池の実施例を示す平面図であり、
前述の図と同一部分は同一符号を付しである。同図にお
いて、第７図と異なる点は、データライン端子部２＆上
に絶縁膜が介在しないことを利用してデータライン２′
の上下部に下部遮光膜８および上部遮光膜１０を形成し
、絶縁膜３゜７．９のないデータライン端子部２ａでゲ
ートラインτと接続されている。FIG. 8 is a plan view showing an embodiment of a pond in which the thin film transistor according to the present invention is applied to an active matrix.
The same parts as in the previous figures are given the same reference numerals. In this figure, the difference from FIG. 7 is that the data line 2' is
A lower light-shielding film 8 and an upper light-shielding film 10 are formed on the upper and lower portions of the data line terminal 2a, which is connected to the gate line τ at a data line terminal portion 2a without an insulating film 3°7.9.
このような構成においても、ゲート電極２は、データラ
イン端子部２＆において下部遮光膜８および上部遮光膜
１０と接続され、同電位となるので、浮遊容量が発生し
ないことになる。また、このような構成は、遮光膜のマ
スクパターンを変更するのみで、プロセスの変更が全く
ないので、極−めて容易にかつ簡単に製作することがで
きる。Even in such a configuration, the gate electrode 2 is connected to the lower light shielding film 8 and the upper light shielding film 10 at the data line terminal portion 2& and have the same potential, so that no stray capacitance is generated. Moreover, such a configuration can be manufactured extremely easily and simply because the only change is the mask pattern of the light shielding film, and there is no change in the process at all.
なお、前述した実施例においては、ゲート電極２の上下
部分にそれぞれ上部遮光膜１０および下部遮光膜８を設
け、これら両速光膜１０，８をゲート電極２と同電位と
なるように接続した場合について説明したが、本発明は
これに限定されるものではなく、上部遮光膜１０あるい
は下部遮光膜８の一方をゲート電極２と同電位となるよ
うに接続しても同様の効果が得られることは言うまでも
ない。In the above-mentioned embodiment, an upper light shielding film 10 and a lower light shielding film 8 were provided on the upper and lower parts of the gate electrode 2, respectively, and both of these light shielding films 10 and 8 were connected to be at the same potential as the gate electrode 2. Although the case has been described, the present invention is not limited to this, and the same effect can be obtained even if one of the upper light shielding film 10 or the lower light shielding film 8 is connected to have the same potential as the gate electrode 2. Needless to say.
以上説明したように本発明によれば、遮光膜とゲート電
極とを電気的に接続することにより、半導体膜が完全に
遮光されるので、ＯＦＦ抵抗の低下を確実に防止するこ
とができる。また、遮光膜と各電極との間に浮遊容量の
発生が皆無となるので、アクティブマトリックスディス
プレイに適用することにより、ＯＦＦ時の情報を保持す
ることが可能となるとともに、画素への誤情報の書き込
みを防止できるなどの極めて優れた効果が得られる。As described above, according to the present invention, the semiconductor film is completely shielded from light by electrically connecting the light shielding film and the gate electrode, so that a decrease in OFF resistance can be reliably prevented. In addition, since there is no stray capacitance between the light-shielding film and each electrode, by applying it to an active matrix display, it is possible to retain information when it is off, and to prevent erroneous information from being transmitted to pixels. Extremely excellent effects such as being able to prevent writing can be obtained.
第１図Ａは薄膜トランジスタを示す平面図、第１図Ｂは
同図ＡのＩＢ−ＩＢＢ断面図第２図および第３図は半導
体膜が露光される状態を示す平面図、第４図Ａは遮光膜
を設けた薄膜トランジスタを示す平面図、第４図Ｂは同
図Ａの４Ｂ−４Ｂ断面図、第５図Ａは薄膜トランジスタ
をアクティブマトリックスに適用する場合を説明する平
面図、第５図Ｂは同図Ａの５ Ｂ−５Ｂ断面図、第６図
は本発明による薄膜トランジスタを説明するための平面
図、第７図Ａは本発明による薄膜トランジスタをアクテ
ィブマトリックスに適用した一実施例を示す平面図、第
７図Ｂは同図Ａの７ Ｂ−７Ｂ断面図、第８図は本発明
による薄膜、トランジスタをアクティブマ） ＩＪラッ
クス適用した他の実施例を示す平面図である。
１・・・・絶縁基板、２・・・・ゲート電極、τ・・・
φデータライン、２ａ・・・・端子部、３・・・・絶縁
膜、４・・・・半導体膜、５・・φ・ソース電極、６・
・φ・ドレイン電極、７・・・・絶縁膜、８・・・・下
部遮光膜、９・・・・絶縁膜、１０・・・・上部遮光膜
、１１・・・・画１ｔｍ、１２Φ・・・スルーホール、
１３＃・・・導電性金属。
代理人 弁理士 小 川 勝 男７パ
（、
第１図Ａ 第１図Ｂ
第２図 第３図
第５図Ａ
第６図
第７図Ａ
第７図ＢFIG. 1A is a plan view showing a thin film transistor, FIG. 1B is a sectional view taken along IB-IBB in FIG. FIG. 4B is a plan view showing a thin film transistor provided with a light-shielding film, FIG. 4B is a sectional view taken along line 4B-4B of FIG. FIG. 6 is a plan view for explaining the thin film transistor according to the present invention; FIG. 7 A is a plan view showing an embodiment in which the thin film transistor according to the present invention is applied to an active matrix; FIG. 7B is a sectional view taken along line 7B-7B in FIG. 1...Insulating substrate, 2...Gate electrode, τ...
φ data line, 2a...terminal section, 3...insulating film, 4...semiconductor film, 5...φ source electrode, 6...
・φ・Drain electrode, 7: Insulating film, 8: Lower light shielding film, 9: Insulating film, 10: Upper light shielding film, 11: Image 1tm, 12Φ・・Through hole,
13#... Conductive metal. Agent Patent Attorney Masaru Ogawa 7P (Figure 1A Figure 1B Figure 2Figure 3Figure 5A Figure 6Figure 7A Figure 7B
Claims (1)
イン電極と遮光膜とを積層形成してなる薄膜トランジス
タにおいて、前記遮光膜は導電性材料で形成されかつゲ
ート電極に接続されることを特徴とした薄膜トランジス
タ。A thin film transistor formed by laminating a gate electrode, a semiconductor film, a gate electrode, a drain electrode, and a light shielding film on an insulating substrate, characterized in that the light shielding film is formed of a conductive material and is connected to the gate electrode. Thin film transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60282801A JPS62143469A (en) | 1985-12-18 | 1985-12-18 | Thin-film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP60282801A JPS62143469A (en) | 1985-12-18 | 1985-12-18 | Thin-film transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62143469A true JPS62143469A (en) | 1987-06-26 |
Family
ID=17657265
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP60282801A Pending JPS62143469A (en) | 1985-12-18 | 1985-12-18 | Thin-film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62143469A (en) |
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01177020A (en) * | 1987-12-28 | 1989-07-13 | Sharp Corp | Active matrix display device |
| JPH01277820A (en) * | 1988-04-30 | 1989-11-08 | Sharp Corp | Thin-film transistor |
| US4894690A (en) * | 1987-04-22 | 1990-01-16 | Alps Electric Co., Ltd. | Thin film transistor array incorporating a shorted circuit bypass technique |
| JPH0534674A (en) * | 1991-07-29 | 1993-02-12 | Sanyo Electric Co Ltd | Liquid crystal projector |
| EP0725301A1 (en) * | 1995-01-31 | 1996-08-07 | Nec Corporation | Active matrix liquid crystal display device with light shielding electrode connected to an independent potential |
| EP0766120A2 (en) * | 1995-09-27 | 1997-04-02 | Sharp Kabushiki Kaisha | Active matrix substrate and display device incorporating the same |
| US5879959A (en) * | 1997-01-17 | 1999-03-09 | Industrial Technology Research Institute | Thin-film transistor structure for liquid crystal display |
| EP1180716A2 (en) * | 2000-08-10 | 2002-02-20 | Sony Corporation | Thin film semiconductor device and liquid crystal display unit, and fabrication methods thereof |
| JP2004247704A (en) * | 2002-08-30 | 2004-09-02 | Sharp Corp | Tft array substrate, liquid crystal display device, their manufacturing method and electronic equipment |
| US7918943B2 (en) | 2005-01-14 | 2011-04-05 | Hoshizaki Denki Kabushiki Kaisha | Dish washer |
| CN104216190A (en) * | 2014-08-28 | 2014-12-17 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method thereof and display device |
| US9059216B2 (en) | 2000-12-11 | 2015-06-16 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device, and manufacturing method thereof |
-
1985
- 1985-12-18 JP JP60282801A patent/JPS62143469A/en active Pending
Cited By (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4894690A (en) * | 1987-04-22 | 1990-01-16 | Alps Electric Co., Ltd. | Thin film transistor array incorporating a shorted circuit bypass technique |
| JPH01177020A (en) * | 1987-12-28 | 1989-07-13 | Sharp Corp | Active matrix display device |
| JPH01277820A (en) * | 1988-04-30 | 1989-11-08 | Sharp Corp | Thin-film transistor |
| JPH0534674A (en) * | 1991-07-29 | 1993-02-12 | Sanyo Electric Co Ltd | Liquid crystal projector |
| EP0725301A1 (en) * | 1995-01-31 | 1996-08-07 | Nec Corporation | Active matrix liquid crystal display device with light shielding electrode connected to an independent potential |
| EP0766120A2 (en) * | 1995-09-27 | 1997-04-02 | Sharp Kabushiki Kaisha | Active matrix substrate and display device incorporating the same |
| EP0766120A3 (en) * | 1995-09-27 | 1998-07-08 | Sharp Kabushiki Kaisha | Active matrix substrate and display device incorporating the same |
| US5879959A (en) * | 1997-01-17 | 1999-03-09 | Industrial Technology Research Institute | Thin-film transistor structure for liquid crystal display |
| EP1180716A2 (en) * | 2000-08-10 | 2002-02-20 | Sony Corporation | Thin film semiconductor device and liquid crystal display unit, and fabrication methods thereof |
| EP1180716A3 (en) * | 2000-08-10 | 2003-10-01 | Sony Corporation | Thin film semiconductor device and liquid crystal display unit, and fabrication methods thereof |
| US9059216B2 (en) | 2000-12-11 | 2015-06-16 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device, and manufacturing method thereof |
| US9666601B2 (en) | 2000-12-11 | 2017-05-30 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device, and manufacturing method thereof |
| US10665610B2 (en) | 2000-12-11 | 2020-05-26 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device, and manufacturing method thereof |
| JP2004247704A (en) * | 2002-08-30 | 2004-09-02 | Sharp Corp | Tft array substrate, liquid crystal display device, their manufacturing method and electronic equipment |
| JP4615197B2 (en) * | 2002-08-30 | 2011-01-19 | シャープ株式会社 | Manufacturing method of TFT array substrate and manufacturing method of liquid crystal display device |
| US7918943B2 (en) | 2005-01-14 | 2011-04-05 | Hoshizaki Denki Kabushiki Kaisha | Dish washer |
| CN104216190A (en) * | 2014-08-28 | 2014-12-17 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method thereof and display device |
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