JPS62142348A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To obtain a semiconductor memory cell device characterized by high speed, low power consumption and large capacity, by performing the selection of memory cells in two stages for prepositioned word lines and divided word lines, and arranging the prepositioned lines and the divided word lines alternately in parallel. CONSTITUTION:Prepositioned word lines 15 are arranged in parallel with word lines 3a-3c as divided word lines in the same direction. When a memory cell in, e.g., a memory cell group 1a is selected, the row address data in the memory cell group 1a to be accessed is decoded by a row decoder 4, and one prepositioned word line 15 is activated. When a selecting signal is applied to a memory-cell-group selecting line 14a, an AND gate 16a is opened and a word line 3a is a activated. A column current flows only to a column in the selected memory cell group 1a through a bit line (not shown) from a power source (not shown).

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device that can improve access time and reduce power consumption.

[Conventional technology]

FIG. 2 is a block diagram showing a conventional semiconductor memory device. In the figure, 1 is a memory cell arranged in a matrix, the detailed circuit of which is shown in FIG. 2, 2a and 2b are a pair of complementary bit lines, and 3 is a memory cell on the same row when selected. A word line for activating cell 1, 4 a row decoder for decoding row address information, 5 a row address signal line, 6a and 6b bit line loads connected to the bit lines 2a and 2b, respectively, and 7 a power supply terminal. be.

In the memory cell l shown in FIG. 3, 8a and 8b are load elements constituted by MO3I transistors, resistors, etc., 9a and 9b are inverter transistors, and 10
a and 10b are access transistors, lla and llb are store nodes of memory cell l.

Next, the operation of the semiconductor memory device having the above configuration will be described, for example, when store nodes Ila and llb are written to the "H" level and the "L" level, respectively.

First, in the case of reading, when the address information of the cell to be read is inputted to the address signal line 5, the desired word line 3 is activated through the row decoder 4. Then, when this word line 3 is activated, the access transistor 10b storing the '1,'' level becomes conductive. Therefore, from the power supply terminal 7, the bit vA load 6b, the bit line 2b, the access transistor 10b, A current flows through the path of inverter transistor 9b and can be read out.

In a semiconductor memory device with this configuration, all memory cells on the same device are activated, so current flows from the power supply to the memory cells in all columns, and when configuring a large capacity static RAM with many columns, the current consumption becomes larger. Therefore, in order to reduce current consumption, a semiconductor memory device shown in FIG. 4 has been proposed. In this case, the row decoder 4 is placed in the center of the memory cell brain, the word line is divided into the left word line 3a and the right word line 3b, and only the word line of the selected memory cell group of the left and right memory cell groups is used. When activated, a current bus is generated in only half of all the columns. Note that 12a and 12b are AND gates that select the left word line 3a or the right word line 3b, respectively, and 13a and 13
b is a gate signal line that opens the AND gates 12a and 12b, respectively.

Next, FIG. 5 is a layout diagram showing a conventional semiconductor memory device constructed based on the idea of FIG. 4.

In this case, row decoders 4a and 4b are arranged in multiple columns,
The word lines 3a to 3d are divided into multiples thereof to reduce the number of DC current paths.

[Problem that the invention seeks to solve]

However, conventional semiconductor memory devices require a large number of row decoders. For this reason, there were drawbacks such as an increase in chip area and a loss in speed performance and yield.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a high-speed, low-power, large-capacity semiconductor memory device.

[Failure to solve the problem]

In order to achieve such an object, the present invention provides a plurality of memory cell groups in which a memory cell array in which memory cells are arranged in a 71-x shape is divided and arranged in the column direction, and a plurality of memory cell groups in each of the plurality of memory cell groups. a memory cell group selection line provided correspondingly to select a specific one of each memory cell group;
a row decoder for decoding row address information of a memory cell group to be accessed; a preword line connected to the output terminal of the row decoder and arranged across the plurality of memory cell groups; and each of the plurality of memory cell groups. The front word line and the divided word line are connected in parallel with each other. This is how it is placed.

[Operation] The semiconductor memory device according to the present invention has high speed and low power consumption.

〔Example〕

FIG. 1 is a block diagram showing an embodiment of a semiconductor memory device according to the present invention. As an example, it shows a case where three memory cell groups 1a, lb and 1c are arranged in the column direction. In the same figure, 14a, 14b and 14
15 is a memory cell group selection line for selecting the memory cell group 1a-1c, and 15 is a word line 3a to 3a as divided word lines.
Preword line 16 arranged in parallel in the same direction as 3c.
Reference numerals a, 16b and 16c are AND gates whose input terminals are connected to the front word line 15 and the memory cell group selection lines 14a-140, respectively, and whose output terminals are connected to the word lines 3a-3c, respectively.

Next, the operation of the semiconductor memory device with the above configuration will be explained. First, when selecting a memory cell in the memory cell group la, for example, the row address information of the memory cell group la to be accessed is decoded by the row decoder 4, and one of the front word lines 15 is activated. Then, memory cell group selection′
When a selection signal is added to gAl 4 a, AND gate 1
6a opens and activates word line 3a. therefore,
A column current flowing into the memory cell group 1a from a power supply (not shown) through a bit line (not shown) flows only in the columns in the selected memory cell group la.

Note that although the selection of the memory cells in the memory cell group la has been described above, it goes without saying that the same can be done for the other memory cell groups lb and ICs. moreover,
Although the case where the memory cell group is divided into three cells has been described, it goes without saying that the same effect can be achieved even if the memory cell group is divided into N cells (N≧2). Furthermore, if only the pre-word line 15 is made of a low-resistance material, even if the word line has a somewhat high resistance, the word line has a short length and therefore has a small capacitance, and the memory cells can be accessed at high speed. Also, and gates 16a to 16C
Since the circuit has two input terminals and one output terminal, the circuit configuration is simple, and the increase in chip area can be ignored. Furthermore, it goes without saying that the row decoder 4 may be placed at the center of the chip or at the edge of the chip.

As described above in detail, according to the semiconductor memory device according to the present invention, row selection is performed hierarchically such that memory cell selection is performed in two stages: 1111 word line and word line. Since the number of columns with direct current paths in the columns can be reduced, it is possible to construct a semiconductor memory device for personal use that is high-speed and consumes low power.

〔Effect of the invention〕

As explained above, in the present invention, the selection of memory cells is performed in two stages: front word lines and divided word lines, so that the number of columns with DC current paths can be reduced. This has the advantage that a high-speed, low-power, large-capacity semiconductor memory device can be obtained.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a semiconductor memory device according to the present invention, FIG. 2 is a block diagram showing a conventional semiconductor memory device, and FIG. 3 is a detailed circuit diagram of the memory cell shown in FIG. FIG. 4 is a block diagram showing another conventional semiconductor memory device, and FIG. 5 is a layout diagram showing another conventional semiconductor memory device. 1a-1c...Memory cell group, 3a-3C...Word line, 4...Row decoder, 143-14G...Memory cell selection line, 15... Front word line, 16a-16
C...and gate.

Claims (1)

[Claims] a plurality of memory cell groups in which a memory cell array in which memory cells are arranged in a matrix is divided and arranged in a column direction;
a memory cell group selection line provided corresponding to each of the plurality of memory cell groups to select a specific one of each memory cell group; and a row decoder to decode row address information of the memory cell group to be accessed. , a preword line connected to the output terminal of the row decoder and arranged across the plurality of memory cell groups, and a selection of the memory cell group selection line provided corresponding to each of the plurality of memory cell groups. A semiconductor memory device comprising a divided word line activated based on a signal and an output signal of the prefix word line, and wherein the prefix word line and the split word line are arranged in parallel with each other. .