JPS62141740A - Manufacture of semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To form a metal wiring and an interlayer insulating film free from void and to make them flat by a method wherein, after cavity-shaped grooves for wiring are formed in an insulating film, a thin semiconductor or metal film is formed on the side surfaces of the grooves, and a gas containing metal is made to react to make the metal grow selectively only in the cavity-shaped grooves. CONSTITUTION:After cavity-shaped grooves 2a and 2b for wiring metal are formed, polycrystalline silicon 3 is deposited on the whole surface by a CVD method. Next, the polycrystalline silicon film 3 on the bottom surfaces of the cavity-shaped grooves 2a and 2b and on the surface of an insulating film 1 is removed by using anisotropic dry etching. Since the etching goes only in the vertical direction, the polycrystalline silicon film 3 is left on the side surfaces of the grooves 2a and 2b. Then, a gas prepared by diluting WF6 with Ar is made to react with the polycrystalline silicon film 3. In other words, tungsten W5a and W5b is made to grow selectively only on the side surfaces of the cavity-shaped grooves respectively by using the reducing reaction of silicon. On the occasion, W does not grow on the surface of the insulating film 1. Next, W is made to grow by using the reducing reaction of hydrogen. Since hydrogen has a property that it is adsorbed only on the surface of metal to ionize same, the above-mentioned reducing reaction of hydrogen grows, on this occasion, only from the side surfaces of the grooves 2a and 2b, while the grooves 2a and 2b are buried completely with W.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a method of manufacturing a high-density, large-scale integrated semiconductor integrated circuit having fine multilayer wiring.

2. Description of the Related Art Conventionally, when forming multilayer interconnections, a method has been used in which a flattening insulating film and an interlayer insulating film are entirely deposited after metal interconnections are formed. This and Figure 8.

This will be explained based on FIG. In FIG. 8, 9 is an insulating film;
10a, 10b, and 10C are metal wirings. Here 1
The metal wiring spacing of 0&, 10b is submicron. In FIG. 9, even if the interlayer insulating film 11 is deposited over the entire surface by, for example, a plasma method with good step coverage, the metal wiring 11 with submicron spacing as shown in the same figure.
4.10b is not completely filled in, and a cavity called a void 12 is created.

Problems to be Solved by the Invention When such cavities occur, the interlayer film 11 becomes partially thin, resulting in a drop in dielectric strength and reliability problems. Another method for depositing a planarizing insulating film is bias sputtering, but this method takes time to form and causes damage, which poses major problems in practical use.

As described above, with conventional methods, it is difficult to manufacture high-density, large-scale integrated semiconductor integrated circuits having fine multilayer wiring.

The present invention has been made in view of the drawbacks of the conventional art, and an object of the present invention is to form and planarize void-free metal wiring and living room insulating films using a simple method in multilayer wiring with microscopic measurements.

Means for Solving the Problems In order to solve the above-mentioned problems, the present invention forms concave grooves for wiring in an insulating film, and then forms a thin semiconductor film or a thin metal film on the side surfaces of the grooves, so that the grooves do not contain metal. This method selectively grows metal only in the concave grooves by reacting with gas.

Operation According to the present invention, wiring metal and interlayer insulating film of submicron multilayer wiring can be easily planarized, and highly reliable multilayer wiring can be obtained.

Embodiment FIG. 1 shows an embodiment of the present invention, and is a cross-sectional view in which wiring metal and planarizing insulating films having submicron intervals are formed. In the figure, 1 is a flattening insulating film, 51L,
5b is a wiring metal having submicron intervals, and is completely flattened without generating voids. 2nd below
The manufacturing method of this embodiment will be explained based on FIGS.

In FIG. 2, 1 is an insulating film, and 2a and 2b are concave grooves for wiring metal. The spacing between the grooves 2a and 2b is submicro//. In FIG. 3, polycrystalline silicon 3 is deposited over the entire surface by CVD. A thin layer is also deposited on the bottom and side surfaces of the grooves 2&, 2b. Next, in FIG. 4, the polycrystalline silicon film 3 on the bottom surfaces of the concave grooves 2a and 2b and on the surface of the insulating film 1 is removed using anisotropic dry etching.

Since etching only progresses in the vertical direction, groove 2-1
．． The polycrystalline silicon film 3 remains on the side surface of 2-2. In FIG. 6, a gas prepared by diluting WF6 (tungsten hexafluoride) with argon (argon) is reacted with the polycrystalline silicon film 3. As shown in FIG. That is, 2WF6+38i → 2W+3SiF.

Tungsten (W) sa and 5bt are selectively grown only on the side surfaces of the concave groove using the silicon ring element reaction. At this time, W does not grow on the surface of the insulating film 1. This reaction proceeds until the polycrystalline silicon film 3 disappears. The thickness of W is approximately several hundred people.

Next, in FIG. 6, a gas containing WF6+H2 (hydrogen) is reacted. That is, W is grown using the hydrogen ring reaction of WF6+3H2→W-1-6HF↑. At this time, since hydrogen has the property of being adsorbed and ionized only on the metal surface, the above hydrogen ring reaction occurs in the groove 21L.

Grooves 2a and 2b are completely formed by growing only from the side of groove 2b.
Filled with This hydrogen ring reaction is completely a surface reaction, so
Growth is isotropic and voids do not grow.

Therefore, as shown in FIG. 6, the metal interconnections having submicron intervals and the planarization insulating film 1 filling the gaps are completely planarized without generating voids. FIG. 7 shows an example applied to a two-layer wiring, where 6 is a base insulating film, 7 is a flattening insulating film, sa and ab are first-layer metal wirings, 1' is an interlayer insulating film, and 5 &'.

6b' is the second layer metal wiring. By repeating the method explained in FIGS. 2 to 6, it is possible to easily form a completely flat two-layer wiring without voids as shown in FIG. 7.

Effects of the Invention As described above, according to the present invention, in submicron multilayer wiring, an interlayer insulating film without voids (cavities) can be obtained by a simple method and can have a high interlayer breakdown voltage.

Furthermore, since a completely flat structure can be obtained, it is effective in improving ease of pattern formation and reliability. Therefore, it becomes easy to realize a high-density, large-scale integrated semiconductor integrated circuit having submicron multilayer wiring.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of a fine metal wiring produced by a method according to an embodiment of the present invention, FIGS. FIG. 9 is a cross-sectional view of metal wiring produced by a conventional manufacturing method. 1... Insulating film, 3... Polycrystalline silicon film, 5a. 5b...Metal wiring with submicron spacing. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure Metal wiring Figure 2 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9

Claims (1)

[Claims] A process of forming a concave groove for wiring in an insulating film, a process of forming a thin semiconductor film or a film containing a metal only on the side surfaces of the concave groove, and a process of forming a concave groove by reacting a gas containing a metal. A method for manufacturing a semiconductor integrated circuit, comprising the step of selectively growing the metal only in the metal.