JPS62140455A - Semiconductor storage - Google Patents

Abstract

PURPOSE:To prevent the direct intrusion to capacitance of noise charges generated at a time when charged particles such as alpha-rays are projected by forming an insulator under the capacitance of a dynamic RAM memory cell with memory cells each having one MOS transistor and a capacitance. CONSTITUTION:A capacitance holding a memory is shaped from two poly crystalline silicon layers 33, 42 and an insulating film 37 formed held by these layers 33, 42. The polycrystalline silicon film 33 is isolated from a substrate 31 by an silicon oxide film 32, and a transistor region 39 is shaped onto a high-concentration p-type region 43. That is, since these silicon oxide film 32 and high-concentration p-type region 43 and interposed among both an MOS transistor and the capacitance and the substrate 31, intrusion into a memory cell of noise charges generated in the substrate 31 is prevented effectively by the silicon oxide film 32 and the high-concentration p-type region 43. Consequent ly, the generation of a soft-error due to alpha-rays is reduced. Since funneling length is inhibited by the p-type layer 43 in high concentration, charges flowing in by a funneling effect are minimized, thus also generating exceedingly few soft errors.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a semiconductor memory device, and more particularly to a dynamic RAM having memristors each having one MOS transistor and a capacitor.

[Background of the invention]

A trace amount of α-rays are emitted from uranium and thorium contained as impurities in semiconductor device packages (containers that house semiconductor chips), and when these α-ray particles enter the semiconductor substrate, electrons and holes are generated within the semiconductor substrate. It is known that a pair occurs, which destroys information stored in a semiconductor memory.

Dynamic RAM, whose memory cell consists of one insulated field effect transistor (hereinafter abbreviated as MOS transistor) and one capacitor, stores information by storing charge in capacitor i. When the charge generated by the incident flows in, the charge stored in the capacitance fluctuates, destroying information. As the memory capacity becomes more highly integrated, the elements become smaller and the size of the capacitance becomes smaller, so the capacitance becomes smaller and information is more likely to be destroyed even by the inflow of a small amount of noise charge.

To prevent this information destruction, it is necessary to prevent the incidence of alpha rays, reduce the amount of charge that collects even if alpha rays are incident, or make the memory cell itself resistant to noise charges. Either of these methods can be used.

The first method is to cover the chip surface with a coating of several tens of micrometers or more made of a material that does not contain alpha ray sources, and cover the chip surface with a film that is thicker than the penetration distance, so that alpha rays can be absorbed by the silicon chips. It prevents it from reaching inside.

The second method is to provide the substrate with an appropriate impurity concentration or
An insulating layer is placed between the element and the substrate to suppress the inflow of charges generated by the incidence of alpha rays.

The third method is to increase the capacitance of the memory cell without increasing the memory cell area, thereby reducing changes in the stored charge due to the inflow of charge.

An example of the second method is the H i -C structure in which a high concentration layer is provided below the capacitor as shown in Figure 2, and an example of the third method is to dig a groove as shown in Figure 3. There are trench-type cells that increase capacity. In FIG. 2, a capacitor connected to the drain of a MOS transistor (consisting of a source drain 4 and a gate electrode 7) (highly doped p-type layer 4 and polycrystalline silicon 6 continuing from the drain, and an oxide film 5 sandwiched between them) is shown. ), one memory cell is formed by α
This prevents noise charges generated by the line from flowing into the capacitor.

In FIG. 3, a source/drain 13 and a gate electrode 14 form a MOS transistor, and a substrate 1
By digging a groove in 1 and filling it with polycrystalline silicon 15,
A capacitor is formed from the substrate 11, the polycrystalline silicon 15, and the insulating film 16 sandwiched therebetween. Also, the second.
As a composite example of the third method, in the conventional example, a capacitor is formed on a substrate such as that shown in FIG.
3 and an insulating film sandwiched between them.

The sidewall of the step formed by the gate electrode 20 is used to increase the area of the capacitance. Between the capacitor and the substrate 26, noise charges generated within the insulating film plate 26 are difficult to enter the capacitor.

Note that the MoS transistor is formed from a source/drain 19 and a gate electrode 20.

However, the structures shown in Figures 2 and 3 cannot be said to be definitively resistant to alpha rays, and in the example in Figure 4, large steps are formed, leading to concerns about wiring defects. .

On the other hand, the MOS transistor described in JP-A-56-108269 has a structure in which the source and drain electrodes are drawn out from the sidewall, and it has a structure similar to that of the high-performance bipolar transistor shown in JP-A-56-001556, and is manufactured in the same process. It is possible. Although it has been desired to realize a high-speed, highly integrated memory that uses two types of transistors, such as MOS and bipolar transistors, and is free from sober errors caused by alpha rays, no memory cell suitable for this purpose has been proposed.

It is an object of the present invention to provide a semiconductor memory device that is capable of achieving fast operation speed and high integration density.

[Summary of the invention]

When charged particles such as alpha rays are incident on a substrate, electron-hole pairs are generated along the trajectory of the charged particles. It is well known that when these electrons and holes flow into memory cells due to a phenomenon called diffusion and funneling effect, they cause memory destruction.

In order to prevent memory destruction from occurring, it is necessary to either block the inflow of carriers generated by the incidence of charged particles, or
The circuit must be configured to be resistant to changes in charge. The present invention proposes a memory cell having a structure that reduces the influx of carriers.

Among the phenomena related to charge movement, considering diffusion, for example, if there is a highly concentrated p-type layer in a p-type substrate, a barrier to electrons is created due to the difference in potential, and deuterons cannot enter the highly concentrated p-type layer. It disappears. Furthermore, as is obvious, electrons cannot flow into the insulator either.

An example of the structure of a memory cell according to the present invention is shown in FIG.

A MoS transistor is formed from the gate electrode 36 and the n+ type source/drain 41, and the source/drain 41 is drawn out from the side wall of the transistor region 39 with polycrystalline silicon 33 and connected to the pit line 38. The capacity to hold memory is two polycrystalline silicon layers 33.42
and an insulating film 37 formed between them.

Polycrystalline silicon W433 is separated from substrate 31 by silicon oxide film 32, and transistor region 39 is formed on heavily doped p-type region 43.

That is, the silicon oxide film 32 and the high concentration P type substantially region 43 form the MOS transistor, the capacitor, and the substrate 31.
Therefore, noise charges generated in the substrate 31 are prevented from entering the memory cells by the silicon oxide film 32.
is effectively blocked by the high concentration p-type region 43, and the soft 2? - The occurrence of - decreases markedly. Note that the symbol 35 represents PSG, 34 represents a thin silicon oxide film, and 40 represents a gate oxide film.

In addition, the funneling effect is a phenomenon that occurs when charged particles penetrate a depletion layer such as a pn junction.The rate is proportional to the junction area, so the funneling length is suppressed by a highly concentrated p-type layer. In the present invention, the amount of charge that flows in due to the fan ringing effect is very small, and the occurrence of soft errors is also very small.

The process allows fine processing and is suitable for high integration. Furthermore, since both bipolar and MOS transistors can be manufactured in the same process, high-speed operation can be achieved by disposing bipolar transistors in peripheral circuits.

[Embodiments of the invention]

The present invention will be explained in detail below.

A p-type layer 43 is formed by selectively implanting a p-type impurity such as boron into a desired portion of the p-type substrate 31 by ion implantation. This p-type layer 43 is a barrier for electrons and holes generated by charged particles such as alpha rays, and is also used to suppress the funneling effect, so its concentration is I x 10 ''
It is desirable that the ion implantation dose be about 1×1018 to 10140−2.Next, the p-type doped epitaxial layer 49 is
It is grown to ~1 μm (FIG. 5(a)).

The heavily doped p-type layer 43 can also be formed by ion implantation after forming the MoS transistor and before forming the gate polycrystalline silicon electrode. This method has the advantage that the shape can be easily controlled because there is little diffusion of the P-type layer 43 due to heat treatment.

After epitaxial growth, 45 shown in FIG. 5(b) is
They are sequentially formed by the VD method. The thickness of the gate oxide film 40 was 100 layers, the thickness of the silicon nitride film 44 was 500 layers, and the thickness of the silicon oxide 45 was 6000 layers.

Next, the silicon oxide film 45 and the silicon nitride film 44 in the other parts except the region 34 where the transistor is formed are
, gate oxide film 40 and epitaxial layer 49 were removed using sputter etching. Thereafter, the entire surface is thermally oxidized to form a silicon oxide film 32', and then a silicon nitride film 44 is formed by CVD. The silicon nitride film 44 is removed by directional etching leaving the sidewalls of the transistor formation region 39, to form a thin oxide wA32 (FIG. 5(Q)), and the nitride film 44 formed on the sidewalls of the transistor formation region 39 is removed. remove. Furthermore, after removing the thin oxide film 32 on the sidewalls, non-doped polycrystalline silicon 33 is formed on the entire surface by CVD to a thickness of about 600 nm.

The concave portions of the polycrystalline silicon 33 are filled with a resist, and a thick resist is further applied thereon until the surface is flattened.

Next, the resist is photo-etched from above until the surface of the convex portion of the polycrystalline silicon 33 appears, and then the convex portion of the polycrystalline silicon is removed by reactive ion etching to flatten the polycrystalline silicon 33 and remove the resist ( Figure 5 (e
)). Next, as shown in FIG. 5(f), after the surface of the polycrystalline silicon layer 33 is thinly thermally oxidized, the nitride film 44 is deposited by CVD.
Deposit by method. An n-type impurity (
For example, the primary polycrystalline silicon layer 33 in which P, etc.) is implanted by ion implantation is etched to a thickness of about 300 nm.

Next, as shown in FIG. 5(g), a polycrystalline silicon layer 33
Among them, the part without the silicon nitride film 44 on the surface is 600
Polycrystalline silica purulent 44 and silicon oxide film 34 are removed by thermal oxidation.

This step can eliminate the difference in level between the isolation region 48 and the polycrystalline silicon portion 33.

The thick oxide film 45 above the transistor region 29 is removed and selective oxidation is performed to form a thick oxide film 34 on the surface of the polycrystalline silicon 33 (FIG. 5(h)).

A portion of the oxide film 34 on the polycrystalline silicon 33 is removed, nitride 11537 is thinly deposited over the entire surface, and a polycrystalline silicon layer 42 is formed in the portion where the oxide film 34 has been removed. By forming a nitride film between two polycrystalline silicon layers 33 and 42, a capacitor for storing memory is formed (see Fig. 5).
i)). The vl electric current of silicon nitride film is about twice that of oxide film, and when the film thickness is 50 nm, it is 1.3 fF/pm.
It is. When using an oxide film of about 10 nm obtained by thermally oxidizing polycrystalline silicon, a dielectric constant comparable to that of the oxide film can be obtained even if the film is thicker than the oxide film. This method has the advantage that a stable film without pinballs can be obtained.

PSG was used for the interlayer film 35 between the polycrystalline silicon 33 serving as the plate and the polycrystalline silicon 42 serving as the gate electrode. The PSGll 135 and nitride film 37 on the gate 36 were removed, and polycrystalline silicon was deposited to form the gate electrode (word line) 36 (FIG. 5(j)). Finally PSG again
An interlayer insulating film 35' was formed by depositing A2, and a bit line 38 made of A2 was formed to obtain the structure shown in FIG.

According to this embodiment, when the AQ wiring width is 2 μm, the memory cell size is 5.7×8.4 μm2. The area of capacity is 2
6.4μmz+capacitance of 34.3fF can be achieved. If the nitride film, which is the insulator of the capacitor, is made to have a thickness of 25 nm, the area of the capacitor can be made 13.2 μm''. In that case, the cell size will be 4.2×8.4 μm”.

An example of the second vJ is shown in FIG. In this embodiment, the polycrystalline silicon layer 33 which is the side wall electrode of the transistor 39
The lower oxide film 32 is thinned, and a high concentration p-type layer 4 is formed under it.
A capacitor is formed in this portion by stretching 3, and the feature is that the two capacitors are formed overlapping each other. When the thickness of the oxide film 32 in the capacitor portion is 10 nm, a capacitance approximately 3.7 times greater than that of the embodiment with the same capacitance area can be obtained.

Moreover, the high concentration layer 43 directly under the capacitor effectively reduces noise charges caused by charged particles such as α rays.

The manufacturing method in this case is almost the same as in the first embodiment. That is, after the structure shown in FIG. 5(d) is formed, a portion of the oxide film 32 adjacent to the transistor is removed and thinly oxidized again. Thereafter, the steps after polycrystalline silicon deposition are the same as those of the first embodiment.

FIG. 7 shows a third embodiment. In this embodiment, the source and drain 46 are formed by ion implantation using the gate electrode 36 of the MOS transistor as a mask, resulting in a structure (LDDtJ structure) having a low concentration source train. After that, the side wall of the gate electrode 36 has a film 4 of a constant thickness.
7 to form a highly sensitive source/drain layer. Further, in the fourth embodiment shown in FIG. 8, a high concentration layer (41 in FIG. 7) is not formed by ion implantation, but a low concentration source/drain 46 is formed by ion implantation. It has a structure.

The third and fourth embodiments have the disadvantage that the epitaxial layer 39 must be wider than the gate electrode 36, which increases the size of the transistor. However, it is easy to control the value voltage and mutual conductance, and a transistor with stable characteristics can be obtained.

In each of the above embodiments, the layers connected to the sides of the source and drain and extending in the plane direction of the substrate were all formed of polycrystalline silicon, but instead of being made of polycrystalline silicon, for example, they were formed of W, Mo, Ti, etc.

Needless to say, conductive substances such as silicides of various metals such as Ta can be used.

〔Effect of the invention〕

According to the present invention, since an insulator exists under the capacitance of the dynamic RAM memory cell, noise charges generated when charged particles such as α rays are incident do not directly enter the capacitance.

The path through which the probe charge enters is the electrode part connected to the capacitance, and by setting the concentration of the high concentration p-type layer to 1019 particles - 3 or more, the amount of inflow charge per α ray is equal to that of the high concentration p-type layer. It is reduced by about 2 to 3 orders of magnitude compared to when it was not used.

Furthermore, by arranging self-aligned bipolar transistors with sidewall base electrode contact in the peripheral circuit, an ultra-high-speed dynamic RAM with an access time of about ins can be realized.

[Brief explanation of drawings]

FIG. 1 is a sectional view showing one embodiment of the present invention, and FIGS. 2 to 4 are sectional views showing a conventional device and an embodiment, respectively. 1.11,26,31...Substrate, 2...Shrimp layer, 3
...p ten layer, 4,13.19...source drain,
5゜12.2l-3iOz film, 6,15-...Cell plate, 7,14.20...Word line, 8,17.24
...Interlayer PSG, 9, 18.25...Bit line, 1
0...Protective film, 16...High dielectric insulating film, 22...
- Charge storage section, 23... polycrystalline silicon plate, 2
7...MOS transistor, 28...cell capacity, 9
...Word line, 30...Bit line contact, 32
．． 34...5 iOz film, 35... Interlayer PSG film, 3
6...Word line, 37...5iaNi film, 38...
・AQ bit line. 39... Shrimp layer, 40... Gate oxide film, 41...
・Source drain, 42... Polycrystalline Si plate, 4
3'''p ten layers, 44-S i sN4 film, 45-8i
Oz, 46...n-source drain, 47...gate electrode side (J spacer, 48...silicon oxide film, 4
9... Ehi No. l Kuchiho 4 Figure No. 5 Kuchi No. 5 a No. 6 Kuchi No. 7

Claims (1)

[Claims] In a semiconductor memory device including at least a capacitor serving as an information storage portion and an insulated gate field effect transistor,
a conductor layer connected to the side of the source and drain of the field effect transistor and extending in the plane direction of the semiconductor substrate; an insulator layer provided in contact with the lower surface of the conductor layer; and at least a portion below the field effect transistor. 1. A semiconductor memory device comprising a highly doped layer having the same conductivity type as the semiconductor substrate provided on the semiconductor substrate.