JPS62139352A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS62139352A
JPS62139352A JP60280750A JP28075085A JPS62139352A JP S62139352 A JPS62139352 A JP S62139352A JP 60280750 A JP60280750 A JP 60280750A JP 28075085 A JP28075085 A JP 28075085A JP S62139352 A JPS62139352 A JP S62139352A
Authority
JP
Japan
Prior art keywords
film
insulating film
electrode
tungsten
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60280750A
Other languages
Japanese (ja)
Inventor
Noriaki Sato
佐藤 典章
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP60280750A priority Critical patent/JPS62139352A/en
Publication of JPS62139352A publication Critical patent/JPS62139352A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/102Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including bipolar components
    • H01L27/1021Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including bipolar components including diodes only

Abstract

PURPOSE:To prevent a punch-through phenomenon in a insulating film breakdown incident by a method wherein an insulating film and Al electrode are laid on a semiconductor conductive region with the intermediary of a high- melting metal film, transition metal film, or high-melting silicide film and the insulating film is electrically broken down for the establishment of continuity between the semiconductor conductive region and Al electrode. CONSTITUTION:A tungsten film 10 is selectively attached to an electrode film formed on a semiconductor conductive region 2. After the attachment of an SiO2 film 3 by vapor phase growth to the tungsten film 10, an Al film is attached. The Al film is patterned into an Al electrode 5. Application of a voltage results in a breakdown of the insulating film 3 for the establishment of electrical continuity between the Al electrode 5 and conductive semiconductor region 2. The application of the voltage also results in a damaged tungsten film 10. With Al going into reaction with tungsten only with difficulty, the migration of Al is stopped by the tungsten film 10 before it reaches the semiconductor conductive region 2.

Description

【発明の詳細な説明】 [概要] 導電性半導体領域上に高融点金属膜、高融点金属シリサ
イド膜等の導電体膜を設け、その上に絶縁膜とアルミニ
ウム電極とを積層した構造にする。
[Detailed Description of the Invention] [Summary] A conductive film such as a high melting point metal film or a high melting point metal silicide film is provided on a conductive semiconductor region, and an insulating film and an aluminum electrode are laminated thereon.

そうすれば、電気的に絶縁膜を破壊した時、半導体領域
にダメージを与えることがな(なる。
This will prevent damage to the semiconductor region when the insulating film is electrically destroyed.

[産業上の利用分野] 本発明は半導体装置のうち、特に、逆フユーズ構造の半
導体セルに関する。
[Industrial Field of Application] The present invention relates to a semiconductor device, and particularly to a semiconductor cell having an inverted fuse structure.

半導体集積回路(IC)において、FROM (プログ
ラマブルROM)や冗長回路構成が採られた場合、逆フ
ェーズセル(絶縁膜を破壊して導通させる:絶縁−導通
)やフユーズセル(導通−絶縁)が設けられている。
When a FROM (programmable ROM) or redundant circuit configuration is adopted in a semiconductor integrated circuit (IC), a reverse phase cell (destroying the insulating film to make it conductive: insulation-conduction) or a fuse cell (conduction-insulation) is provided. ing.

このようなセルは、接続または切断の動作時に、ICメ
モリ (セルアレイ)に悪影響を与えないように考慮し
た構造が望まれている。
It is desired that such cells have a structure that takes into consideration not to adversely affect the IC memory (cell array) during connection or disconnection operations.

[従来の技術] P ROM (Programmabie Read 
0nly Memory)は   ゛使用者が自由にメ
モリをプログラムできる半渾体記憶装置であり、そのた
めに所望のビットセルを接続または切断することが必要
になって、逆フユーズセルやフユーズセルが設けられて
いる。
[Prior art] P ROM (Programmabie Read
0nly Memory) is a semi-electromechanical storage device in which the user can freely program the memory.For this purpose, it is necessary to connect or disconnect desired bit cells, and therefore reverse fuse cells and fuse cells are provided.

また、ICメモリ (セルアレイ)の高集積化に伴って
、メモリのビット数が飛躍的に増大し、それが収率の低
下(歩留の低下)をきたし、率いては、コストアップに
繋がっているが、これを避けるために考案されたのがI
Cの冗長回路構成で、従って、冗長回路はFROMと同
様に逆フユーズセルやフユーズセルが設けられて、不良
ビットを切り捨てたり、良品ビットを接続する処置がな
されている。
Additionally, as IC memories (cell arrays) become more highly integrated, the number of memory bits increases dramatically, leading to a decrease in yield (yield reduction), which in turn leads to an increase in costs. However, I was devised to avoid this.
According to the redundant circuit configuration of C, the redundant circuit is provided with inverse fuse cells and fuse cells similar to FROM, and measures are taken to discard defective bits and connect good bits.

本発明は、これらの回路に設けられている逆フユーズセ
ルやフユーズセルのうち、逆フユーズセルに関するもの
である。又、逆フユーズセルはBI C(Breakd
own of In5ulator for Cond
uction)セルとも称している。
The present invention relates to a reverse fuse cell among the reverse fuse cells and fuse cells provided in these circuits. Also, the reverse fuse cell is BI C (Breakd
own of In5lator for Cond
It is also called a cell.

この逆フユーズセルは通常、第4図(alの実施例に示
すような断面構造のものが利用されており、第4図fa
lにおいて、1はp型半導体基板、2はn“型半導体導
電領域、3は5i02膜(酸化シリコン膜)又はSi3
 N4膜(窒化シリコン膜)からなる絶縁膜、4は燐珪
酸ガラス(PSG)膜(層間絶縁膜)、4はアルミニウ
ム電極である。
This inverted fuse cell usually has a cross-sectional structure as shown in the example in Fig. 4 (al), and is
1, 1 is a p-type semiconductor substrate, 2 is an n" type semiconductor conductive region, and 3 is a 5i02 film (silicon oxide film) or Si3
An insulating film made of an N4 film (silicon nitride film), 4 a phosphosilicate glass (PSG) film (interlayer insulating film), and 4 an aluminum electrode.

このような構造を設けた後、プログラム時に絶縁膜3を
電気的に破壊し、アルミニウム電極5と導電領域2とを
導通させて、導電領域2と接続しているビットライン(
図示せず)とアルミニウム電極と接続して、セルあるい
は回路の選択を図っている。第4図(b)は絶縁膜3を
破壊した後の断面図を示しており、この絶縁膜3は絶縁
耐圧以上の電圧を印加すれば破壊され、例えば膜厚80
〜100人の絶縁膜であると20V前後の電圧で破壊す
ることができる。
After providing such a structure, the insulating film 3 is electrically destroyed during programming, the aluminum electrode 5 and the conductive region 2 are electrically connected, and the bit line (
(not shown) and an aluminum electrode to select a cell or circuit. FIG. 4(b) shows a cross-sectional view after the insulating film 3 is destroyed, and this insulating film 3 will be destroyed if a voltage higher than the dielectric strength voltage is applied, and for example, the film thickness is 80 mm.
An insulating film of ~100 people can be destroyed at a voltage of around 20V.

[発明が解決しようとする問題点] ところが、第4図山)のように電圧を印加して絶縁膜3
を破壊すると、その際、アルミニウムがスパイクして導
電領域2を越えて半導体基板1に突き抜けることとがあ
り、そうすれば、半導体基板とアルミニウム電極が短絡
してしまうことになる。
[Problems to be solved by the invention] However, as shown in Fig. 4, the insulating film 3
When broken, aluminum may spike and penetrate beyond the conductive region 2 into the semiconductor substrate 1, resulting in a short circuit between the semiconductor substrate and the aluminum electrode.

そうすれば、そのアルミニウム電極に接続するビットセ
ルや回路が不良になって、書込みエラーを生じ、セルア
レイ全体の信頼性を低下させる。
If this happens, the bit cells or circuits connected to the aluminum electrodes will become defective, causing write errors and lowering the reliability of the entire cell array.

最近、ICが微細化され、シャロウジャンクショウ(浅
い接合)によって半導体導電領域2が形成されているか
ら、特に上記のようなトラブルが増加しつつある。
Recently, as ICs have been miniaturized and semiconductor conductive regions 2 have been formed by shallow junctions, the above-mentioned troubles are increasing in particular.

本発明は、このような問題点を解消するための逆フユー
ズセルを提案するものである。
The present invention proposes a reverse fuse cell to solve these problems.

[問題点を解決するための手段] その問題は、導電性半導体領域上に高融点金属膜、高融
点金属シリサイド膜などを介して絶縁膜とアルミニウム
電極とを積層した構造にして、前記絶縁膜を電気的に破
壊して前記導電性半導体領域とアルミニウム電極とを導
通ずるようにした半導体装置によって解決される。
[Means for solving the problem] The problem is to create a structure in which an insulating film and an aluminum electrode are laminated on a conductive semiconductor region via a high melting point metal film, a high melting point metal silicide film, etc. The problem is solved by a semiconductor device in which the conductive semiconductor region and the aluminum electrode are electrically broken down to establish electrical continuity between the conductive semiconductor region and the aluminum electrode.

[作用コ 即ち、本発明は、導電性領域と絶縁膜との間に、高融点
金属膜、高融点金属シリサイド膜などを設け、その上に
絶縁膜とアルミニウム電極とを積層した構造にする。そ
うすれば、電圧印加して絶縁膜を破壊した時、半導体基
板にまでアルミニウムが達する突き抜は現象はなくなる
[In other words, the present invention has a structure in which a refractory metal film, a refractory metal silicide film, or the like is provided between a conductive region and an insulating film, and an insulating film and an aluminum electrode are laminated thereon. By doing so, when the insulating film is destroyed by applying a voltage, there will be no punch-through phenomenon in which the aluminum reaches the semiconductor substrate.

[実施例コ 以下、図面を参照して実施例によって詳細に説明する。[Example code] Hereinafter, embodiments will be described in detail with reference to the drawings.

第1図は本発明にかかるセルの断面構造を示しており、
10はタングステン(W)膜で、その他の部材の記号は
第4図(at、 (blと同様である。即ち、電極窓に
膜厚1000人前後のタングステン膜10を設け、これ
をバリヤメタルとして、その上に膜厚80〜100人の
5i02膜3を介してアルミニウム電極5を設ける。そ
うすると、電圧を印加した時、ダメージがタングステン
膜10に加わるが、アルミニウムはタングステンと反応
し難いから、アルミニウムの移動がタングステン膜で阻
止されて、電圧印加、の影響が半導体基板1は勿論、半
導体導電領域2にも及ばない。且つ、絶縁膜3が破壊さ
れて、アルミニウム電極5と導電領域2とは導通する。
FIG. 1 shows the cross-sectional structure of a cell according to the present invention,
10 is a tungsten (W) film, and the symbols of other members are the same as those in FIG. An aluminum electrode 5 is provided thereon through a 5i02 film 3 with a film thickness of 80 to 100. Then, when a voltage is applied, damage is added to the tungsten film 10, but since aluminum hardly reacts with tungsten, The movement is blocked by the tungsten film, and the influence of the voltage application does not affect not only the semiconductor substrate 1 but also the semiconductor conductive region 2. Furthermore, the insulating film 3 is destroyed, and the aluminum electrode 5 and the conductive region 2 are not electrically connected. do.

次に、第2図(a)〜(C)はその形成工程順断面図を
示し、まず、同図(a)に示すように、半導体導電領域
2の上に形成された約2μm角の電極窓に、選択的に膜
厚1000人程度0タングステン膜10を被着させる。
Next, FIGS. 2(a) to 2(C) show cross-sectional views in the order of the formation process. First, as shown in FIG. 2(a), an approximately 2 μm square electrode is formed on the semiconductor conductive region 2. A tungsten film 10 having a film thickness of about 1000 mm is selectively deposited on the window.

被着方法は六弗化タングステン(W F s)を用いた
気相成長法によるが、この方法を用いれば半導体領域に
のみ選択成長させることができる。
The deposition method is a vapor phase growth method using tungsten hexafluoride (W F s), which allows selective growth only in the semiconductor region.

次いで、第2図(blに示すように、気相成長法によっ
て膜厚80〜100人の5i02膜3を上面に被着した
後、同図(C1に示すように、スパッター法で膜厚1μ
m程度のアルミニウム膜を被着し、これをパターンニン
グしてアルミニウム電極5を形成する。
Next, as shown in FIG. 2 (bl), a 5i02 film 3 with a thickness of 80 to 100 layers was deposited on the upper surface by vapor phase epitaxy, and then, as shown in FIG.
An aluminum film having a thickness of approximately m is deposited and patterned to form an aluminum electrode 5.

また、第3図は本発明にかかる他のセルの断面構造を示
しており、本例はタングステンシリサイド(WSi2)
膜11をスパンタ法で全面に被着させ、更に、その上に
5i02膜3を被着して、同時に両方をドライエツチン
グ法でパターンニングした構造である。本例も第1図の
構造と同様に、ダメージを半導体導電領域に与えること
がなくなる。
Moreover, FIG. 3 shows the cross-sectional structure of another cell according to the present invention, and this example is made of tungsten silicide (WSi2).
The structure is such that a film 11 is deposited over the entire surface by a spunter method, a 5i02 film 3 is further deposited thereon, and both are simultaneously patterned by a dry etching method. Similarly to the structure shown in FIG. 1, this example also prevents damage from being caused to the semiconductor conductive region.

なお、このような絶縁膜3と半導体導電領域2との間に
介在させるバリヤメタルは、上記例に躍らず、その他の
モリブデンや白金、そのシリサイド膜などを用いること
ができる。
Note that the barrier metal interposed between the insulating film 3 and the semiconductor conductive region 2 is not limited to the above example, and other materials such as molybdenum, platinum, or a silicide film thereof may be used.

上記のような構造にすれば、アルミニウムの突き抜は現
象が防止されて、セルアレイの書込みエラーが解消され
、ICが高信頼化される。
With the above structure, the phenomenon of punching through the aluminum is prevented, writing errors in the cell array are eliminated, and the IC becomes highly reliable.

上記例はメモリで説明しているが、その他のICにも適
用できることは云うまでもない。
Although the above example is explained using a memory, it goes without saying that it can also be applied to other ICs.

[発明の効果コ 以上の説明から明らかなように、本発明によればメモリ
などICの信頬性が大幅に向上するものである。
[Effects of the Invention] As is clear from the above explanation, according to the present invention, the credibility of ICs such as memories is greatly improved.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明にかかるセルの断面構造図、第2図(a
)〜(C)はその形成工程順断面図、第3図は本発明に
かかる他のセルの断面構造図、第4図(a)、 (b)
は従来のセルの断面構造図である。 図において、 1はp型半導体基板、 2はn+型半導体導電領域、 3は絶縁膜、     4はPSG膜、5はアルミニウ
ム電極、10はタングステン膜、11はタングステンシ
リサイド膜 半1EJfi+;v・tps tLqpfjnJL5J
[11!1  図 ン)i Bl+=tpeltM e*’r、g槽図@ 
2 図
FIG. 1 is a cross-sectional structural diagram of a cell according to the present invention, and FIG. 2 (a
) to (C) are sectional views in the order of their formation steps, FIG. 3 is a sectional structural view of another cell according to the present invention, and FIGS. 4(a) and (b)
is a cross-sectional structural diagram of a conventional cell. In the figure, 1 is a p-type semiconductor substrate, 2 is an n + type semiconductor conductive region, 3 is an insulating film, 4 is a PSG film, 5 is an aluminum electrode, 10 is a tungsten film, 11 is a tungsten silicide film half 1EJfi+; v・tps tLqpfjnJL5J
[11!1 Diagram) i Bl+=tpeltM e*'r, g tank diagram @
2 Figure

Claims (1)

【特許請求の範囲】[Claims]  導電性半導体領域上に高融点金属膜、高融点以外の遷
移金属膜、高融点金属シリサイド膜、またはそれらの複
合膜・合金膜を介して絶縁膜とアルミニウム電極とを積
層した構造にして、前記絶縁膜を電気的に破壊して前記
導電性半導体領域とアルミニウム電極とを導通するよう
にしたことを特徴とする半導体装置。
A structure is formed in which an insulating film and an aluminum electrode are laminated on a conductive semiconductor region via a high melting point metal film, a transition metal film other than a high melting point film, a high melting point metal silicide film, or a composite film/alloy film thereof. 1. A semiconductor device, characterized in that the insulating film is electrically broken down to establish electrical continuity between the conductive semiconductor region and the aluminum electrode.
JP60280750A 1985-12-12 1985-12-12 Semiconductor device Pending JPS62139352A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60280750A JPS62139352A (en) 1985-12-12 1985-12-12 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60280750A JPS62139352A (en) 1985-12-12 1985-12-12 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS62139352A true JPS62139352A (en) 1987-06-23

Family

ID=17629431

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60280750A Pending JPS62139352A (en) 1985-12-12 1985-12-12 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS62139352A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01207725A (en) * 1988-02-16 1989-08-21 Hamamatsu Photonics Kk Total optical image signal processing device
US5852328A (en) * 1996-02-05 1998-12-22 Matsushita Electronics Corporation Semiconductor device and method of manufacturing the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01207725A (en) * 1988-02-16 1989-08-21 Hamamatsu Photonics Kk Total optical image signal processing device
US5852328A (en) * 1996-02-05 1998-12-22 Matsushita Electronics Corporation Semiconductor device and method of manufacturing the same

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