JPS62139132U - - Google Patents
Info
- Publication number
- JPS62139132U JPS62139132U JP2546386U JP2546386U JPS62139132U JP S62139132 U JPS62139132 U JP S62139132U JP 2546386 U JP2546386 U JP 2546386U JP 2546386 U JP2546386 U JP 2546386U JP S62139132 U JPS62139132 U JP S62139132U
- Authority
- JP
- Japan
- Prior art keywords
- output
- flop
- flip
- differential amplifier
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims 3
- 230000010355 oscillation Effects 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 4
Description
第１図は本考案の一実施例を示す図、第２図は
第１図各部の波形図、第３図は従来例を示す図、
第４図は第３図各部の波形図である。
２，３，７……差動増幅回路、４……フリツプ
フロツプ、６……時定数回路、８……ＥＸ―ＮＯ
Ｒ回路。
FIG. 1 is a diagram showing an embodiment of the present invention, FIG. 2 is a waveform diagram of each part of FIG. 1, and FIG. 3 is a diagram showing a conventional example.
FIG. 4 is a waveform diagram of each part in FIG. 3. 2, 3, 7...Differential amplifier circuit, 4 ...Flip-flop, 6 ...Time constant circuit, 8...EX-NO
R circuit.
Claims (1)
フロツプの夫々の入力端に接続し、前記フリツプ
フロツプの出力端を抵抗とコンデンサとよりなる
時定数回路に接続し、コンデンサと抵抗との接続
点から前記第１、第２の差動増幅回路の比較入力
端に夫々接続すると共に基準入力端には基準電圧
Ｖ１，Ｖ２を夫々入力するようになし、更に基準
入力端に前記基準電圧Ｖ１，Ｖ２に対してＶ１＜
Ｖ３＜Ｖ２の関係を有する基準電圧Ｖ３が入力さ
れ且つ比較入力端に前記コンデンサと抵抗との接
続点が接続された少なくとも１つの差動増幅回路
を設け、この差動増幅回路の出力と前記フリツプ
フロツプの出力とを論理回路にて論理演算するこ
とにより発振出力を得るようにしたことを特徴と
する発振回路。 The output terminals of the first and second differential amplifier circuits are connected to respective input terminals of a flip-flop, and the output terminal of the flip-flop is connected to a time constant circuit consisting of a resistor and a capacitor, and the connection point between the capacitor and the resistor is connected to the output terminal of the flip-flop. are connected to the comparison input terminals of the first and second differential amplifier circuits, respectively, and the reference voltages V 1 and V 2 are input to the reference input terminals, respectively, and the reference voltage V is connected to the reference input terminal. 1 , V 2 for V 1 <
At least one differential amplifier circuit is provided to which a reference voltage V 3 having a relationship of V 3 <V 2 is input and a connection point between the capacitor and the resistor is connected to a comparison input terminal, and the output of this differential amplifier circuit is An oscillation circuit characterized in that an oscillation output is obtained by performing a logical operation on and the output of the flip-flop in a logic circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2546386U JPS62139132U (en) | 1986-02-24 | 1986-02-24 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2546386U JPS62139132U (en) | 1986-02-24 | 1986-02-24 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62139132U true JPS62139132U (en) | 1987-09-02 |
Family
ID=30825640
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2546386U Pending JPS62139132U (en) | 1986-02-24 | 1986-02-24 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62139132U (en) |
-
1986
- 1986-02-24 JP JP2546386U patent/JPS62139132U/ja active Pending
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