JPS62138967A - Data converting and processing system - Google Patents

Data converting and processing system

Info

Publication number
JPS62138967A
JPS62138967A JP60280610A JP28061085A JPS62138967A JP S62138967 A JPS62138967 A JP S62138967A JP 60280610 A JP60280610 A JP 60280610A JP 28061085 A JP28061085 A JP 28061085A JP S62138967 A JPS62138967 A JP S62138967A
Authority
JP
Japan
Prior art keywords
arithmetic operation
arithmetic
register
memory
instruction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60280610A
Other languages
Japanese (ja)
Inventor
Isamu Hosaka
保坂 勇
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP60280610A priority Critical patent/JPS62138967A/en
Publication of JPS62138967A publication Critical patent/JPS62138967A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To decrease the possibility to generate a malfunction by saving the contents of a register to a memory on the way to convert an arithmetic operation formula tree to an arithmetic operation instruction without forecasting whether or not the arithmetic operation result accommodated to a register is saved to a memory. CONSTITUTION:An inputted arithmetic operation formula tree, in a common arithmetic operation item overlapping device 1, traces in the back end formula sequence (the sequence of f, g, d, h and b) from arithmetic item codes f-k to operator nodes a-e, registers to an arithmetic operation item memory device 2 and the common arithmetic operation item overlapping device 1 investigates the registered arithmetic operation item and at the time of the same arithmetic operation item, overlapping is executed. A register control device 4, when an arithmetic operation formula converting device 3 converts the arithmetic operation item to the arithmetic operation instruction, executes the assignment of the register needed to hold the arithmetic operation result, and when the register to be assigned is already used to hold other arithmetic operation result, the contents are saved to the memory and can be used.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は、データ変換装置に於けるデータ変換処理方式
に関するもので、算術演算式木を算術演算器への算術演
算命令列へ変換するための変換処理方式に関する。
Detailed Description of the Invention (Industrial Application Field) The present invention relates to a data conversion processing method in a data conversion device, and is for converting an arithmetic expression tree into an arithmetic operation instruction string for an arithmetic operation unit. Concerning the conversion processing method.

(従来の技術) 従来、この種のデータ変換処理方式では、算術演算命令
への変換を行う前に、レジスタに格納された算術演算結
果をメモリへ退避する必要があるか否かの予測をしてか
ら行っていた。また、共通部分式の重ね合わせを行って
いなかった。
(Prior art) Conventionally, this type of data conversion processing method predicts whether or not the arithmetic operation result stored in a register needs to be saved to memory before converting it to an arithmetic operation instruction. I went there after that. Also, the common subexpressions were not superimposed.

(発明が解決しようとする問題点) 上述した従来のデータ変換処理方式において、レジスタ
に格納された算術演算結果をメモリへ退避するか否かの
予測を算術演算器毎に作成する必要があり予測が正確に
行われずに誤動作の原因になっていた。さらに、共通部
分式の重ね合せが行われないために変換された算術演算
命令列に重複した算術演算命令を含み冗長さがあった。
(Problems to be Solved by the Invention) In the conventional data conversion processing method described above, it is necessary to create a prediction for each arithmetic unit as to whether or not the arithmetic operation result stored in the register will be saved to memory. was not performed accurately, causing malfunctions. Furthermore, since the common subexpressions are not superimposed, the converted arithmetic operation instruction string contains redundant arithmetic operation instructions, resulting in redundancy.

(問題点を解決するための手段) 本発明のテ゛−タ変換処理方式は、レジスタに格納され
た算術演算結果をメモリへ退避するか否かの予測は行わ
ず、算術演算式木を算術演算命令へ変換する途中で、演
算結果を格納するためのレジスタが既に以前の算術演算
結果を格納するために使用中であるとき、レジスタに格
納された算術演算結果をメモリへ退避することにより、
誤動作の起る可能性を減らし、共通部分式の重ね今わせ
を行うことにより、変換された算術演算命令列の重複し
た算術演算命令を削除している。
(Means for Solving the Problem) The data conversion processing method of the present invention does not predict whether or not the arithmetic operation result stored in a register will be saved to memory, but instead performs an arithmetic operation on an arithmetic operation expression tree. During conversion to an instruction, if the register for storing the operation result is already in use for storing the previous arithmetic operation result, by saving the arithmetic operation result stored in the register to memory,
Duplicate arithmetic operation instructions in the converted arithmetic operation instruction sequence are deleted by reducing the possibility of malfunctions and by resizing common subexpressions.

(実施例) 次に、本発明について図面を参照して説明する。(Example) Next, the present invention will be explained with reference to the drawings.

第1図は本発明のデータ変換処理方式を具体的にした装
置の一実施例の構成を示す図である。1は入力された算
術波n式本の中から共通部分式を捜しだし、共通部分式
の重ね合せを行うための共通算術演算項重ね合せ装置で
ある。2は共通算術演算項重ね合せ装置1で使用する共
通部分式を保持しておくための算術演算項記憶装置であ
る。3は算術演算式木を算術演算器の算術演算命令列へ
変換するための算術演算式変換装置である。4は算術演
算式変換装置3が算術演算項を算術演算命令へ変換する
際に算術演算結果を保持するために必要とされるレジス
タの割り当てを行いかつ、割り当てるべきレジスタが既
に他の算術演算結果を保持するために使用中であるとき
に、既に使用中のレジスタの内容をメモリへ退避して使
用可能にするためのレジスタ管理装置である。5は算術
演算式変換装置3が算術演算項を算術演算命令へ変換し
た結果、算術演算項を算術演算結果の保持されているレ
ジスタへ書き換えを行うか、レジスタ管理装置4が使用
中のレジスタの内容をメモリへ退避した結果、算術演算
項を算術演算結果の保持されているメモリへ書き換えを
行うための算術演算項書き換え装置である。
FIG. 1 is a diagram showing the configuration of an embodiment of an apparatus embodying the data conversion processing method of the present invention. Reference numeral 1 denotes a common arithmetic operation term superposition device for searching for a common sub-expression from among the input n arithmetic wave expressions and superimposing the common sub-expressions. 2 is an arithmetic operand storage device for holding common subexpressions used in the common arithmetic operand superposition device 1; 3 is an arithmetic expression conversion device for converting an arithmetic expression tree into an arithmetic operation instruction string for an arithmetic operation unit. 4 allocates registers required to hold arithmetic operation results when the arithmetic operation expression conversion device 3 converts an arithmetic operation term into an arithmetic operation instruction, and the register to be allocated has already been used for another arithmetic operation result. This is a register management device that saves the contents of a register that is already in use to memory and makes it usable when the register is being used to hold a register. 5, as a result of the arithmetic operation term being converted into an arithmetic operation instruction by the arithmetic operation expression conversion device 3, the arithmetic operation term is rewritten into the register where the arithmetic operation result is held, or the register management device 4 rewrites the register in use. This is an arithmetic operation term rewriting device for rewriting an arithmetic operation term to a memory in which the arithmetic operation result is held as a result of saving the contents to the memory.

第2図は本発明のデータ変換処理装置への入力データで
ある算術演算式木の一例を示す図である。算術演算式木
の各算術演算項(a−k)は、ランダムアクセスメモリ
上に置かれ、■〜[株]のアドレス値により関係付けら
れる。第2図の各算術演算項(a−k)のうちa−eま
でを演算子ノード、f−kまでを演算項メートと呼び、
各々のノードのデータ構造を第3図、第4図に示す。第
3図の演算子ノードは演算項を指し示すためのアドレス
を保持している。
FIG. 2 is a diagram showing an example of an arithmetic expression tree that is input data to the data conversion processing device of the present invention. Each arithmetic operation term (a-k) of the arithmetic operation expression tree is placed on a random access memory and is related by an address value of .about.[stock]. Among the arithmetic operands (a-k) in Figure 2, a-e are called operator nodes, and f-k are called operator mates,
The data structure of each node is shown in FIGS. 3 and 4. The operator node in FIG. 3 holds an address for pointing to an operand.

第4図の演算項ノードは演算項を指し示すアドレス値ま
たはレジスタ種別を示す値を保持している。
The operand node in FIG. 4 holds an address value pointing to the operand or a value indicating the register type.

第5図は第2図の算術演算式木に対し共通部分式の重ね
合せを行った結果の算術演算式木を図示したものである
FIG. 5 shows an arithmetic expression tree obtained by superimposing common subexpressions on the arithmetic expression tree of FIG. 2.

次に本実施例における動作を説明する。本データ変換処
理装置へ入力された算術演算式木は、共通算術演算項重
ね合せ装置1において演算項ノードから演算子ノードへ
と後置式順(第2図のf、g、d、h、bの順)にたど
り算術演算項記憶装置2へ登録する。共通算術演算項重
ね合せ装置1は、算術演算項記憶装置2に登録済の算術
演算項を調べて同じ算術演算項があれば重ね合せを行う
。重ね合せられた共通部分式は複数の演算子ノードから
同じアドレス値により指し示されることになる。全ての
重ね合せが行なわれた算術演算大木は演算式変換装置3
において算術演算命令に変換される算術演算命令への変
換は後置式順に各演算子ノードに対応した算術演算命令
へ逐次変換して行われる。算術演算命令への変換では演
算結果を格納するために必要なレジスタをレジスタ管理
装置4から受は取り使用する。算術演算命令に変換され
た演算子ノードは算術演算項書き換え装置5によりレジ
スタ管理装置4から受は取ったレジスタを保持する演算
項ノードに書き換えられる。
Next, the operation in this embodiment will be explained. The arithmetic expression tree input to this data conversion processing device is processed in the common arithmetic operand superposition device 1 in the order of postfix expressions (f, g, d, h, b in Fig. 2) from the operand node to the operator node. ) and register it in the arithmetic operation term storage device 2. The common arithmetic operation term superimposition device 1 examines the arithmetic operation terms already registered in the arithmetic operation term storage device 2, and performs superposition if there are the same arithmetic operation terms. The superimposed common subexpressions will be pointed to by the same address value from multiple operator nodes. The arithmetic operation large tree on which all the superpositions have been performed is the arithmetic expression conversion device 3.
Conversion into arithmetic operation instructions that are converted into arithmetic operation instructions is performed by successively converting into arithmetic operation instructions corresponding to each operator node in the order of postfix expressions. In the conversion to an arithmetic operation instruction, registers necessary for storing the operation result are received from the register management device 4 and used. The operator node converted into an arithmetic operation instruction is rewritten by the arithmetic operation item rewriting device 5 into an operation item node that holds the register received from the register management device 4.

(発明の効果) 以上説明したように本発明のデータ変換処理方式は、レ
ジスタに格納された算術演算結果をメモリへ退避するか
否かの予測は行わず、算術演算式木を算術命令へ変換す
る途中で、演n結果を格納するためのレジスタが既に以
前の算術演算結果を格納するために使用中であるとき、
レジスタに格納された算術演算結果をメモリへ退避する
ことにより、誤動作の起る可能性を減らし、共通部分式
の重ね合せを行うことにより、変換された算術演算命令
列の重複した算術演算命令を削除できる効果がある。
(Effects of the Invention) As explained above, the data conversion processing method of the present invention does not predict whether or not the arithmetic operation result stored in the register will be saved to memory, but converts the arithmetic expression tree into an arithmetic instruction. During the process, when the register for storing the result of the operation n is already in use for storing the result of the previous arithmetic operation,
By saving the arithmetic operation results stored in the registers to memory, the possibility of malfunctions is reduced, and by overlapping common subexpressions, duplicate arithmetic operation instructions in the converted arithmetic operation instruction string are eliminated. There is an effect that can be deleted.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明のデータ変換処理方式を具体的にした装
置の一実施例の構成図、第2図は算術演算大木の一例を
示す図、第3図は演算子ノードのデータ構造の一例を示
す図、第4図は演算項ノードのデータ構造の一例を示す
図、第5図は共通部分式の重ね合せを行った結果の一例
を示す図である。 図において、 109.共通算術演算項重ね合せ装置、2・・・算術演
算項記憶装置、 3・・・算術演算式変換装置、 4・・・レジスタ管理装置、 5、・・算fl’J’r演算項書き換え装置、a−k・
・・算術演算項、 ■〜[株]・6.アドレス値をそれ
ぞれ示す。
Fig. 1 is a block diagram of an embodiment of a device embodying the data conversion processing method of the present invention, Fig. 2 is a diagram showing an example of a large arithmetic operation tree, and Fig. 3 is an example of the data structure of an operator node. FIG. 4 is a diagram showing an example of the data structure of an operand node, and FIG. 5 is a diagram showing an example of the result of superimposing common subexpressions. In the figure, 109. Common arithmetic operand superposition device, 2... Arithmetic operand storage device, 3... Arithmetic expression conversion device, 4... Register management device, 5... Arithmetic fl'J'r operand rewriting device , a-k・
・・Arithmetic operator, ■〜[Stock]・6. Each indicates an address value.

Claims (1)

【特許請求の範囲】[Claims] 木構造に表現された算術演算式(算術演算式木)を入力
データとして、1個以上の高速レジスタと一次記憶を行
なうメモリとを持った算術演算器への算術演算命令列を
出力データとするデータ変換処理方式において、算術演
算式中に現れる重複した算術演算部分式である共通部分
式を同一の算術演算部分式と重ね合わせることにより、
入力データである算術演算式木の全ての同形算術部分式
を重ね合わせるとともに、算術演算式木のボトムからト
ップへ算術演算項をたどりながらレジスタへ算術演算結
果を格納する算術演算命令に変換し、算術演算命令への
変換において算術演算結果を格納するレジスタが既に以
前の算術演算命令で算術演算結果を格納するために使用
中であるとき、以前の算術演算結果を保持しているレジ
スタの内容をメモリへ退避する命令を出力した後、該レ
ジスタへ算術演算結果を格納する算術演算命令へ変換す
ることにより、算術演算式木を算術演算命令列へ変換す
ることを特徴とするデータ変換処理方式。
An arithmetic operation expression expressed in a tree structure (arithmetic operation expression tree) is used as input data, and an arithmetic operation instruction sequence to an arithmetic operation unit having one or more high-speed registers and memory for primary storage is output data. In the data conversion processing method, by overlapping a common subexpression that is a duplicate arithmetic operation subexpression that appears in an arithmetic operation expression with the same arithmetic operation subexpression,
All isomorphic arithmetic subexpressions of the arithmetic operation expression tree that are input data are superimposed, and the arithmetic operation results are converted into arithmetic operation instructions that store the arithmetic operation results in registers while tracing the arithmetic operation terms from the bottom to the top of the arithmetic operation expression tree. In conversion to an arithmetic operation instruction, if the register storing the arithmetic operation result is already in use for storing the arithmetic operation result in a previous arithmetic operation instruction, the contents of the register holding the previous arithmetic operation result are A data conversion processing method characterized by converting an arithmetic expression tree into an arithmetic operation instruction string by outputting an instruction to save to a memory and then converting it into an arithmetic operation instruction that stores an arithmetic operation result in the register.
JP60280610A 1985-12-12 1985-12-12 Data converting and processing system Pending JPS62138967A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60280610A JPS62138967A (en) 1985-12-12 1985-12-12 Data converting and processing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60280610A JPS62138967A (en) 1985-12-12 1985-12-12 Data converting and processing system

Publications (1)

Publication Number Publication Date
JPS62138967A true JPS62138967A (en) 1987-06-22

Family

ID=17627435

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60280610A Pending JPS62138967A (en) 1985-12-12 1985-12-12 Data converting and processing system

Country Status (1)

Country Link
JP (1) JPS62138967A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105431789A (en) * 2014-07-14 2016-03-23 三菱电机株式会社 Plc system and arithmetic expression data creation assistance device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105431789A (en) * 2014-07-14 2016-03-23 三菱电机株式会社 Plc system and arithmetic expression data creation assistance device

Similar Documents

Publication Publication Date Title
US5701487A (en) Method and apparatus for displaying locations of errors detected inside software macro calls
US5551039A (en) Compiling a source code vector instruction by generating a subgrid loop for iteratively processing array elements by plural processing elements
Nelson A comparison of PASCAL intermediate languages
JPS62138967A (en) Data converting and processing system
JPH0877118A (en) Distributed processor and process execution method
JP2501394B2 (en) Procedure call translation device
KR970011897B1 (en) Words interpretating device
JPS6049464A (en) Inter-processor communication system of multi-processor computer
JPH02130637A (en) Source code translating system
JPS62105240A (en) Register assignment system for common type optimized processing
JPS63285668A (en) Vector load processing method
JPS6358558A (en) Garbage collection processing system
JPH0531170B2 (en)
Dermoudy FLIPPANT: A Transputer-based Implementation of a Functional Language
JPH09120383A (en) Data input and output method and device therefor
JPH04287130A (en) Branching instruction optimizing system for base address system machine
JPH06282443A (en) Method and device for editing program
JPH02156332A (en) System for managing code shared between processes
JPH07219781A (en) Program translation device and its method
JPH06301549A (en) Program translation device
Charle'R et al. A DESIGN APPROACH FOR MULTIPLE PROCESSOR COMPUTERS
JPH08123692A (en) Method and device for register allocation
JP2002099424A (en) Compile method to use register in storage area
JP2002091778A (en) Device and method for converting program, and recording medium
JPS62202264A (en) Vector operation processing system