JPS63285668A - Vector load processing method - Google Patents

Abstract

PURPOSE:To shorten a period during which a vector register is occupied in order to hold the loaded vector data and to decrease the number of desired vector registers, by correcting a reference instruction so that the coincidence is secured between a vector register set at a loading destination and a reference vector register for the reference instruction. CONSTITUTION:A vector load instruction is detected and a reference instruction corresponding to said load instruction is retrieved. Then the vector load instruction is moved to a position close as much as possible to the reference instruction as long as the optimization is possible. Then more reference instructions are retrieved out of the subsequent intermediate code strings and a vector load instruction equivalent to the first vector load instruction is produced and put into a place near the reference instruction when a reference instruction is retrieved and can be optimized. This processing is continued for the intermediate code strings set within a prescribed range. Thus it is possible to secure the effect of optimization for decrease of the number of desired vector registers even when plural reference instructions are scattered in response to a single vector load instruction.

Description

[Detailed Description of the Invention] (Summary) This is a vector load processing method for optimization to reduce the required number of vector registers in computer compiler processing.

A vector load instruction is detected from the intermediate code string in the translation processing process, and the vector load instruction is moved to immediately before the first reference instruction among the instructions that refer to the loaded vector data, and immediately before the other reference instructions. generates and inserts vector load instructions for the same vector data, and modifies the reference instruction so that the vector registers to which they are loaded match the reference vector register of the reference instruction.

With this method, the period during which vector registers are occupied to hold loaded vector data is shortened, and the number of required vector registers can be reduced.

[Industrial application field]

The present invention relates to a processing method for a compiler that translates a computer program, and particularly to a vector load processing method for reducing the number of required vector registers.

[Conventional technology]

FIG. 3 is a block diagram showing an example of the configuration of a computer. By executing the program of the compiler 2, the processing device 1 translates the source program 4 stored in the storage device 3 and outputs the target program 5 to the storage device 6.

The source program 4 is, for example, a program written in the FORTRAN programming language, and the compiler 2 can generate from this source program a vectorized target program to be executed by a so-called vector processor.

For this purpose, in the compiler 2, the intermediate code generation unit 7 reads the source program 4, analyzes the program statements, generates an intermediate code string 10, and outputs it to the storage device 11.

When generating an intermediate code string, the compiler allocates a storage area for the data, and also detects parts that can be executed in parallel by a vector processor, such as in the processing of vector data.
In order to correspond to vector instructions executed by a vector processor, so-called vectorization is performed, and these are expressed as a predetermined intermediate code string.

Regarding this intermediate code string 10, the intermediate code optimization unit 8
executes an optimization process that changes the program to improve the execution efficiency of the target program, and the result is processed by the target program generation unit 9 to create a target program consisting of so-called machine language scalar instructions and vector instructions. is generated and output as the target program 5.

FIG. 4 shows an example of a source program written in the well-known FORTRAN language and an intermediate code string generated from the source program.

As is well known, the source program 17 shown in the figure increases the value of the subscript "■" by 1 from 1 to 100 for the two substitute sentences sandwiched between the DO statement and the CoNTINUE statement with the label "10". This is the content that specifies repeated execution.

Therefore, A(I), B(1) in the operands of the assignment statement
, C(I), --- data is typical vector data, so this program is vectorized into 2
, an intermediate code string 18 is generated.

Intermediate code string 18 days, rVLENG=100 J
B(*), C
Indicates each vector data of the specified number of elements in the format such as (*).

vtl, vt2, etc. indicate vector registers to be allocated from the vector processor, so for example rvtl
The intermediate code of the vector load instruction (hereinafter referred to simply as the vector load instruction, and the same applies to other intermediate codes), which is indicated by "=8 (book)", etc. Corresponds to a vector instruction to load vector register νt1.

Also, an intermediate code such as rvt3=vtl+vt2 J stores vector data, which is the result of addition between elements of vector data loaded into vector registers vtl and vt2 in a previous vector load process, in vector register vt3. Show that.

As is well known, a vector processor is a processing device that achieves high-speed processing by executing a large number of similar operations in parallel using a so-called pipeline calculation mechanism. It is necessary to perform vectorization to perform calculations on vector data with a large vector length.

To do this, it is necessary to install the necessary number of vector registers that can store the required number of elements of vector data specified by the VLHNG, but due to the hardware configuration of the vector processor, a storage device that can store data of, for example, 8192 elements is necessary. Divide into 8 pieces using
A vector register holding 024 element data, 8
If there are not enough pieces, divide it into 16 pieces and make up to 16 pieces each with 512 pieces.
If we use a vector register that holds element data and divide it into 32 vector registers in this way,
The number of data elements that can be held by each register is 256, and the number of data elements can be reduced to 128 by using 64 vector registers.

Generally, when it comes to programs that require complex operations, VL
The number of vector registers that are required at the same time and has the required vector length specified by ENG increases. the result,
In order to obtain the required number of vector registers, if the possible vector length becomes shorter, processing such as exchanging the contents of the vector registers during a series of operations becomes necessary, and as a result, the processing of the pipeline operation mechanism described above becomes shorter. A situation arises in which efficiency must be reduced.

Therefore, it is desirable to always take measures to reduce the number of required vector registers as much as possible, and a method of intermediate code optimization processing for this purpose is proposed in the patent application filed by the present applicant (Japanese Patent Application No. 61
-39673).

That is, in the optimization processing shown in FIG. 5, in processing step 20, the situation of the number of vector registers that will be simultaneously required within the effective range of the vector length specified by one VLENG is grasped, and in processing step 21, the intermediate code string is is scanned to detect one of the vector load instructions.

In processing step 22, the intermediate code following the detected vector load instruction is scanned to detect a vector operation instruction (hereinafter referred to as reference instruction) that references the vector register loaded by the vector load instruction, and the processing step 23, the required number of vector registers can be reduced by moving the vector load instruction to a position as close as possible before the referenced instruction, usually to the immediately previous position;
If possible, process step 24 moves the vector load instruction to that location.

Through this process, for example, intermediate code string 1 in FIG.
As in the case of vector load instruction 13 and reference instruction 14 in Example 2, the vector operation instruction that references the vector register (vtl in the example in the figure) loaded by the vector load instruction for the first time is separated from the vector load instruction. As shown in intermediate code string 15 of ra),
By moving the vector load instruction 13 to the position immediately before the reference instruction 14, the number of vector registers required in the program section 16 of the intermediate code string 13 can be reduced.

[Problem that the invention seeks to solve]

When the loop using the 00 statements in the source program to be vectorized becomes large-scale, there are often multiple reference instructions corresponding to one vector load instruction in the intermediate code string, and these instructions are scattered throughout the program. arise,
In such a case, there is a problem in that the effect of reducing the number of vector registers is limited and a sufficient effect cannot be expected if only the vector load instruction related to one reference instruction is moved by the optimization process described above.

[Means for solving problems]

FIG. 1 is a process flowchart showing the configuration of the present invention.

The figure shows the flow of optimization processing for reducing the number of required vector registers in the compiler, and 30 to 38 indicate processing steps.

[For production]

The compiler performs optimization processing to reduce the number of required vector registers for the intermediate code string in processing steps 30 to 34 in FIG. do,
If optimization is possible, move the vector load instruction as close to the reference instruction as possible.

Next, in processing step 35, a reference instruction is further searched from the subsequent intermediate code string, and if there is a reference instruction, processing step 36
In steps 38 to 38, if optimization is possible, a process is performed to generate a vector load instruction equivalent to the vector load instruction and insert it near the reference instruction, and the above process is performed for the intermediate code string in the required range. continue.

With the above processing method, even when a plurality of reference instructions corresponding to one vector load instruction are distributed, it is possible to increase the optimization effect of reducing the number of required vector registers.

〔Example〕

In the processing flow of FIG. 1, processing steps 30 to 34
are similar to each of the conventional processing steps 20 to 24, and as a result, if optimization to reduce the number of vector registers is possible, the vector load instruction is moved to the vicinity of the reference instruction.

Next, according to the present invention, in processing step 35, the search for a reference instruction is further continued in the intermediate code string following the reference instruction.

As a result of the search, if there is a reference instruction, the process ゛ In step 36, a vector load instruction equivalent to the detected vector load instruction is generated and inserted in an appropriate vicinity before the reference instruction. detects the vector register loaded by the vector load instruction,
It is determined whether the required number of vector registers can be reduced by eliminating the need for continued occupation even after the previous reference instruction.

As a result, if there is an effect of reducing the number of vector registers, a vector load instruction as described above is inserted in processing step 37.

A vector load instruction equivalent to the detected vector load instruction means a vector load instruction that loads the same vector data as the former, but the vector register to which it is loaded is not necessarily the same, and is inserted. An appropriate vector register is allocated to the load destination vector register of the vector load instruction generated for the purpose, taking into consideration the usage situation.

As a result, it is generally necessary to modify the reference instruction, and in process step 38 the corresponding vector register salt specified in the reference operand of the reference instruction is changed to the vector register salt assigned by the inserted vector load instruction.

After that, the process returns to processing step 35, and the above processing step 3
Processes 5 to 38 are repeated as long as there is a reference instruction, and in processing step 35, VL[! The remaining range of the intermediate code string within the effective range of the NG instruction is searched, and since there is no reference instruction, the process ends.

An intermediate code string 40 in FIG. 2 shows an example in which a plurality of reference instructions corresponding to a vector load instruction 41 are distributed as 42 to 44, and an intermediate code string 45 corresponds to the intermediate code string 40.
This is an example of the result updated by the optimization process described above.

In this example, it is assumed that optimization processing is determined to be effective for any reference instruction, and in the intermediate code string 45, the vector load instruction 41 is moved immediately before the reference instruction 42, and the vector load instruction 41 is moved immediately before the reference instructions 43 and 44. Vector load instructions 46 and 47, which are equivalent to the vector load instruction, are inserted, respectively.

The vector registers vtX % Vjy assigned appropriately are specified in the load destination vector registers of the vector load instructions 46 and 47 to be inserted, so one of the reference operands of the reference instructions 43 and 44 is respectively referenced accordingly. vt and vt, respectively, as shown in instructions 48.49.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, in a compiler that generates a vectorized target program, it is possible to improve the optimization effect of reducing the number of vector registers that are simultaneously required. This has a significant industrial effect in that it becomes possible to generate efficient target programs.

[Brief explanation of the drawing]

FIG. 1 is a process flowchart showing the configuration of the present invention, FIG. 2 is a diagram explaining the invention in detail, FIG. 3 is a block diagram of an example configuration of a computer, FIG. 4 is an explanatory diagram of an intermediate code string, FIG. 5 is a flowchart of conventional processing, and FIG. 6 is a diagram explaining an example of conventional processing. In the figure, 1 is a processing unit, 2 is a compiler, 3.6.1
1 is a storage device, 4.17 is a source program, 5 is a target program, 7 is an intermediate code generation unit, 8 is an intermediate code optimization unit, 9 is a target program generation unit, 10.12.15.18.40.45 is the intermediate code string,
20 to 24. 30 to 38 are processing steps. Fig. 1 is a process flow diagram showing the configuration of the present invention. Fig. 2 is a detailed explanation of the invention. Fig. 2 is a block diagram of an example of the configuration of a computer. Fig. 3 is an explanatory diagram of an intermediate code string. Figure 5: Flowchart of conventional processing

Claims (1)

[Scope of Claim] A compiler that translates a source program to generate a vectorized intermediate code string, and generates a target program by optimizing the intermediate code string, wherein vector data is generated from the intermediate code string. Detects a vector load instruction that loads the vector register into the vector register (30, 3
1) Move the vector load instruction to the vicinity of the first reference instruction among the instructions that refer to the vector data using the vector register (32 to 34), and move each reference instruction other than the first reference instruction. Insert a vector load instruction to load the vector data near each (35 to 3).
7) A vector load processing method, characterized in that the vector register referenced by each reference instruction is changed to match the vector register loaded by each inserted vector load instruction (38).