JPS6358558A - Garbage collection processing system - Google Patents

Garbage collection processing system

Info

Publication number
JPS6358558A
JPS6358558A JP20322586A JP20322586A JPS6358558A JP S6358558 A JPS6358558 A JP S6358558A JP 20322586 A JP20322586 A JP 20322586A JP 20322586 A JP20322586 A JP 20322586A JP S6358558 A JPS6358558 A JP S6358558A
Authority
JP
Japan
Prior art keywords
memory area
cell
information
address
register
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20322586A
Other languages
Japanese (ja)
Inventor
Kiminori Sato
Toshihiro Ozawa
Masanobu Yuhara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP20322586A priority Critical patent/JPS6358558A/en
Publication of JPS6358558A publication Critical patent/JPS6358558A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To perform the garbage collection processing at a high speed by omitting the storage of the point information to be given to the corresponding cell in a new memory area against an old memory area that stores no reference relation information.
CONSTITUTION: When the address information and the prescribed read/write signals received from an address register 4-1 are supplied to a main memory 1, the contents of an active cell in an old memory area are compressed and copied to a new memory area from the old memory area. At the same time, a bit operation control circuit 3 received the address information from a register 4-1 or a data register 4-2 supplies a prescribed address to a bit operation memory 2 and gives the accesses to the copy information and the reference relation information independently of the access of the cell main body and against the cell that gave an access to the memory 1. In this case, the reference relation information bit is turned on only to a cell to which plural cells have reference. At the same time, the value of a forwarding pointer is stored to rewrite the subsequent pointers.
COPYRIGHT: (C)1988,JPO&Japio
JP20322586A 1986-08-29 1986-08-29 Garbage collection processing system Pending JPS6358558A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20322586A JPS6358558A (en) 1986-08-29 1986-08-29 Garbage collection processing system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20322586A JPS6358558A (en) 1986-08-29 1986-08-29 Garbage collection processing system

Publications (1)

Publication Number Publication Date
JPS6358558A true JPS6358558A (en) 1988-03-14

Family

ID=16470524

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20322586A Pending JPS6358558A (en) 1986-08-29 1986-08-29 Garbage collection processing system

Country Status (1)

Country Link
JP (1) JPS6358558A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5075848A (en) * 1989-12-22 1991-12-24 Intel Corporation Object lifetime control in an object-oriented memory protection mechanism

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5075848A (en) * 1989-12-22 1991-12-24 Intel Corporation Object lifetime control in an object-oriented memory protection mechanism

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