JPS62136337U - - Google Patents
Info
- Publication number
- JPS62136337U JPS62136337U JP2491486U JP2491486U JPS62136337U JP S62136337 U JPS62136337 U JP S62136337U JP 2491486 U JP2491486 U JP 2491486U JP 2491486 U JP2491486 U JP 2491486U JP S62136337 U JPS62136337 U JP S62136337U
- Authority
- JP
- Japan
- Prior art keywords
- dot
- signal
- predetermined time
- driver circuit
- cpu
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 1
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 1
Landscapes
- Dot-Matrix Printers And Others (AREA)
Description
第１図は本考案プリンタの制御構成を示す回路
図、第２図及び第３図は同プリンタの動作を示す
タイミングチヤートである。
１：ＣＰＵ、２：ドライバー回路、３：制御回
路、４：制御信号発生回路、ＤＯＴ１〜ＤＯＴ７
：ドツト信号ライン、Ｒ１〜Ｒ７：抵抗、３Ａ：
共通ライン、Ｔｒ：スイツチングトランジスタ。
FIG. 1 is a circuit diagram showing the control structure of the printer of the present invention, and FIGS. 2 and 3 are timing charts showing the operation of the printer. 1: CPU, 2: Driver circuit, 3: Control circuit, 4: Control signal generation circuit, DOT 1 to DOT 7
: Dot signal line, R1 to R7 : Resistor, 3A:
Common line, Tr: switching transistor.
Claims (1)
個のドツト信号を出力するＣＰＵと、前記各ドツ
ト信号に対応したｎ個のドツトラインが接続され
て各ドツト信号に応じてソレノイドの駆動信号を
夫々出力するドライバー回路と、前記ＣＰＵより
出力されるドツト信号と同期して出力される信号
に応答して一定時間ｔだけ制御信号を発生する制
御信号発生回路と、前記制御信号に応答して一定
時間ｔだけ駆動ＯＮされるスイツチング手段を含
むと共に前記スイツチング手段のＯＮ，ＯＦＦ出
力で上記ＣＰＵとドライバー回路の間のｎ個のド
ツトラインを有効、無効に制御する前記ドツトラ
インに接続された制御回路を有し、前記制御回路
によりＣＰＵとドライバー回路の間のドツトライ
ンを、ドツト信号出力時から一定時間ｔだけ有効
にすると共に前記一定時間ｔの経過時に強制的に
無効に制御するように成したドツトプリンタの安
全装置。 n for printing specified characters, numbers, symbols, etc.
a CPU that outputs n dot signals, a driver circuit to which n dot lines corresponding to each of the dot signals are connected and outputs a solenoid drive signal in accordance with each dot signal, and a driver circuit that outputs a solenoid drive signal in accordance with each dot signal; a control signal generating circuit that generates a control signal for a predetermined time t in response to a signal output in synchronization with the signal; and a switching means that is driven ON for a predetermined time t in response to the control signal; It has a control circuit connected to the dot lines that enables or disables the n dot lines between the CPU and the driver circuit by ON/OFF output of the means, and the control circuit controls the n dot lines between the CPU and the driver circuit by the control circuit. A safety device for a dot printer, which is configured to enable a dot signal for a predetermined time t from when a dot signal is output, and forcibly disable it when the predetermined time t has elapsed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2491486U JPS62136337U (en) | 1986-02-21 | 1986-02-21 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2491486U JPS62136337U (en) | 1986-02-21 | 1986-02-21 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62136337U true JPS62136337U (en) | 1987-08-27 |
Family
ID=30824574
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2491486U Pending JPS62136337U (en) | 1986-02-21 | 1986-02-21 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62136337U (en) |
-
1986
- 1986-02-21 JP JP2491486U patent/JPS62136337U/ja active Pending