JPH0365911U - - Google Patents
Info
- Publication number
- JPH0365911U JPH0365911U JP12704689U JP12704689U JPH0365911U JP H0365911 U JPH0365911 U JP H0365911U JP 12704689 U JP12704689 U JP 12704689U JP 12704689 U JP12704689 U JP 12704689U JP H0365911 U JPH0365911 U JP H0365911U
- Authority
- JP
- Japan
- Prior art keywords
- output
- signal
- circuit
- time
- stepping motor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000010354 integration Effects 0.000 claims description 3
- 230000001934 delay Effects 0.000 claims 1
- 230000001360 synchronised effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
Landscapes
- Measurement Of Distances Traversed On The Ground (AREA)
Description
図面は本考案の一実施例を示すもので、第１図
は概略構成図、第２図はＤタイプフリツプフロツ
プのクロツク信号の初期値が「Ｈ」状態である場
合の各信号のタイムチヤート式説明図、第３図は
Ｄタイプフリツプフロツプのクロツク信号入力の
初期値が「Ｌ」状態である場合の各信号のタイム
チヤート式説明図である。
Ｃ……クロツク信号入力、Ｒ……リセツト信号
入力、Ｄ……データ信号入力、Ｑ……出力、ａ…
…スピードパルス、ｂ……駆動信号、ｃ……クロ
ツク信号、ｄ……ＯＮ信号、ｅ……データ信号、
ｆ……リセツト信号、ｇ……出力信号、ｓ……リ
セツト信号出力時間、ｔ……不安定時間、ｕ……
ＯＮ信号立ち上がり遅延時間、ｖ……リセツト立
ち上がり遅延時間、１……スピードパルス発生器
、２……駆動回路部、３……ステツピングモータ
式積算表示部、４……遅延回路、５……単安定回
路、６……ラツチ回路、７……接続個所、８……
接続個所、９……接続回路。
The drawings show one embodiment of the present invention, and FIG. 1 is a schematic configuration diagram, and FIG. 2 shows the timing of each signal when the initial value of the clock signal of the D-type flip-flop is in the "H" state. Figure 3 is a time chart diagram of each signal when the initial value of the clock signal input to the D-type flip-flop is in the "L" state. C...Clock signal input, R...Reset signal input, D...Data signal input, Q...Output, a...
...speed pulse, b...drive signal, c...clock signal, d...ON signal, e...data signal,
f...Reset signal, g...Output signal, s...Reset signal output time, t...Unstable time, u...
ON signal rise delay time, v...Reset rise delay time, 1...Speed pulse generator, 2...Drive circuit section, 3...Stepping motor type integration display section, 4...Delay circuit, 5...Single Stabilization circuit, 6... Latch circuit, 7... Connection point, 8...
Connection point, 9...Connection circuit.
Claims (1)
発生するスピードパルス発生器と、このスピード
パルス発生器から出力されるスピードパルスをス
ツテピングモータを駆動可能とする駆動信号に変
換する駆動回路部と、このステツピングモータと
スツテピングモータの駆動により廻動する積算計
とから成るステツピングモータ式積算表示部とを
備えたステツピングモータ式積算表示装置におい
て、前記スピードパルス発生器から出力されるス
ピードパルスに同期した信号をクロツク信号とし
て入力し、またイグニツシヨンスイツチがＯＮし
たことにより起励するＯＮ信号を遅延させる遅延
回路の出力をデータ信号として入力し、更に前記
ＯＮ信号を入力した単安定回路の出力をリセツト
信号として入力するＤタイプフリツプフロツプな
どのラツチ回路を更に備え、前記イグニツシヨン
スイツチをＯＮすることにより起励する前記単安
定回路から出力されるリセツト信号のリセツト信
号出力時間ｓをイグニツシヨンスイツチをＯＮし
たときから前記駆動回路部が正常に動作するまで
の不安定時間ｔより長い時間に設定し、前記遅延
回路のＯＮ信号立ち上がり遅延時間ｕを前記単安
定回路から出力されるリセツト信号のイグニツシ
ヨンスイツチをＯＮしたときから立ち上がるまで
のリセツト信号立ち上がり遅延時間ｖより長い時
間に設定し、前記ラツチ回路の出力Ｑを前記駆動
回路部のクロツク信号入力Ｃとの接続個所より出
力側の接続箇所にこの出力Ｑより出力される出力
信号がリセツト信号により設定される出力信号の
状態から反転したときに前記駆動信号をステツピ
ングモータ式積算表示部に出力する接続回路を介
して接続したことを特徴とするステツピングモー
タ式積算表示装置。 A speed pulse generator that generates a speed pulse every time the vehicle travels a certain distance; a drive circuit that converts the speed pulse output from the speed pulse generator into a drive signal that can drive the stepping motor; In a stepping motor type totalization display device comprising a stepping motor and a totalizer that rotates due to the driving of the stepping motor, the speed pulse output from the speed pulse generator is A synchronized signal is input as a clock signal, the output of a delay circuit that delays the ON signal excited when the ignition switch is turned ON is input as a data signal, and the monostable circuit to which the ON signal is input is input. It further includes a latch circuit such as a D-type flip-flop that inputs the output as a reset signal, and the reset signal output time s of the reset signal output from the monostable circuit excited by turning on the ignition switch. is set to a time longer than the unstable time t from when the ignition switch is turned on until the drive circuit unit operates normally, and the ON signal rise delay time u of the delay circuit is set to the time when the delay circuit is output from the monostable circuit. The output Q of the latch circuit is set to a time longer than the reset signal rise delay time v from when the ignition switch is turned on until it rises, and the output Q of the latch circuit is When the output signal outputted from this output Q is reversed from the state of the output signal set by the reset signal, it is connected to the connection point on the output side through a connection circuit that outputs the drive signal to the stepping motor type integration display section. A stepping motor type integration display device characterized by being connected.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12704689U JPH0650734Y2 (en) | 1989-10-30 | 1989-10-30 | Stepping motor type integrated display |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12704689U JPH0650734Y2 (en) | 1989-10-30 | 1989-10-30 | Stepping motor type integrated display |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0365911U true JPH0365911U (en) | 1991-06-26 |
| JPH0650734Y2 JPH0650734Y2 (en) | 1994-12-21 |
Family
ID=31674830
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12704689U Expired - Fee Related JPH0650734Y2 (en) | 1989-10-30 | 1989-10-30 | Stepping motor type integrated display |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0650734Y2 (en) |
-
1989
- 1989-10-30 JP JP12704689U patent/JPH0650734Y2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0650734Y2 (en) | 1994-12-21 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |