JPS62136072A - Manufacture of schottky barrier diode - Google Patents

Manufacture of schottky barrier diode

Info

Publication number
JPS62136072A
JPS62136072A JP27745485A JP27745485A JPS62136072A JP S62136072 A JPS62136072 A JP S62136072A JP 27745485 A JP27745485 A JP 27745485A JP 27745485 A JP27745485 A JP 27745485A JP S62136072 A JPS62136072 A JP S62136072A
Authority
JP
Japan
Prior art keywords
metal layer
barrier metal
substrate
bevel
insulating film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP27745485A
Other languages
Japanese (ja)
Inventor
Hirokazu Kaneda
金田 裕和
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP27745485A priority Critical patent/JPS62136072A/en
Publication of JPS62136072A publication Critical patent/JPS62136072A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To eliminate the irregularity of the circumference of a Schottky junction and stabilize the characteristics by a method wherein, after a barrier metal layer is formed over the whole surface of a semiconductor substrate, the substrate is formed into bevel by selective etching and the bevel slope is covered with an insulating film. CONSTITUTION:A substrate composed of an N<+> type silicon substrate 1 and an N-type epitaxial layer 2 deposited on the substrate 1 is employed. A barrier metal layer 5 composed of three layers of Mo, Ni and A is formed over the whole surface and subjected to sintering treatment. Then the center part of the barrier metal layer 5 only is covered with a resist film and the substrate is formed into bevel by etching. After that, an insulating film 3 is applied to the bevel slope 6 by, for instance, varnish coating. With this constitution, the barrier metal layer is not formed on a stepped part so that secure bonding between the barrier metal layer and the semiconductor substrate surface can be always obtained and the instability of the characteristics of a Schottky barrier diode can be eliminated.

Description

【発明の詳細な説明】[Detailed description of the invention] 【発明の属する技術分野】[Technical field to which the invention pertains]

本発明は、ショットキーバリアダイオード、特に大容量
のショットキーバリアダイオードの製造方法に関する。
The present invention relates to a method for manufacturing a Schottky barrier diode, particularly a large capacity Schottky barrier diode.

【従来技術とその問題点】[Prior art and its problems]

大容量のショットキーバリアダイオードの耐圧を高める
構造の例、とじて第2図+8!、 (bl、 (C1の
ようなものが連室されている。これらは逆電圧印加時に
バリア周辺に電界が集中することを避けるために、生ず
る空乏層の端部の基板面に角度をつける構造となってい
る。第2図+8!に示すものは、N゛シリコン基板1の
上に堆積したNエピタキシャル層2の表面を絶縁膜3に
よって覆い、その開口部からエツチングして凹部4を形
成したのち、バリア金属N5を被着して製造する。第2
図山)に示すものは、傾斜面を有する凹部4を形成し凹
部底面および傾斜面にバリア金属N5を被着して製造す
る。第2図(C1に示すものは、基Fi1およびエピタ
キシャルN2をメサ型に形成し、傾斜面6を絶縁膜3で
被覆後バリア金属層5を被着して製造する。 しかしこれらの場合、いずれもバリア金属層5を段差部
に被着するため、図中に符号Aで示したバリア金属層の
周辺部において、半導体N2にバリア金属が着きにくく
、ショットキー接合が不規則になり、素子特性が不安定
になるという欠点があった。
An example of a structure that increases the withstand voltage of a large-capacity Schottky barrier diode is shown in Figure 2 +8! , (bl, (C1) are connected to each other. These have a structure that angles the substrate surface at the end of the depletion layer to avoid concentration of the electric field around the barrier when a reverse voltage is applied. In the case shown in Fig. 2+8!, the surface of the N epitaxial layer 2 deposited on the N silicon substrate 1 is covered with an insulating film 3, and a recess 4 is formed by etching from the opening. Afterwards, barrier metal N5 is deposited and manufactured.Second
The one shown in Figure 1) is manufactured by forming a recess 4 having an inclined surface and coating the barrier metal N5 on the bottom surface and the inclined surface of the recess. The one shown in FIG. 2 (C1) is manufactured by forming the base Fi1 and the epitaxial layer N2 in a mesa shape, covering the inclined surface 6 with the insulating film 3, and then depositing the barrier metal layer 5. However, in these cases, Since the barrier metal layer 5 is deposited on the stepped portion, it is difficult for the barrier metal to adhere to the semiconductor N2 in the peripheral area of the barrier metal layer indicated by the symbol A in the figure, and the Schottky junction becomes irregular, resulting in poor device characteristics. The disadvantage was that it became unstable.

【発明の目的] 本発明は、傾斜面を有する半導体基体に形成されるシロソトキーバリア金属層周辺部において金属層と半導体基体との確実な接着ができ、ショットキー接合周縁部の不規則性をなくし、特性の安定したショットキーバリアダイオードを製造する方法を提供することを目的とする。 【発明の要点】[Purpose of the invention] The present invention enables reliable adhesion between the metal layer and the semiconductor substrate in the periphery of the Schottky barrier metal layer formed on the semiconductor substrate having an inclined surface, eliminates irregularities in the periphery of the Schottky junction, and improves the characteristics. The purpose is to provide a method for manufacturing a stable Schottky barrier diode. [Key points of the invention]

本発明によれば、半導体基体の表面に一面にバリア金属
層を被着後、選択エツチングによりヘベル成形し、ベベ
ル傾斜面を絶縁膜により被覆することによって、バリア
金属層の周辺部が金属層の被着後のエツチングにより形
成されるので、ショットキー接合周縁部の不規則性が生
ずることがなく、上記の目的が達成される。
According to the present invention, after a barrier metal layer is entirely deposited on the surface of a semiconductor substrate, it is bevel-formed by selective etching, and the beveled inclined surface is covered with an insulating film, so that the peripheral portion of the barrier metal layer is covered with the metal layer. Since it is formed by etching after deposition, irregularities in the Schottky joint periphery do not occur, and the above objective is achieved.

【発明の実施例】[Embodiments of the invention]

第1図は本発明の実施例を示し、従来と同IN”シリコ
ン基板1の上にNエピタキシャル層2を堆積した基体を
用い、先ずMo、 N+、 Auの3Nからなるバリア
金属層5を第1図(4)に示すように全面に被着し、シ
ンター処理をする0次いでバリア金属It!!5の中央
部のみをレジスト膜で覆い、エツチングすることにより
第1図(blに示すようにベベル成形したのち、例えば
フェスの塗布により絶縁膜3をヘベル傾斜面6の上に被
着する。 【発明の効果] 本発明は、空乏層の端部に設けられる傾斜面をバリア金
属層の半導体基体面への被着後に形成することにより、
段差部へのバリア金属層の被着がなくなるため、常に確
実なバリア金属層と半導体基体面との接着が得られ、シ
ョットキーバリアダイオードの特性の不安定を阻止する
ことができる。
FIG. 1 shows an embodiment of the present invention, using a substrate in which an N epitaxial layer 2 is deposited on the same IN'' silicon substrate 1 as in the conventional case, and first a barrier metal layer 5 made of 3N of Mo, N+, and Au is deposited. As shown in Figure 1 (4), only the central part of the barrier metal It!! 5 is covered with a resist film, which is coated on the entire surface and subjected to sintering, and then etched, as shown in Figure 1 (bl). After bevel forming, the insulating film 3 is deposited on the bevel inclined surface 6 by, for example, coating with a face.Effects of the Invention The present invention is advantageous in that the inclined surface provided at the end of the depletion layer is formed on the semiconductor layer of the barrier metal layer. By forming it after adhering to the substrate surface,
Since the barrier metal layer does not adhere to the stepped portion, reliable adhesion between the barrier metal layer and the semiconductor substrate surface can be obtained at all times, and instability in the characteristics of the Schottky barrier diode can be prevented.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例の工程を順次示す断面図、第
2図は従来の大容量ショットキーバリアダイオードの三
つの例を示す断面図である。 1:N’ シリコン基板、2:Nエピタキシャル層、3
:絶縁膜、5:バリア金属層、6;ヘベル傾斜面。 l−]・
FIG. 1 is a sectional view sequentially showing the steps of an embodiment of the present invention, and FIG. 2 is a sectional view showing three examples of conventional large-capacity Schottky barrier diodes. 1: N' silicon substrate, 2: N epitaxial layer, 3
: Insulating film, 5: Barrier metal layer, 6: Hevel slope. l-]・

Claims (1)

【特許請求の範囲】[Claims] 1)半導体基体の表面に一面にバリア金属層を被着後、
選択エッチングによりベベル成形し、ベベル傾斜面を絶
縁膜により被覆することを特徴とするショットキーバリ
アダイオードの製造方法。
1) After depositing a barrier metal layer all over the surface of the semiconductor substrate,
A method for manufacturing a Schottky barrier diode, characterized by forming a bevel by selective etching and covering the beveled inclined surface with an insulating film.
JP27745485A 1985-12-10 1985-12-10 Manufacture of schottky barrier diode Pending JPS62136072A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP27745485A JPS62136072A (en) 1985-12-10 1985-12-10 Manufacture of schottky barrier diode

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP27745485A JPS62136072A (en) 1985-12-10 1985-12-10 Manufacture of schottky barrier diode

Publications (1)

Publication Number Publication Date
JPS62136072A true JPS62136072A (en) 1987-06-19

Family

ID=17583805

Family Applications (1)

Application Number Title Priority Date Filing Date
JP27745485A Pending JPS62136072A (en) 1985-12-10 1985-12-10 Manufacture of schottky barrier diode

Country Status (1)

Country Link
JP (1) JPS62136072A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110215338A1 (en) * 2010-03-08 2011-09-08 Qingchun Zhang Semiconductor devices with heterojunction barrier regions and methods of fabricating same
US9231122B2 (en) 2011-09-11 2016-01-05 Cree, Inc. Schottky diode
US9236500B2 (en) 2013-09-10 2016-01-12 Hyundai Motor Company Schottky barrier diode and method for manufacturing schottky barrier diode

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110215338A1 (en) * 2010-03-08 2011-09-08 Qingchun Zhang Semiconductor devices with heterojunction barrier regions and methods of fabricating same
US9117739B2 (en) * 2010-03-08 2015-08-25 Cree, Inc. Semiconductor devices with heterojunction barrier regions and methods of fabricating same
US9595618B2 (en) 2010-03-08 2017-03-14 Cree, Inc. Semiconductor devices with heterojunction barrier regions and methods of fabricating same
US9231122B2 (en) 2011-09-11 2016-01-05 Cree, Inc. Schottky diode
US9865750B2 (en) 2011-09-11 2018-01-09 Cree, Inc. Schottky diode
US9236500B2 (en) 2013-09-10 2016-01-12 Hyundai Motor Company Schottky barrier diode and method for manufacturing schottky barrier diode

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