JPS62135008A - Phase shift circuit - Google Patents

Phase shift circuit

Info

Publication number
JPS62135008A
JPS62135008A JP27548485A JP27548485A JPS62135008A JP S62135008 A JPS62135008 A JP S62135008A JP 27548485 A JP27548485 A JP 27548485A JP 27548485 A JP27548485 A JP 27548485A JP S62135008 A JPS62135008 A JP S62135008A
Authority
JP
Japan
Prior art keywords
circuit
phase shift
signal
resistors
signal voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP27548485A
Other languages
Japanese (ja)
Other versions
JPH0520005B2 (en
Inventor
Toru Amamoto
天本 徹
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP27548485A priority Critical patent/JPS62135008A/en
Publication of JPS62135008A publication Critical patent/JPS62135008A/en
Publication of JPH0520005B2 publication Critical patent/JPH0520005B2/ja
Granted legal-status Critical Current

Links

Abstract

PURPOSE:To shift accurately an input signal by 90 deg. and to make the circuit suitable for circuit integration by setting the 1st, 2nd and 3rd resistors in response to the phase shift quantity so as to eliminate a DC bias cut-off capacitor. CONSTITUTION:Output terminals A, B of the 1st and 2nd signal voltage sources 12, 16 are connected through a series circuit comprising resistors R6, R7, and a connecting point C between the resistors R6 and R7 is connected to a base of a transistor (TR) Q1 of a differential amplifier circuit 13. A difference voltage of collector voltages extracted from Trs Q1, Q2 becomes a signal whose phase is shifted from that of an emitter AC voltage v' of a TR Q3 by 90 deg.. That is, a frequency signal generated by the 1st signal voltage source 12 is shifted by 90 deg. and outputted from output terminals 14, 15. Since the phase shift circuit uses no DC bias cut-off capacitor, an accurate phase shift is applied and the circuit is suitable for circuit integration.

Description

【発明の詳細な説明】 [発明の技術分野] この発明は例えばFM受信機等のクオドラチャ検波回路
に用いられる位相シフト回路に関する。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a phase shift circuit used in a quadrature detection circuit of, for example, an FM receiver.

[発明の技術的背景とその問題点] 従来より、FM受信機にはF M検波器としてクオドラ
チャ検波回路がよく用いられる。このクオドラチャ検波
回路は移相器により90°位相をずらした周波数変調波
と元の周波数変調波とを乗算器に入力し、その出力ビー
ト成分から復調信号を得るようにしたものである。特に
、上記移相器には通常インダクタし及びキャパシタCに
よるLC共振方式の位相シフト回路゛が用いられている
。ところが、このLC共振方式の位相シフト回路は外部
調整が必要であり、IC化には適さない。
[Technical background of the invention and its problems] Conventionally, a quadrature detection circuit is often used as an FM detector in an FM receiver. This quadrature detection circuit inputs a frequency modulated wave whose phase is shifted by 90 degrees by a phase shifter and an original frequency modulated wave to a multiplier, and obtains a demodulated signal from the output beat component. In particular, an LC resonance type phase shift circuit using an inductor and a capacitor C is usually used as the phase shifter. However, this LC resonance type phase shift circuit requires external adjustment and is not suitable for IC implementation.

そこで、従来より位相シフト回路の無調整化が図られて
いるが、その一つに第3図に示すような回路がある。こ
の位相シフト回路は抵抗R1〜R3及びセラミック共振
子CFで構成されるブリッジ回路11を用いたもので、
ブリッジ回路■lの一方の入力端aは信号電圧源12の
出力端に接続され、他方の入力端dはACグランドに接
続されている。
Therefore, attempts have been made to eliminate the need for adjustment in phase shift circuits, one of which is a circuit as shown in FIG. This phase shift circuit uses a bridge circuit 11 composed of resistors R1 to R3 and a ceramic resonator CF.
One input terminal a of the bridge circuit 1 is connected to the output terminal of the signal voltage source 12, and the other input terminal d is connected to AC ground.

このブリッジ回路11はR1−R2であり、またセラミ
ック共振子CFのインピーダンスをZS−jXsとして
R3=lZslに設定される。すなわち、ブリッジ回路
110入力端aに信号電圧源12からの周波数信号を供
給し、R1とR2、R3とCFの各接続点す、c間に現
れる電位差を差動増幅器(図示せず)によって取出すこ
とにより、90°位ト1」のずれた周波数信号を得るこ
とができる。
This bridge circuit 11 has R1-R2, and the impedance of the ceramic resonator CF is set to ZS-jXs, so that R3=lZsl. That is, the frequency signal from the signal voltage source 12 is supplied to the input terminal a of the bridge circuit 110, and the potential difference appearing between the connection points A and C of R1 and R2, R3 and CF is extracted by a differential amplifier (not shown). By doing this, it is possible to obtain a frequency signal shifted by about 90 degrees.

しかしながら、上記のような従来の位相シフト回路は、
実際には第4図に示すように構成され、以下の問題があ
る。すなわち、第4図においてトランジスタQl、Q2
、抵抗R4,R5及び定電流源11は差動増幅回路13
を構成するもので、その駆動電圧はDC電源電圧ライン
VCCから得ている。尚、トランジスタQl、Q2のコ
レクタは出力端子14.15に接続されており、ここか
ら90゜位相した周波数信号が得られるようになってい
る。
However, the conventional phase shift circuit as described above is
In reality, the configuration is as shown in FIG. 4, and there are the following problems. That is, in FIG. 4, transistors Ql, Q2
, resistors R4, R5 and constant current source 11 are a differential amplifier circuit 13.
The drive voltage is obtained from the DC power supply voltage line VCC. Note that the collectors of the transistors Ql and Q2 are connected to the output terminal 14.15, from which frequency signals having a phase of 90° can be obtained.

また、ブリッジ回路11の他方の入力端d(di。Further, the other input terminal d (di) of the bridge circuit 11.

d2)はACグランドとしての電源電圧ラインVCCに
接続されている。ここで、トランジスタQl、Q2のベ
ースのDCバイアスは信号電圧R12の信号電圧により
供給されており、抵抗R2はDC切離し用のコンデンサ
C1を介して電源ラインVCCに接続されている。つま
り、このコンデンサCIは位相が正確に90°シフトし
ない原因となっており、またIC化に関して上記コンデ
ンサC1は大きな面積が必要であるため、非常に不利で
ある。
d2) is connected to the power supply voltage line VCC as an AC ground. Here, the DC bias of the bases of the transistors Ql and Q2 is supplied by a signal voltage R12, and the resistor R2 is connected to the power supply line VCC via a DC isolation capacitor C1. In other words, this capacitor CI causes the phase to not shift by 90° accurately, and the capacitor C1 requires a large area when integrated into an IC, which is very disadvantageous.

[発明の目的コ この発明は上記のような問題を改善するためになされた
もので、DCバイアス切離し用コンデンサをなくし、正
確に入力信号を90’位相シフトさせることのでき、さ
らにIC化に適した位相シフト回路を提供することを目
的とする。
[Purpose of the Invention] This invention was made to improve the above-mentioned problems, and it is possible to eliminate the DC bias isolation capacitor, accurately shift the input signal by 90' phase, and is also suitable for IC implementation. The purpose of the present invention is to provide a phase shift circuit that has the following characteristics.

[発明の概要] すなわち、この発明に係る位相シフト回路は、第1の交
流周波数信号及びこの第1の交流周波数信号と逆位相の
第2の交流周波数信号を発生するMl及び第2の信号電
圧源と、これらの第1の信号電圧源の出力端及び第2の
信号電圧源の出力端間に接続した第1及び第2の抵抗で
なる第1の直列回路と、前記第1の信号電圧源と交流グ
ランド間に接続した第3の抵抗及びセラミック共振子で
なる第2の直列回路と、前記第1の直列回路の第1及び
第2の抵抗の接続点が一方の入力端に接続され、前記第
2の直列回路の第3の抵抗及びセラミック共振子の接続
点が他方の入力端に接続される差動増幅回路とを具備し
、前記第1及び第2及び第3の抵抗を位相シフト量に応
じて設定したことを特徴とするものである。
[Summary of the Invention] That is, the phase shift circuit according to the present invention includes Ml and a second signal voltage that generate a first AC frequency signal and a second AC frequency signal having an opposite phase to the first AC frequency signal. a first series circuit comprising a source, a first and a second resistor connected between the output terminal of the first signal voltage source and the output terminal of the second signal voltage source, and the first signal voltage source; A second series circuit including a third resistor and a ceramic resonator connected between the source and the AC ground, and a connection point between the first and second resistors of the first series circuit are connected to one input terminal. , a differential amplifier circuit in which a connection point between the third resistor and the ceramic resonator of the second series circuit is connected to the other input terminal, and the first, second, and third resistors are connected to each other in phase. It is characterized in that it is set according to the amount of shift.

[発明の実施例] 以下、第1図及び第2図を参照してこの発明の一実施例
を詳細に説明する。但し、第1図及び第2図において、
第3図及び第4図と同一部分には同一符号を付して示し
、ここでは異なる部分についてのみ述べる。
[Embodiment of the Invention] Hereinafter, an embodiment of the present invention will be described in detail with reference to FIGS. 1 and 2. However, in Figures 1 and 2,
The same parts as in FIGS. 3 and 4 are denoted by the same reference numerals, and only the different parts will be described here.

第1図はその基本構成を示すものである。この位相シフ
ト回路では第1及び第2の信号電圧源12゜1Gの各出
力端A、Bを抵抗Re、R7の直列回路を介して接続し
、さらに抵抗R8,R7の接続点Cを前記差動増幅回路
13のトランジスタQ1のベースに接続している。尚、
ここではトランジスタQ1のコレクタをり、)ランジス
タQ2のコレクタ及びベースをE、Fとする。
FIG. 1 shows its basic configuration. In this phase shift circuit, the output terminals A and B of the first and second signal voltage sources 12°1G are connected through a series circuit of resistors Re and R7, and the connection point C of resistors R8 and R7 is connected to the It is connected to the base of the transistor Q1 of the dynamic amplifier circuit 13. still,
Here, the collector of the transistor Q1 is denoted by E, and the collector and base of the transistor Q2 are denoted by E and F.

上記の構成において、その動作について説明すると、ま
ず上記第1及び第2の信号電圧源12.18の出力AC
電圧をv、−vとし、上記各接続点A〜Fに発生するA
C電圧をそれぞれvA =vPとし、抵抗Re、R7の
抵抗比をR8:R7−1:nとすると、 となる。また、セラミック共振子CFのインピーダンス
をZs−jXs(セラミック共振子は共振と反共振の間
を使う)とすると、 ・・・(2) となり、vD、vEの差電圧はv C+  v Fの差
に比例した電圧となる。したがって、n及びR3の設定
によって任意の位相シフト量が得られる。
In the above configuration, to explain its operation, first, the output AC of the first and second signal voltage sources 12 and 18 is
Let the voltages be v and -v, and A generated at each connection point A to F above.
Assuming that the C voltage is vA = vP, and the resistance ratio of the resistors Re and R7 is R8:R7-1:n, the following is obtained. Also, if the impedance of the ceramic resonator CF is Zs-jXs (ceramic resonator uses between resonance and anti-resonance), it becomes...(2), and the difference voltage between vD and vE is the difference between vC+vF The voltage is proportional to . Therefore, an arbitrary amount of phase shift can be obtained by setting n and R3.

第2図は実際の回路構成を示すもので、前記第1及び第
2の信号電圧源12.16から出力される各周波数信号
はそれぞれ入力端子17.18より位相シフト回路に入
力され、さらにカップリングコンデンサC2,C3を介
して第1及び第2のエミッタフォロワ増幅回路19.2
0に供給される。第1のエミッタフォロワ増幅回路19
はトランジスタQ3、抵抗R8及び定電流源■2で構成
され、トランジスタQ3のエミッタが前記接続点Aとな
っている。
FIG. 2 shows an actual circuit configuration, in which each frequency signal output from the first and second signal voltage sources 12.16 is inputted to a phase shift circuit through an input terminal 17.18, and further coupled to a phase shift circuit. First and second emitter follower amplifier circuits 19.2 via ring capacitors C2 and C3.
0. First emitter follower amplifier circuit 19
is composed of a transistor Q3, a resistor R8, and a constant current source (2), and the emitter of the transistor Q3 is the connection point A.

また、第2のエミッタフォロワ増幅回路20はトランジ
スタQ4、抵抗R9及び定電流源I3で構成され、トラ
ンジスタQ4のエミッタが前記接続点Bとなっている。
Further, the second emitter follower amplifier circuit 20 is composed of a transistor Q4, a resistor R9, and a constant current source I3, and the emitter of the transistor Q4 is the connection point B.

尚、前記抵抗Re、R7はR6:R7−1:3に設定さ
れる。また、前記抵抗R3はセラミック共振子CFのイ
ンピーダンスZS−jXsに等しく設定される。
Note that the resistances Re and R7 are set to R6:R7-1:3. Further, the resistor R3 is set equal to the impedance ZS-jXs of the ceramic resonator CF.

すなわち、第1及び第2の信号電圧源12.18がらの
各周波数信号を入力した時、各エミッタフォロワ増幅回
路19.20のトランジスタQ3.Q4の各エミッタA
C電圧をv−、−v″とすると、差動増幅回路13のト
ランジスタQl、Q2のベースにかかるAC電圧VBQ
I 、  VBQ21;1(11式より、となる。した
がって、トランジスタQl、Q2の出力電圧v l +
  v 2は、 v1纏jA4v′ v2−−jA−v− となる。但し、Aは差動増幅回路13の利得によって決
定される。このことかられかるように、トランジスタQ
1.Q2から取出される各コレクタ電圧の差電圧はV′
と90″位相のずれた信号となる。つまり、第1の信号
電圧源12で発生される周波数信号は90°位相シフト
されて出力端子14゜15から出力される。
That is, when each frequency signal from the first and second signal voltage sources 12.18 is input, the transistors Q3. Each emitter A of Q4
When the C voltage is v-, -v'', the AC voltage VBQ applied to the bases of the transistors Ql and Q2 of the differential amplifier circuit 13 is
I, VBQ21; 1 (from formula 11, it becomes. Therefore, the output voltage of transistors Ql and Q2 v l +
v2 becomes v1jA4v' v2--jA-v-. However, A is determined by the gain of the differential amplifier circuit 13. As can be seen from this, the transistor Q
1. The voltage difference between the collector voltages taken out from Q2 is V'
That is, the frequency signal generated by the first signal voltage source 12 is outputted from the output terminals 14 and 15 with a phase shift of 90 degrees.

したがって、上記のように構成した位相シフト回路はD
Cバイアス切離し用のコンデンサを用いないので正確な
位相シフトが可能となり、IC化にも適している。
Therefore, the phase shift circuit configured as above is D
Since a capacitor for C bias isolation is not used, accurate phase shifting is possible, and it is also suitable for IC implementation.

[発明の効果] 以上詳述したようにこの発明によれば、DCバイアス切
離し用コンデンサをなくシ、正確に入力信号を90”位
相シフトさせることのでき、さらにIC化に適した位相
シフト回路を提供することができる。
[Effects of the Invention] As detailed above, according to the present invention, it is possible to eliminate the DC bias isolation capacitor, accurately shift the phase of the input signal by 90'', and furthermore, it is possible to create a phase shift circuit suitable for IC implementation. can be provided.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの発明に係る位相シフト回路の一実施例を示
す基本回路構成図、第2図は同実施例の実際の回路構成
を示す回路図、第3図及び第4図はそれぞれ従来の位相
シフト回路の構成を示す回路図である。 11・・・ブリッジ回路、12・・・第1の信号電圧源
、13・・・差動増幅回路、14.15・・・出力端子
、1B・・・第2の信号電圧源、17.18・・・入力
端子、19.20・・・エミッタフォロワ増幅回路。 第1図 第2図
FIG. 1 is a basic circuit configuration diagram showing an embodiment of a phase shift circuit according to the present invention, FIG. 2 is a circuit diagram showing an actual circuit configuration of the same embodiment, and FIGS. FIG. 2 is a circuit diagram showing the configuration of a phase shift circuit. 11... Bridge circuit, 12... First signal voltage source, 13... Differential amplifier circuit, 14.15... Output terminal, 1B... Second signal voltage source, 17.18 ...Input terminal, 19.20...Emitter follower amplifier circuit. Figure 1 Figure 2

Claims (1)

【特許請求の範囲】[Claims] 第1の交流周波数信号及びこの第1の交流周波数信号と
逆位相の第2の交流周波数信号を発生する第1及び第2
の信号電圧源と、これらの第1の信号電圧源の出力端及
び第2の信号電圧源の出力端間に接続した第1及び第2
の抵抗でなる第1の直列回路と、前記第1の信号電圧源
と交流グランド間に接続した第3の抵抗及びセラミック
共振子でなる第2の直列回路と、前記第1の直列回路の
第1及び第2の抵抗の接続点が一方の入力端に接続され
、前記第2の直列回路の第3の抵抗及びセラミック共振
子の接続点が他方の入力端に接続される差動増幅回路と
を具備し、前記第1及び第2及び第3の抵抗を位相シフ
ト量に応じて設定したことを特徴とする位相シフト回路
first and second AC frequency signals that generate a first AC frequency signal and a second AC frequency signal that is in opposite phase to the first AC frequency signal;
a signal voltage source, and first and second signal voltage sources connected between the output terminal of the first signal voltage source and the output terminal of the second signal voltage source.
a first series circuit consisting of a resistor, a second series circuit consisting of a ceramic resonator and a third resistor connected between the first signal voltage source and AC ground; A differential amplifier circuit in which a connection point between the first and second resistors is connected to one input terminal, and a connection point between the third resistor and the ceramic resonator of the second series circuit is connected to the other input terminal. A phase shift circuit, characterized in that the first, second, and third resistors are set according to a phase shift amount.
JP27548485A 1985-12-07 1985-12-07 Phase shift circuit Granted JPS62135008A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP27548485A JPS62135008A (en) 1985-12-07 1985-12-07 Phase shift circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP27548485A JPS62135008A (en) 1985-12-07 1985-12-07 Phase shift circuit

Publications (2)

Publication Number Publication Date
JPS62135008A true JPS62135008A (en) 1987-06-18
JPH0520005B2 JPH0520005B2 (en) 1993-03-18

Family

ID=17556164

Family Applications (1)

Application Number Title Priority Date Filing Date
JP27548485A Granted JPS62135008A (en) 1985-12-07 1985-12-07 Phase shift circuit

Country Status (1)

Country Link
JP (1) JPS62135008A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5448196A (en) * 1993-04-21 1995-09-05 Kabushiki Kaisha Toshiba Phase shift circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5448196A (en) * 1993-04-21 1995-09-05 Kabushiki Kaisha Toshiba Phase shift circuit

Also Published As

Publication number Publication date
JPH0520005B2 (en) 1993-03-18

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