JPS62133732A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

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Publication number
JPS62133732A
JPS62133732A JP27335685A JP27335685A JPS62133732A JP S62133732 A JPS62133732 A JP S62133732A JP 27335685 A JP27335685 A JP 27335685A JP 27335685 A JP27335685 A JP 27335685A JP S62133732 A JPS62133732 A JP S62133732A
Authority
JP
Japan
Prior art keywords
film
oxide film
oxidation
silicon
silicon oxide
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP27335685A
Other languages
Japanese (ja)
Inventor
Shuichi Oya
大屋 秀市
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP27335685A priority Critical patent/JPS62133732A/en
Publication of JPS62133732A publication Critical patent/JPS62133732A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To prevent the reduction of an active region as well as to form the active region in accordance with the designed value by a method wherein a patterning is performed on a second oxidation-resisting film utilizing the eave generated on a silicon oxide film, and an interelement isolation region is formed by oxidation using said oxide film as a mask. CONSTITUTION:A first oxidation-resistant film 3 is formed on the surface of a semiconductor substrate 1, and a polycrystalline silicon film 4 of active region form is formed thereon by patterning. The whole body of the above-mentioned films is converted into a silicon oxide film 5 by oxidizing the silicon film 4. An oxide film 3 is removed by etching using the oxide film 5 as a mask. The second oxidation-resistant film 8 is formed on the whole surface of the substrate 1, and an oxide film 8 is left on the lower side only of the oxide film 5 by performing an anisotropic etching on the film 8. The oxide film 5 is removed by etching. A selective oxidation is performed on the surface of the substrate 1 using the left oxide films 3 and 8 as masks, and a thick silicon oxide film 9 is formed. As a result, the contraction of an active region is prevented, and the active region in accordance with the designed value can be formed.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置の製造方法に関し、特に素子間分離
領域の形成方法を改善した半導体装置の製造方法に関す
る。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device in which a method for forming an isolation region between elements is improved.

〔従来の技術〕[Conventional technology]

従来、半導体装置における素子間分離領域の形成方法と
してL OG OS (Local 0xidatio
n ofSilicon)法と呼ばれる技術が用いられ
ている。
Conventionally, LOGOS (Local Oxidation) has been used as a method for forming element isolation regions in semiconductor devices.
A technique called the nofSilicon method is used.

このI、ocos法は、シリコン基体の表面を選択的に
酸化することにより厚い酸化膜からなる素子間分離領域
を形成するものである。
This I,ocos method forms an interelement isolation region made of a thick oxide film by selectively oxidizing the surface of a silicon substrate.

簡単にこれを説明すれば、シリコン基体を熱酸化して薄
いシリコン酸化膜を基体表面に成長し、その上にシリコ
ン窒化膜を成長する。そして、活性領域以外の領域のシ
リコン窒化膜を選択的に除去し、ガードリングとしての
不純物を基体表面に拡散した後に、このシリコン窒化膜
をマスクとして基体表面を更に熱酸化して厚いシリコン
酸化膜を選択的に形成し、これを素子間分離領域として
構成する。この状態を第2図に示しており、11はシリ
コン基体、12は先に形成しているシリコン酸化膜、1
3は選択酸化用のマスクに用いたシリコン窒化膜、14
はガードリングそして15が形成された厚いシリコン酸
化膜からなる素子量分Nt ?it’f域である。
Briefly, a silicon substrate is thermally oxidized to grow a thin silicon oxide film on the surface of the substrate, and a silicon nitride film is grown on top of it. After selectively removing the silicon nitride film in areas other than the active region and diffusing impurities as a guard ring onto the substrate surface, the substrate surface is further thermally oxidized using this silicon nitride film as a mask to form a thick silicon oxide film. is selectively formed and configured as an element isolation region. This state is shown in FIG. 2, where 11 is the silicon substrate, 12 is the previously formed silicon oxide film, 1
3 is a silicon nitride film used as a mask for selective oxidation, 14
is the element amount Nt consisting of the thick silicon oxide film on which the guard ring and 15 are formed? It'f area.

なお、その後にシリコン窒化膜及び薄いシリコン酸化膜
を除去して活性領域の基体表面を商呈さ4、ごこに種々
の素子を形成することになる。
Thereafter, the silicon nitride film and the thin silicon oxide film are removed to expose the base surface of the active region 4, on which various elements will be formed.

(発明が解決しようとする問題点〕 上述した従来のり、 OCOS法では、マスクとしての
シリコン窒化膜を利用して自己整合的にガート−リング
及び素子間分離領域を形成できる点において有効であり
、これまで種々の半導体装置に利用されてきている。
(Problems to be Solved by the Invention) The conventional adhesive and OCOS methods described above are effective in that they can form guard rings and element isolation regions in a self-aligned manner using a silicon nitride film as a mask; Until now, it has been used in various semiconductor devices.

しかしながら、シリコン窒化膜をマスクとした基体表面
の熱酸化時に、マスクの両端からマスク内に向かう酸化
の進行を有効に防止することが難しいため、第2図に示
したように、素子量分M %N域15がマスク13の端
部よりも寸法7!2だけ内方に侵入し”ζしまう。この
ため、この寸法12の2倍だけ活性領域が縮小され、素
子の高集積化に不利となる。1ill常この侵入部分を
バースビークと称しているが、この寸法12は素子間分
離領域、つまり厚いシリコン酸化膜15の厚さの略半分
になるごとが判明している。したがって、この酸化膜の
膜厚を1μmとすると、バースビークは0.5μmとな
り、これらを両側に有する活14領域は1μmだけ縮小
されることになる。
However, during thermal oxidation of the substrate surface using a silicon nitride film as a mask, it is difficult to effectively prevent oxidation from proceeding from both ends of the mask toward the inside of the mask. The %N region 15 intrudes inward by a dimension 7!2 from the edge of the mask 13, resulting in "ζ".As a result, the active region is reduced by twice this dimension 12, which is disadvantageous for high integration of devices. This intrusion portion is usually called a birth beak, but it has been found that this dimension 12 is approximately half the thickness of the inter-element isolation region, that is, the thick silicon oxide film 15. Therefore, this oxide film If the film thickness of is 1 μm, the birth beak will be 0.5 μm, and the active 14 regions having these on both sides will be reduced by 1 μm.

最近の超LSIと称される半導体柴積回路においては1
μm前後の倣細なパターンが使用されるようになってき
ており、このような微細なパターンにおいて設計上の活
性領域パターンから製造−1−でlpm程度もパターン
の縮小が生じることばパターンの設計に大きな制約とな
る。
In recent semiconductor circuits called VLSIs, 1
Fine patterns on the order of μm have come to be used, and in the design of word patterns, such fine patterns can be reduced by as much as lpm from the designed active region pattern during manufacturing. This is a big restriction.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の半導体装置の製造方法は、設計パターンからの
活性領域の縮小がなくその設計の制約をなくして微細な
半導体装置に適した素子量分#領域の形成を可能とする
ものである。
The method of manufacturing a semiconductor device according to the present invention does not cause the active region to be reduced from the design pattern, eliminates restrictions on the design, and makes it possible to form #region with an element amount suitable for a minute semiconductor device.

本発明の半導体装置の製造方法は、半導体基体表面に少
なくとも第1の耐酸化膜を形成しこの上に活性領域形状
の多結晶シリコン膜をパターン形成する工程と、この多
結晶シリコン膜を酸化して全体をシリコン酸化膜に変換
する工程と、このシリコン酸化膜をマスクにして前記第
1の耐酸化膜をエツチング除去する工程と、半導体基体
全面に第2の耐酸化膜を形成しかつこれを異方性エツチ
ングして前記シリコン酸化膜の下側にのみ第2の耐酸化
膜を残す工程と、前記シリコン酸化膜をエツチング除去
する工程と、残された第1及び第2の耐酸化膜をマスク
として半導体基体表面を選択酸化して厚いシリコン酸化
膜を形成する工程とを含んでいる。
The method for manufacturing a semiconductor device of the present invention includes the steps of forming at least a first oxidation-resistant film on the surface of a semiconductor substrate, patterning a polycrystalline silicon film in the shape of an active region thereon, and oxidizing the polycrystalline silicon film. a step of converting the entire semiconductor substrate into a silicon oxide film; a step of etching and removing the first oxidation-resistant film using the silicon oxide film as a mask; forming a second oxidation-resistant film on the entire surface of the semiconductor substrate; A step of anisotropic etching to leave a second oxidation resistant film only under the silicon oxide film, a step of etching and removing the silicon oxide film, and a step of etching the remaining first and second oxidation resistant films. The method includes a step of selectively oxidizing the surface of the semiconductor substrate as a mask to form a thick silicon oxide film.

〔実施例〕〔Example〕

次に、本発明を図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図(a)〜(h)は本発明をMO5型半導体装置に
適用した実施例を工程順に示す断面図である。
FIGS. 1(a) to 1(h) are cross-sectional views showing, in order of steps, an embodiment in which the present invention is applied to an MO5 type semiconductor device.

先ず、同図(a)のように例えばP型導電型でかつ比抵
抗が10Ωcmの単結晶シリコン基体I上に熱酸化法に
より約300人のシリコン酸化膜2を成長し、その」−
に通常の気相成長法により第1の耐酸化膜としてのシリ
コン窒化膜3を100OAの厚さに、また多結晶シリコ
ン膜4を3000人の厚さに順次成長する。そして、フ
ォトリソグラフィ技術により前記多結晶シリコン膜4を
選択エツチングし、同図(b)のように活性領域に相当
する箇所にのみ多結晶シリコン膜4を残す。なお、選択
エツチングには例えば4塩化炭素ガスを用いたプラズマ
エツチング法を利用する。
First, as shown in Figure (a), about 300 silicon oxide films 2 are grown by thermal oxidation on a single crystal silicon substrate I of, for example, P-type conductivity and a specific resistance of 10 Ωcm.
Next, a silicon nitride film 3 and a polycrystalline silicon film 4 are sequentially grown to a thickness of 100 OA and a polycrystalline silicon film 4 to a thickness of 3000 Å, respectively, as a first oxidation-resistant film by a normal vapor growth method. Then, the polycrystalline silicon film 4 is selectively etched using a photolithography technique, leaving the polycrystalline silicon film 4 only in the area corresponding to the active region, as shown in FIG. 2(b). For the selective etching, for example, a plasma etching method using carbon tetrachloride gas is used.

次いで、前記多結晶シリコンII!4を1000℃のス
チーム雰囲気中で約3時間酸化し、同図(C)のように
多結晶シリコン1194を全て酸化させる。この酸化に
より、多結晶シリコン膜4は約6000人の厚さのシリ
コン酸化膜5に変換され、かつこの際の体積膨張によっ
てシリコン酸化膜5は上部が両側に張出してひさし6が
形成される。このひさし6の突出寸法りは元の多結晶シ
リコン膜4の厚さに略等しく、約0.3μmであること
が確認されている。
Next, the polycrystalline silicon II! 4 is oxidized for about 3 hours in a steam atmosphere at 1000° C., and all of the polycrystalline silicon 1194 is oxidized as shown in FIG. Through this oxidation, the polycrystalline silicon film 4 is converted into a silicon oxide film 5 having a thickness of about 6,000 wafers, and due to the volume expansion at this time, the upper part of the silicon oxide film 5 protrudes to both sides to form an eaves 6. It has been confirmed that the protruding dimension of this eaves 6 is approximately equal to the thickness of the original polycrystalline silicon film 4, which is approximately 0.3 μm.

次に、前記シリコン酸化膜5をマスクとして同図(d)
のように熱リン酸によって前記シリコン窒化膜3を、ま
た弗酸によって前記シリコン酸化膜2を夫々エツチング
する。この時、弗酸によってシリコン酸化膜5もシリコ
ン酸化膜2の厚さ300人に略等しい程度だけエツチン
グされるが、これは殆ど無視してもよい。その後、シリ
コン酸化Iり5を再度マスクに利用してP型不純物であ
るボロンを5 X 1012cm−2の濃度でイオン注
入して基体■にガードリング層7を形成する。
Next, using the silicon oxide film 5 as a mask, as shown in FIG.
The silicon nitride film 3 is etched with hot phosphoric acid, and the silicon oxide film 2 is etched with hydrofluoric acid, respectively. At this time, the silicon oxide film 5 is also etched by the hydrofluoric acid to an extent approximately equal to the thickness of the silicon oxide film 2 by 300 mm, but this can be almost ignored. Thereafter, using the silicon oxide I layer 5 as a mask again, boron, which is a P-type impurity, is ion-implanted at a concentration of 5.times.10@12 cm@-2 to form a guard ring layer 7 on the substrate (1).

次いで、同図(e)のように通常の減圧気相成長法によ
り第2の耐酸化膜としてのシリコン窒化膜8を200人
の厚さで全面に成長する。なお、このシリコン窒化膜8
はシリコン酸化膜5の下層の前記シリコン窒化膜3と一
体化される。そして、このシリコン窒化膜8をCF4系
のガスを用いた異方性の強いプラズマエツチング法でエ
ツチング除去すれば、同図(f)のようにシリコン酸化
膜5のひさし6の下側面及びこの陰になる部分のみにシ
リコン窒化膜8が残され、他の部分でシリコン酸化膜5
の上面やシリコン基体1の表面が露呈される。
Next, as shown in FIG. 4(e), a silicon nitride film 8 as a second oxidation-resistant film is grown over the entire surface to a thickness of 200 nm using a normal low pressure vapor phase growth method. Note that this silicon nitride film 8
is integrated with the silicon nitride film 3 below the silicon oxide film 5. If this silicon nitride film 8 is etched away by a highly anisotropic plasma etching method using a CF4 gas, the lower surface of the eaves 6 of the silicon oxide film 5 and this shadow are etched as shown in FIG. The silicon nitride film 8 is left only in the area where the
The upper surface of the silicon substrate 1 and the surface of the silicon substrate 1 are exposed.

その後、弗酸でシリコン酸化膜5をエツチング除去する
と、同図(g)のようにシリコン窒化膜8はシリコン窒
化膜3の両端において斜め」三方に突出したひさしとし
て残される。
Thereafter, when the silicon oxide film 5 is removed by etching with hydrofluoric acid, the silicon nitride film 8 is left as an eaves projecting obliquely in three directions at both ends of the silicon nitride film 3, as shown in FIG.

しかる上で、これらシリコン窒化膜3とシリコン窒化膜
8とをマスクとしてシリコン基体1を熱酸化法によって
酸化することにより、同図(h)のようにシリコン基体
1の表面に約1μmの厚いシリコン酸化膜9を素子間分
離領域として形成することができる。
Then, by oxidizing the silicon substrate 1 by thermal oxidation using the silicon nitride film 3 and the silicon nitride film 8 as masks, a thick silicon layer of about 1 μm is formed on the surface of the silicon substrate 1 as shown in FIG. Oxide film 9 can be formed as an element isolation region.

なお、その後シリコン窒化膜3.8及びシリコン酸化膜
2を順次エツチング除去した後、活性領域にMO3I−
ランジスタを形成することはこれまでと同様である。
Note that after the silicon nitride film 3.8 and the silicon oxide film 2 are removed by etching in sequence, MO3I- is etched in the active region.
Forming the transistor is the same as before.

この実施例によれば、活性領域の形状にパターニングし
た多結晶シリコン膜4をシリコン酸化膜5に変換するこ
とにより、活性領域の周囲に自己整合的に酸化膜のひさ
し6を形成でき、このひさし寸法に相当する分だけ非活
性領域側に進出させることができる。このため、この例
では厚いシリコン酸化膜9の酸化時にマスクとして機能
するシリコン窒化膜8は、本来の活性領域のシリコン窒
化膜3よりもひさし6寸法だけ外側に張出して形成され
ることになり、したがってこのシリコン窒化膜8をマス
クとして用いた厚いシリコン酸化膜9の酸化時には活性
領域に侵入しようとするバーズビークの発生を抑制し、
活性領域の実質的な縮小を解消することができる。
According to this embodiment, by converting the polycrystalline silicon film 4 patterned into the shape of the active region into the silicon oxide film 5, the oxide film canopy 6 can be formed in a self-aligned manner around the active region. It can be advanced toward the non-active region by an amount corresponding to the size. Therefore, in this example, the silicon nitride film 8, which functions as a mask during oxidation of the thick silicon oxide film 9, is formed so as to protrude outward from the silicon nitride film 3 in the original active region by the dimension of the eaves 6. Therefore, when oxidizing the thick silicon oxide film 9 using this silicon nitride film 8 as a mask, the generation of bird's beaks that try to invade the active region is suppressed.
Substantial shrinkage of the active area can be avoided.

この場合、シリコン窒化膜8が厚くなる程バーズビーク
の抑制効果は大きいが、程度を越えると熱酸化時の応力
集中が大きくなり接合リークの原因となる。本実施例の
場合、シリコン窒化膜8の厚さを約200人に設定して
おり、このため、シリコン基体lの表面を熱酸化して1
μmの厚さにシリコン酸化膜9を形成した結果、シリコ
ン窒化膜8のパターン端からのバーズビーク寸法11は
約C)、3μmに抑制でき、結局最初に形成したシリコ
ン窒化膜3と同し寸法の活性6NMを得ることかできた
。また、シリコン窒化膜8のこの程度の厚さでは接合リ
ークを生じることもない。
In this case, the thicker the silicon nitride film 8, the greater the effect of suppressing bird's beak, but if the silicon nitride film 8 becomes thicker, the stress concentration during thermal oxidation increases, causing junction leakage. In the case of this embodiment, the thickness of the silicon nitride film 8 is set to about 200, so the surface of the silicon substrate l is thermally oxidized to
As a result of forming the silicon oxide film 9 with a thickness of μm, the bird's beak dimension 11 from the pattern edge of the silicon nitride film 8 can be suppressed to approximately C), 3 μm, which is the same size as the silicon nitride film 3 formed first. It was possible to obtain active 6NM. Furthermore, with the silicon nitride film 8 having such a thickness, junction leakage does not occur.

なお、ガードリングを構成する不純物であるポロンもシ
リコン窒化膜8の外側に自己整合的に拡散されており、
その後の熱処理、酸化等の工程により活性領域中に侵入
することはない。
Note that poron, which is an impurity constituting the guard ring, is also diffused outside the silicon nitride film 8 in a self-aligned manner.
It does not invade the active region during subsequent steps such as heat treatment and oxidation.

なお、多結晶シリコン膜4の厚さによりひきし6の寸法
を変化でき、シリコン窒化膜8の厚さによりバーズビー
ク寸法を変化できるので、目的に応じてこれらの膜厚を
選択すればよい。
Note that the dimensions of the dimples 6 can be changed depending on the thickness of the polycrystalline silicon film 4, and the dimensions of the bird's beak can be changed depending on the thickness of the silicon nitride film 8, so these film thicknesses can be selected depending on the purpose.

ここで、本発明はMO3型半導体装置に限らずバイポー
ラ型半導体装置にも適用することができることは言うま
でもない。
Here, it goes without saying that the present invention can be applied not only to MO3 type semiconductor devices but also to bipolar type semiconductor devices.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、活性領域の形状にパター
ン形成した多結晶シリコンを酸化してシリコン酸化膜に
変換し、このシリコン酸化膜に生じたひさしを利用して
第2の耐酸化膜をパターニングし、この耐酸化膜を用い
て素子間分離領域を酸化形成しているので、素子間分離
領域の酸化端位置をひさし寸法だけ非活性領域側に後退
させることができ、これにより素子間分離領域によって
画成される活性領域の縮小を解消して設計値illりの
活性領域を形成することができ、倣細な半導体装置の製
造を実現できる。
As explained above, the present invention oxidizes polycrystalline silicon patterned in the shape of an active region to convert it into a silicon oxide film, and uses the eaves formed in this silicon oxide film to form a second oxidation-resistant film. Since the element isolation region is formed by patterning and oxidized using this oxidation-resistant film, the oxidized end position of the element isolation region can be set back toward the non-active region by the eaves dimension, thereby making it possible to isolate the element isolation region. It is possible to eliminate the shrinkage of the active region defined by the regions and form an active region that is larger than the design value, and it is possible to manufacture a semiconductor device with a fine pattern.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)〜(h)は本発明の一実施例を工程順に示
す断面図、第2図は従来方法における問題点を示す断面
図である。 1・・・シリコン基体、2・・・シリコン酸化111.
3・・・シリコン窒化膜(第1の耐酸化膜)、4・・・
多結晶シリコン膜、5・・・シリコン酸化膜、6・・・
ひさし、7・・・ガードリング、8・・・シリコン窒化
膜(第2の耐酸化膜)、9・・・厚いシリコン酸化膜(
素子間分離領域)、11・・・シリコン基体、12・・
・シリコン酸化膜、13・・・シリコン窒化膜、14・
・・ガードリング、15・・・素子間分離領域。 第1図 第1図 第1図 第2図
FIGS. 1(a) to 1(h) are cross-sectional views showing an embodiment of the present invention in the order of steps, and FIG. 2 is a cross-sectional view showing problems in the conventional method. 1... Silicon base, 2... Silicon oxide 111.
3... Silicon nitride film (first oxidation resistant film), 4...
Polycrystalline silicon film, 5... silicon oxide film, 6...
Eaves, 7... Guard ring, 8... Silicon nitride film (second oxidation resistant film), 9... Thick silicon oxide film (
(inter-element isolation region), 11... silicon substrate, 12...
・Silicon oxide film, 13...Silicon nitride film, 14.
... Guard ring, 15... Inter-element isolation region. Figure 1 Figure 1 Figure 1 Figure 2

Claims (1)

【特許請求の範囲】[Claims] 1、半導体基体表面に少なくとも第1の耐酸化膜を形成
しこの上に活性領域形状の多結晶シリコン膜をパターン
形成する工程と、この多結晶シリコン膜を酸化して全体
をシリコン酸化膜に変換する工程と、このシリコン酸化
膜をマスクにして前記第1の耐酸化膜をエッチング除去
する工程と、半導体基体全面に第2の耐酸化膜を形成し
かつこれを異方性エッチングして前記シリコン酸化膜の
下側にのみ第2の耐酸化膜を残す工程と、前記シリコン
酸化膜をエッチング除去する工程と、残された第1及び
第2の耐酸化膜をマスクとして半導体基体表面を選択酸
化して厚いシリコン酸化膜を形成する工程とを含むこと
を特徴とする半導体装置の製造方法。
1. Forming at least a first oxidation-resistant film on the surface of the semiconductor substrate, patterning a polycrystalline silicon film in the shape of an active region thereon, and oxidizing this polycrystalline silicon film to convert the entire film into a silicon oxide film. a step of etching away the first oxidation-resistant film using this silicon oxide film as a mask; and a step of forming a second oxidation-resistant film on the entire surface of the semiconductor substrate and anisotropically etching it to remove the silicon oxide film. A step of leaving a second oxidation resistant film only on the underside of the oxide film, a step of etching away the silicon oxide film, and selectively oxidizing the surface of the semiconductor substrate using the remaining first and second oxidation resistant films as a mask. and forming a thick silicon oxide film.
JP27335685A 1985-12-06 1985-12-06 Manufacture of semiconductor device Pending JPS62133732A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP27335685A JPS62133732A (en) 1985-12-06 1985-12-06 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP27335685A JPS62133732A (en) 1985-12-06 1985-12-06 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS62133732A true JPS62133732A (en) 1987-06-16

Family

ID=17526756

Family Applications (1)

Application Number Title Priority Date Filing Date
JP27335685A Pending JPS62133732A (en) 1985-12-06 1985-12-06 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS62133732A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5504034A (en) * 1992-09-23 1996-04-02 Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno Local oxidation method with bird's beak suppression

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5504034A (en) * 1992-09-23 1996-04-02 Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno Local oxidation method with bird's beak suppression

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