JPS62132292A - Address transition detecting circuit - Google Patents

Abstract

PURPOSE:To obtain the detecting pulse to secure a constant time from the change of a last address signal to the rear end of a pulse and to prevent an erroneous action by providing the fall and rise exclusive-use detecting circuit of an address signal composed of a latch circuit and a delaying circuit and synthesizing the output of respective detecting circuits. CONSTITUTION:The combination of a latch circuit 104 and a delaying circuit 105 is the same as the combination of a latch circuit 101 and a delaying circuit 102, and the signal of an address signal input terminal 108 is supplied through an inverter circuit 126 to a NAND circuit 117 of the latch circuit 104. By the combination of the latch circuit 104 and the delaying circuit 105, the rise of the signal of the address signal input terminal 108 is detected, and the pulse output is obtained from the output of a NAND circuit 118. Since a NAND circuit 124 in an output signal synthesizing circuit 107 inputs a signal line 130 to generate a fall detecting pulse and a signal line 135 to generate the transition detecting circuit, the pulse of a constant width corresponding to the fall and rise of an address signal is outputted.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention starts operation in response to a change in an address signal.
The present invention relates to a circuit for detecting a change in an address signal of a child circuit, particularly a half-quadruple memory integrated circuit, a so-called address transition detection circuit.

[Summary of invention O]

The present invention provides a detection circuit dedicated to the fall of the address signal consisting of a latch circuit and a delay circuit, and a detection circuit dedicated to the rise of the address signal 0 consisting of another latch circuit and delay circuit, and performs full synthesis of the outputs of each detection circuit. In addition, when a falling edge of the address signal is detected, the production circuit dedicated to rising is reset to the initial state, and conversely, when a falling of the address signal is produced, the V) production circuit dedicated to falling is reset. Is it possible to always space the next address signal change sufficiently apart? K so that it can be prompted under the same conditions as the address signal change when the
This is to obtain a detection pulse that secures a constant time at the trailing edge of the pulse from the last change in the address signal, that is, to realize an address transition production circuit that does not malfunction.

[Conventional technology]

Although there are some circuit differences, conventional address transition production circuits are basically a combination of an inverter-based delay circuit and an EXOR circuit O, as shown in Fig. It is configured to obtain a detection pulse of .

[Problems and objects to be solved by the invention] However, in the conventional circuit described above, as shown in the timing chart in Figure 9 (α), if the change in the address signal is sufficiently delayed, the design IM can be achieved. Although an output with a pulse width is obtained, as shown in Figure 9 (b) and Figure 9 (c), if the address goes high twice within a time shorter than the delay time of the delay circuit, the address transition detection circuit The pulse width may be narrower than the original design, and the temporal relationship between the final address signal change point and the trailing edge of the detection pulse ρ will be out of order, which may cause malfunctions of circuits that operate using this production pulse from now on. .

Therefore, the present invention solves this problem, and its purpose is to change the address signal to 7) lap K.
To provide an address transition producing circuit which not only provides a detection pattern immediately even if there is a change, but also always maintains a constant time interval from the last address change point to the trailing edge of a detection pulse υ.

[Means for solving problems]

The address transition detection circuit of the present invention includes a) a first latch circuit that inputs an address signal into a set terminal; 1 latch circuit ■Delay circuit 1 that supplies the reset terminal; C) address signal or output signal or internal signal of the first launch circuit;
Or the logic is modified by tN by the combination of the output signal or internal signal of the 1st ■ delay circuit @ 1 OI) set fK generation circuit and d) address 1g? Input the latch circuit of a2 which enters the set terminal and the output pin of the latch circuit of e) Mi mentioned above,
A second delay circuit supplies the delayed signal as an output to the reset terminal of the second V) latch circuit.

f) an address signal, or a second latch circuit 0 output signal, an internal signal, or a second delay circuit output signal lA is a second reset signal generation circuit whose logic is configured by a combination of internal signals 0; ) The output signal from the first latch circuit or the output signal from the first reset signal generation circuit l■ is input, and the output signal from the second latch circuit or the second reset signal is input. The output signal from the signal generation circuit is
an output signal synthesis circuit whose input is the output signal of the address transition detection circuit of the present invention, h) the first reset signal generation circuit; The output signal of the second reset signal generating circuit is supplied to both or at least one of the delay circuits of the first V) latch circuit, and the first V) latch circuit.
The special feature is that it is supplied to both or at least one of the delay circuits.

[Effect]

According to the above configuration of the present invention, the first countercircuit and the
The fall of the address signal O (
It detects the rise (rise) and creates a constant pulse width, and uses the combination of the second latch circuit and the 20th delay circuit O to make the rise (fall) of the address signal abrupt, and then creates a constant pulse width. The fall and rise 0 detection of the address signal is divided into separate circuits.
Furthermore, when the fall (rise) of the address signal is detected by the first latch circuit and the tenth delay circuit, the first reset signal generation circuit generates the second latch circuit and the second delay circuit. (
The falling edge) detection circuit is returned to its initial state so that it can immediately detect the rising edge (falling edge) of the address signal, and conversely, the second latch circuit and second delay circuit detect the rising edge (falling edge) of the address signal. Once detected, the second reset signal generation circuit returns the address signal falling (rising) detection circuit consisting of the first counter circuit and the first delay circuit to the initial state, and the address signal is immediately reset to the initial state. The address transition detection circuit of the present invention is prepared so that it can detect falling (rising) vc-, and the falling pulse and the rising pulse are synthesized by the output signal@r circuit. It outputs a pulse in immediate response to a change in the address signal, and it outputs a pulse that guarantees a constant intensity within the general range in response to any change in the address signal, and This is to keep the interval between the trailing edge of the output pulse and the last address change constant even if the output pulse passes through.

[Actual t@column]

FIG. 1 is a circuit diagram showing a tenth embodiment of VAJ according to the present invention. In FIG. 1, the circuit surrounded by a broken line 101 is the 117th circuit.
) Latch circuit, the circuit surrounded by broken line 102 is the first delay circuit, the circuit surrounded by broken line 103 is the first reset signal generation circuit, the circuit surrounded by broken line 104 is the second latch circuit, broken line 105 The circuit surrounded by 106 is a second delay circuit, the circuit surrounded by a broken line 106 is a second reset signal generation circuit,
The circuit surrounded by a broken line 107 is an output signal @r forming circuit. Further, the terminal 108 is an address signal input terminal, and the terminal 109 is an output terminal as an address transition detection circuit of the present invention. Latch (b) path 101ij NAND circuit 11
The first gate of the NAND circuit 110 is connected to the address signal input terminal 108, the second gate is connected to the output of the NAND circuit 111, and the first gate of the NAND circuit 111 is connected to the NAND circuit 111.
The output of circuit 101 is connected. The delay circuit 102 includes a NAND circuit 112, a NOR circuit 113, and a NAND circuit 114. The QNAND circuit 110 in the latch circuit 1010 is connected to the first gate of the NAND circuit 112 and the first gate of the BIAND circuit 114.
output is connected. The 1st gate of the NOR circuit 113 is connected to the output of the NAND circuit 112, and the 2nd gate of the NAND circuit 114 is connected to the 1st gate of the NAND circuit 112.

It is connected to the output of the R circuit 113. NAND circuit 1
The output of 14 is connected as a delay circuit output signal 129 to the DHAND circuit 1110 in the latch circuit 101. The reset signal generation circuit 103 is configured with a NOR circuit 115 and an inverter circuit 116. The first gate of the NOR circuit 115 is connected to the output of the latch circuit 101!7) NAND circuit 111, and the second gate is connected to the address signal input terminal 108.

The gate of the inverter circuit 116 is connected to the output of the NOR circuit 115. It is connected to the output of the gated NOR circuit 115 of the inverter circuit 116. The gate of the inverter circuit 126 is connected to the address signal input terminal 108 to generate an inverted address signal. The latch circuit 104 and the MAND circuit 117 perform NAND times % 1181
C Yotsu” C structure 5M.

And NANDU:! The first gate of JSho 117 is connected to the output of the inverter circuit 126, and the second gate is connected to N
connected to the output of the AND circuit 118, and connected to the output of the NAND circuit 11
80 first gate is connected to the output of the NAND circuit 117. The delay circuit 105 is a NAND circuit 119 and a NOR
It is composed of a circuit 120 and a NAND circuit 121. The first gate of NAND circuit 119 and NAND circuit 1
21!7) The first gate is N in the latch circuit 1040.
It is connected to the output of the AjID circuit 117. The NOR circuit 12(1)@1 gate is connected to the output of the 1JAlliD circuit 119. The second gate of NARD circuit 121 is connected to the NOR circuit 1200 output.

NAND[gl circuit 21 output is delay circuit output signal 13
4, NANIJ circuit 1 in the launch circuit 104
Connected to 18 ugly 2 gates. The reset signal generation circuit 106 includes a NOR circuit 122 and an inverter circuit 123.
It consists of The first gate of the R circuit 122 is connected to the NARD circuit 118v) output in the latch circuit 104, and the second gate is connected to the inverter circuit 126.
connected to the output of The inverter circuit 1230 input μNOR circuit 122v) is connected to the gate.

The output signal synthesis circuit 107 is composed of an AND circuit 124 and an inverter circuit 125.

The first gate of the NAND circuit 1240 is connected to the launch circuit 10.
The output of the θNAND circuit 111 in 1D is connected, and the DNAAND circuit 11 in the latch circuit 1047) is connected to the
8 outputs are connected. The gate of the inverter circuit 125 is connected to the output of the NAND circuit 124, and the output is connected to the output terminal 109 of the address transition injection circuit of the present invention.

The most important reset signal 13 of the reset signal generation circuit 103
The output of the NOR circuit 1157) is connected to the second gate of the delay circuit 105, and the output of the inverter circuit 116, which is the reset signal 132, is connected to the second gate of the delay circuit 105. 119 second
θNAND circuit 118 in the gate and latch circuit 104
It is connected to the third gate. Reset signal generation circuit 1
06's 10th reset 7th convention 136'e certain IJOR times m
The output of 122 is the θNOR circuit 113 in the delay circuit 102.
0 second gate VC connected, 20 reset is No. 137
``C: An inverter circuit 1230 output μ delay circuit 10
It is connected to the second gate of the IQIJAND circuit 112 in 2ρ and to the hemp 3 gate of the DHAND circuit 111 in the latch circuit 1olO. Also delay circuit 102.17 in 105C1
) NARD circuits 112, 114゜119, 121 respond slowly to a high level gate input signal and quickly respond to a low level 0 gate input signal. and the conductance constant Ilt of the N-channel MO8FEiT.

Also, delay circuit 102.10! The MD QNOR circuits 113 and 120 are set to respond slowly to a low-level 0 gate input signal and quickly to a high-level D gate input signal.

Now, in the above circuit, the latch circuit 101 and the delay circuit 1
The fall of the address signal 0 is detected by the 020 combination. In other words, if the address 1 word input terminal 108 is initially at a high level, the output signal of the NAND circuit 110 is 128μ low level, and the output of the MAND circuit 111 is No. 13.
0 ■ Sieve level, Nmu ND circuit 112 output is high level,
NOR circuit 1130 output low L/HELL, NA 1
1 D times i% l l 417) The output is at a high level 9th When the address D input terminal 108 changes to the 1 degree level, the output signal 128 of the NAND circuit 110 becomes a high level, but the NAND circuit 112 ．． MAID circuit 11
4 are designed to respond slowly to a high level gate input signal I/c, and the NOR circuit 113 is designed to respond slowly to a low level 0 gate input signal, so the HAND circuit 114') output The signal 129 remains at a high level ft for a delay time, and then changes to a low level. Therefore, the NAND circuit 111! 7) Output signal 1
30 changes to low level, and then, after a certain delay time, when the HAND circuit 1140 output signal 129 changes to low level VC, it changes to high level VC. Therefore, NARD circuit 111
The output signal 130 of the delay circuit 102T: When the address signal falls, a pulse output with a width corresponding to the set delay time is obtained. Latch circuit 104 and delay circuit 10
50 combination is the same as the latch circuit 101 and delay circuit 1020 combination, except that the signal at the address signal input terminal 108 passes through the inverter circuit 126 to the latch circuit 104.
With the combination of the latch circuit 104 and the delay circuit 105, the address store name input terminal 1080 detects the rising edge of the number 0 and MAID is supplied to the C1HAND circuit 117.
A pulse output is obtained from the circuit 118'7) output. 7) In the output signal synthesis circuit 1070, the NARD circuit 124 outputs a falling effect pulse and the output terminal 109 of the address transition effect circuit receives an address signal at the input O signal line 130 and the signal line 135ft that generates a rising ejection pulse. 0
9 or more, in which constant width O pulses corresponding to falling and rising edges are output, the time from the address signal change to the next O change is sufficiently longer than the delay time of delay circuits 102 and 105, that is, the basic FIG. 2 is a timing chart showing the waveforms of each signal in this basic case. Note that the numbers shown on the left of each waveform in FIG. 2 correspond to the numbers shown in the circuit υ of FIG. 1, and O indicates the signal waveform at each location. In addition, TATri indicates the time in the address D conversion ratio color weight ratio color output pulse, and 'no' indicates the pulse width. The operation of the address transition detection circuit O of the invention will be explained with reference to timing charts shown in FIGS. 3 and 4. Also in Figures 3 and @4, the numbers shown to the left of each waveform correspond to the numbers in the circuit of Figure 1, indicating the signal waveforms at each location. Figure 3 shows gIhP11'' when an address that once changed at the address signal input terminal 108 returns to its original state in a time shorter than the delay time of the delay circuit. Regarding changes, the circuit in Figure 1 uses separate circuits to produce the rising and falling changes of the address signal, so at the last change in the address D in Figure 3, the falling edge, the NAN
As shown in the timing chart of FIG. 3, the output signal 130, which is the output of the D circuit 111, has a constant output current without being affected by the previous state. The fc signal 1350 pulse that captures the first change in address 0 and the signal 1300 that captures the later change are combined to obtain a width D'rw, which is wider than TWO.Here, TW
l ■] The leading edge of cis0 corresponds to the first O change of address D, and the edge of pulse DI of TV corresponds to a time TA after the last change of address O.

Figure 4 shows that if the address that once changed at the address signal input terminal 108 returns to its original state within a time shorter than the delay time of the delay circuit, and then changes again, 0 operation is shown.
It is. Now, the latch circuit 104 and the delay circuit 1050 set, which are the rising 1 rising D production circuit, react to the first O address O rising ■ change IC and output an output pulse from the signal 135, but depending on the next 0 address D falling Di ratio, When the notch circuit 101 and the delay circuit 102D set output a falling θ ejection pulse from the signal 130, the reset signal generation circuit 103 generates a reset signal 131.1321 and outputs the latch circuit 10, which is a rising detection circuit.
4 and the delay circuit 105 is returned to its initial state, that is, it is brought into a state where it can immediately detect the next rising edge. Therefore, it is possible to respond normally to the change in the rising edge of the last address shown in Figure @4 even if the time from the previous address signal change is short. Therefore, the output terminal 1091C of the address transition detection circuit obtains an output having the width of the I curve of T- in FIG. Note that the leading edge of the pulse TV corresponds to the first change of the address signal, the vk edge corresponds to the first 0 change of the last 0 address signal, and the vk edge corresponds to the VC after a time TA has passed since the last change of the address signal. Compatible.

Note that in the circuit shown in Figure 1, the reset signal generation circuit 106
is a latch circuit 10 which is an address rise producing circuit.
4 and the delay circuit 105 detect the rising edge, and the signal 135
When a signal is output from the latch circuit 101 and the delay circuit 102t, which are falling detection circuits, are set to the initial state.

As described above, dedicated circuits are provided to match the latch circuit 101 and delay circuit 1020 pairs for detecting the falling edge of the address, and the pair of latch circuit 104 and delay circuit 105 for detecting the rising edge of the address. When the reset signal generation circuit 103 detects the latch circuit 104. ! : The delay circuit 105 was reset and a rising edge was detected. :Ra1 Since the latch circuit 101 and the delay circuit 102 are reset by the set fear generating circuit 106, it is possible to respond to short-time address changes without fail.

Moreover, it is possible to always maintain the interval between the trailing edge of the output pulse and the last address signal change to Tm.

Figure 5 is a circuit diagram showing the second embodiment of the present invention. The circuit in Figure 5 has the same basic configuration as the circuit in Figure 11.
7, and for use on the address signal,
Address signal or inverted signal? The ρ example is given to show that it is not an essential problem whether it is used or not.

FIG. 6 is a circuit diagram showing an embodiment of part 3 of the present invention. Figure 6 is r11Fi5t, which is the same as the basic VCCl2O circuit, and the difference is that the output signal synthesis circuit D2 (only the connection of the fixed gate O is changed; in the circuit shown in Figure 6, the reset signal generation circuit 1037) is different. ■Inverter circuit 116
The GO output and the output of the inverter circuit 1230 in the reset signal generation circuit 106 are used as input signals to the output signal @r formation circuit 6070. The circuit in the implementation column of FIG. 6 shows that it is not necessary to be particular about a specific V) signal as long as the signal has falling detection pulse and rising detection pulse O information as input to the output signal synthesis circuit 0. There is.

Fig. 7 is a circuit diagram showing an implementation row of the casing 4 of the present invention. Figure 7 basically has the same number of grooves as the O circuit in Figure 1, and the difference is in the O latch circuit 101') in Figure 1.
The reset input of the D circuit 1110 is the output signal 129 of the delay circuit 102 and the output signal 13 of the reset signal generation circuit 106.
However, in the circuit shown in FIG. 7, the reset input of the NAND circuit 711 in the latch circuit 701 is only the output signal of the delay circuit 702. Therefore, in the delay circuit 702, the NARD circuit 730 and the inverter circuit 7
31 is installed and the WAND circuit 730 ■ NAN is connected to the 1st gate.
The output of the D circuit 114 is connected, and the output of the middle D inverter circuit 123 of the reset signal generation circuit 106 is connected to the second gate. Furthermore, for the same reason, a HAND circuit 732 and an inverter circuit 733 are provided in the delay circuit 705. This figure 7! j! The circuit shown here consists of a latch circuit and a delay circuit.■It shows that there are various ways of resetting.

Also, although it is not shown in the circuit diagram, it goes without saying that *a may be used in any logical stage of the delay circuit in order to increase the delay time of the delay circuit, and that a special capacitor may be added. .

Furthermore, various circuit configurations can be used to generate the reset signal depending on each latch circuit and delay circuit.

〔Effect of the invention〕

As described above, according to the present invention, dedicated circuits are provided for the fall detection circuit and the rise detection circuit of the address signal, and when a fall is detected, the rise detection circuit is reset to return to the initial state, and when a rise is detected, the rise detection circuit is reset to the initial state. The falling detection circuit is reset, and each output signal is synthesized with a D pulse. This has the effect of always keeping the interval between the trailing edge of the pulse and the last 0 address change at a constant VC, that is, providing an address transition detection circuit that does not malfunction in response to any change in the address signal.

[Brief explanation of drawings]

Figure 1 is a circuit diagram showing an implementation column of the address transition detection circuit 1 of the present invention, and Figures 2, 3, and 4 are timing charts showing the operating waveforms of the circuit in Figure 1 in each case. Figure 5 is a circuit diagram showing the entire 20th main row of the present invention, Figure 6 is a circuit diagram showing the third implementation row of the present invention, and Figure 7 is a circuit diagram showing the 4th central cannon of the present invention. A circuit diagram showing columns, Figure 8 is a circuit diagram of a conventional address transition detection circuit, Figure 9 (α), (b)
, (C) is a timing chart showing the operating waveforms of the circuit in Figure 8. 101, 104, 701, 704... Latch circuit 102. 105, 702, 705... Delay circuit 103.
106...Reset signal generation circuit 107.607...Output signal synthesis circuit 108...Address signal input terminal 109...Address transition detection circuit output terminal 110.11
1,112,114,117,118.119,121
, 124,624,711.718. ff30,732
-・NAND circuit 113.115, 120.122-@
NOR circuit 116.123, 125, 126, 526, 527.7
31.733... Inverter circuit or above Applicant: Seiko Epson 7) Luz' 1. , a Noimi Socie Y No. 20 7) - 4 I3, υ0 kudzu,
5 Kasumi No. 6 Ato Shimata #$iomt=x! ,■ Seventh

Claims (1)

[Claims] (1) a) a first latch circuit that inputs an address signal to a set terminal; and b) an output signal of the first latch circuit that inputs the output signal and outputs the delayed signal to a reset terminal of the first latch circuit. c) an address signal or a first latch circuit; output signal or internal signal,
or a first reset signal generation circuit whose logic is configured by a combination of output signals or internal signals of the first delay circuit; d) a second latch circuit that inputs the address signal to the set terminal; and e) the second latch circuit. a second delay circuit that inputs the output signal of the second latch circuit and supplies the delayed signal as an output to the reset terminal of the second latch circuit; and f) an address signal or an output signal of the second latch circuit. Or an internal signal,
or a second reset signal generation circuit whose logic is configured by a combination of output signals or internal signals of the second delay circuit; and g) an output signal from the first latch circuit or the first reset. The output signal from the signal generation circuit is used as a first input, the output signal from the second latch circuit or the output signal from the second reset signal generation circuit is used as the second input, and the output is the address transition of the present invention. h) The output signal of the first reset signal generation circuit is supplied to both or at least one of the second latch circuit and the second delay circuit. An address transition detection circuit characterized in that the output signal of the second reset signal generation circuit is supplied to both or at least one of the first latch circuit and the first delay circuit.