JPS62131652A - Processor for isdn subscriber line signal - Google Patents

Abstract

PURPOSE:To improve the reliability of the entire signal processing unit by forming a signal processing circuit section physically as (n+1) or (n+2) spare constitution and making the connection between a subscriber line and the signal processing unit programmable. CONSTITUTION:In addition to elastic storage devices 111-1-111-j, k-set of elastic storage devices 112-1-112-k are provided. An optical subscriber line signal is connected to an optional channel of an optional Lap D processor (120-1-120-k). Similarly, an optional channel of an optional Lap D processor (120-1-120-k) is connected to an optional subscriber line signal. If any Lap D processor is faulty, a connection control information data in a control memory 115 of a time switch 114 is rewritten and assigned to a line of a Lap D processor not in use. Thus, the high reliability of the signal processing unit is attained.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an ISDN exchange, and particularly to a subscriber line signal processing device thereof.

(Prior Art) As for the ISDN exchange system, the CCI TT Recommendation Recommendations have been approved, and its practical use is progressing. The subscriber line signal processing device used in ISDN exchanges has been described in the paper 5E85-25 of the Institute of Electronics and Communication Engineers' Switching Study Group, titled "Prototype and Evaluation of RLSDN Subscriber Line Signal Processing Device (Part 1)" by Noh Nakamura. In the system described in this document, the correspondence between subscriber line signals and signal processing devices is unique.

More specifically, in Layer 2, D channels are multiplexed in a multiplex circuit as a line concentrator, and this multiplexed D channel signal is handled by a Lap D processor as a Layer 2 processing unit, which interfaces with Layer 3. is taken. In an ISDN switch, all signals are sent and received in frames. Therefore, it is not necessary to connect to a different signaling device for each call, or to connect subscriber signal lines to the east on an n-to-1 basis. Therefore, each subscriber line is always connected to the signal processing device.

(Problems to be Solved by the Invention) However, such a fixed configuration has the following problems in system reliability and maintainability. One is that since subscriber lines and signal processing equipment are directly connected, if the signal processing equipment fails, all subscribers included in that operating unit will be out of service. This is particularly important in a configuration in which the signal processing device performs multiple processing. Another reason is that the signal processing device does not have a preliminary circuit configuration.
The problem is that autonomous testing is not possible.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an ISDN subscriber line signal processing device that overcomes the drawbacks of the prior art and has improved system reliability and maintainability.

(Means for Solving the Problems) In order to solve the above-mentioned problems, the present invention provides a method for physically connecting the signal processing circuit section to n+1 or n in a signal processing device.
+2 backup configuration, and the connection between the subscriber line and the signal processing device is programmable.

(Function) According to the present invention, when one LapD processor in the signal processing circuit section becomes faulty, the connection between the subscriber line and the LapD processor is changed to replace the line accommodated in the faulty LapD processor. Allocate to other unused LapD processor lines. Tests between Lap D processors can be performed using free Lap D processor lines by connecting any Lap D processor in a time slot in a one-sided switching circuit. Tests between the Lap' D processor and the terminal are performed by connecting a vacant Lap D processor line to an arbitrary D channel using a switching circuit.

(Embodiment) Prior to detailed description of the present invention, an example of a conventional ISDN subscriber line signal processing device will be briefly described with reference to FIG.

As described in the above-mentioned document, a number of D channels (Dch) are multiplexed in layer 2 by a multiplexing circuit 210. The multiplex circuit 210 functions as a concentrator stage,
The multiplexed D channel signal is handled by a Lap D processor (SIG) 212 as a layer 2 processing unit. These are provided with n (n is a natural number) circuits. L
The signal processed by the ap D processor 212 is L2-
It is interfaced with layer 3 by L3 and M interface section 214. Signals are sent and received in frame units.

In this conventional example, each call is connected to a different signaling device, and the subscriber signal lines are not concentrated in an n-to-l ratio. Therefore, each subscriber line is always connected to the signal processing device. I keep it.

Next, an embodiment of the ISDN subscriber line signal processing apparatus according to the present invention will be described in detail.

Referring to FIG. 1, a subscriber line terminal (SLT) 10 is provided in an embodiment of the present invention. This system accommodates eight subscribers at the same time and has the function of separating communication information signals and subscriber line signals. output to the communication information signal line 11. The subscriber line signals are multiplexed by 8 and output to the subscriber line signal line 12 at 2 Mb/s. A plurality of subscriber line terminal devices 10 are added depending on the number of subscribers.

The communication information signal line 11 of the subscriber line terminal device 10 is connected to the input side of the network 20, and information signals are exchanged in the network 20. The output side of the network 20 is connected to a trunk terminal station (DST) 30.

The subscriber signal line 12 of the subscriber line terminal device IO is connected to the subscriber line signal processing device 100. The subscriber line signal processing device 100 has the function of performing call processing in accordance with signals input from the subscriber line signal line 12 and executing call path connections of the network 20. This call processing is controlled by a processor (cc) ao having layer 3 functionality.

As shown in FIG. 1, the subscriber line signal processing device 100 basically includes a single-sided switching circuit (MPX) 110;
Lap D processor (SIG) with k circuits (k is a natural number)
) 120-1 to 120-, and an interface control circuit (IFG) 130. A specific example of the configuration is shown in FIG.

Subscriber line signal lines 12-1 to 1 from subscriber terminal equipment 10
From 2-j to each elastic store (ES) 111-
1 to 111-j (j is a natural number), a 2 Mb/s highway obtained by multiplexing eight D channels is input. The highway format is shown in FIG. 3(a).

In addition to the elastic stores tit-1 to 111-j, in this embodiment, k (natural number) elastic stores 1
12-1 to 112-k are arranged. Elastic stores 111 and 112 are each 256-bit storage devices with elastic functionality. Highway data is read out from each elastic store at 8 MHz to the outputs 13-1 to 13-j and 14-1 to 14-k. The format is shown in FIG. 4(C). Therefore, 8 MHz, 8 bit information appears on the signal line 15, and its format is as shown in FIG. 4(d).

The signal line 15 is connected to a serial/parallel conversion circuit (S/P) 113. The serial-to-parallel conversion circuit 113 is a conversion circuit that outputs 8MH28-bit parallel information to its output 1B, and its format is as shown in FIG. 4(e).

In this embodiment, the input side of the serial/parallel conversion circuit 113 is configured to be able to accommodate eight sets of elastic stores 111-1 to 111-j and elastic stores 112-1 to 112-.

The output 16 of the serial-parallel conversion circuit 113 is a time switch (TS
W) Connected to 114. The time switch 114 is a time exchange switch that mutually exchanges 8-bit information between 1024 time slots, and connection control information data indicating which time slot a specific time slot is exchanged with is stored in a control memory (SON). ) 115.

The output 122 of the time switch 114 is connected to a parallel-to-serial conversion circuit (
P/S) is connected to other j elastic stores 119-1 to 119-j through 1lfl. The parallel/serial conversion circuit 118 converts the 8-bit parallel information from the time switch 114 into a serial signal and inputs the serial signal to the corresponding elastic stores till-1 to 119-j. These elastic stores 119-1 to 1ts-j are also 256-bit storage devices with elastic functions like the elastic stores 111-1 to 111-j, and in this embodiment, up to eight groups of errors are stored. Stick Store 119-1~119-8.119-9~11111
-16°, , , , 1111-57 to 119-64
It is divided into A 2 Mb/s highway is output from these outputs 17-1 to 17-j to the subscriber line terminal equipment IO. The output format is shown in FIG. 3(a).

The output 122 of time switch 114 is also connected to 8-bit parallel inputs to k 8-bit shift registers (SFTs) 117-1 through 117-. Outputs 18-1 to 18-k to each shift register 117-1 to 117-
From there, signals in the format shown in FIG. 3(b) are output to the Lap D processors 120-1 to +20-k.

Lap D processor 120-1-120- has output 1
1]-1 to 19-k, from which signals in the format shown in (b) are output to the elastic stores 112-1 to 112-k. Lap D processors 120-1 through 120- are also interfaced with processor 40 via interface control circuit 130.

Subscriber! The t1 terminal device 10 separates the subscriber line signal received from the subscriber line into a communication information signal and D channel information, and outputs the former to the communication information signal line 11 and the latter to the subscriber line signal line 12. do. The D channel information is multiplexed and input to each elastic store 111-1 to 111-j in the format shown in FIG. 3(a). Elastic stores 112-1 to 112-k also have Lap I
Signals in the format shown in FIG. 3(b) are input from the corresponding outputs 19-1 to 19-k of the I processors 120-1 to 120-. These elastic stores 112-1 to 112-j and 112-1 to 112-k
, signals in these formats are continuously input at a rate of 2 Nb/s. In this embodiment, the number of valid highway time slots input to elastic stores 111-1 to 111-k is 8, and the number of valid highway time slots input to elastic stores 112-1 to 112-k is 8. is 16.

For example, output 13-1 of elastic store 1111
From there, 8 bits are read out at 8 Nb/s in discrete bursts according to the timing shown at 13-1 in FIG. 3(c). In the same way, elastic store 111-
The D channel information is read out from elastic stores 112-2 to 111-4, and then 8 bits at a time are similarly read out at 8 Nb/s from elastic stores 112-2 to 112-4.

In this way, 8Nb/
s highway 15, and the serial/parallel conversion circuit 113
is input. As a result, elastic store 11
8 circuits 1-1 to 112-8 and 112-1 to 112
The outputs of the four circuits -4 are combined to obtain eight (7) 8 Nb/s, 128 time slot highways in the format shown in (d), which are input to the serial/parallel conversion circuit 113.

The serial/parallel conversion circuit 113 converts this input signal into an 8-pit parallel information signal string in the format shown in FIG. The nine columns of information signals correspond to a series of storage positions of the time switch 114, for example, from address O to 10
The data is stored sequentially in storage locations up to address 23.

In the time switch 114, this information string is read out in a random read format according to the connection control information stored in the control memory 115. As a result, the information signal string is exchanged to an arbitrary time slot within the 1024 time slots, and time exchange is performed.

The time-exchanged information signal string is on the one hand developed by the serial/parallel conversion circuit 118 into an 8-tree highway of 8 IHz and 128 time slots, and on the other hand is expanded into 8-tree highways of 128 time slots in shift registers 117-1 to 117-k. is input. In this embodiment, the output of the parallel-to-serial conversion circuit 116 is applied to a maximum of eight groups of elastic stores IHI-1 to 119-8.11.
9-13~11! It-16,,,,1111-57
~118-84 are connected separately. The output format is shown in FIG. 3(d).

8 elastic stores within each group, e.g. 119-
1-119-8. Writing operations to the elastic stores are performed in discrete bursts of 8 MHz and 8 pits, and the write operations are configured to have a phase shift of π/64 between each elastic store. This write timing matches that of 13-j (i is arbitrary) shown in FIG. 3(C).

The data is read out from the elastic stores 1111-1 to 119-j to outputs 17-1 to 17-j at a constant speed of 2 MHz.

The signal format is shown in FIG. 3(a), and the read timings are in the same phase.

Output 122 of time switch 114 is also input to shift registers 117-1 to 117-k. An arbitrary shift register 117-i latches the 8-bit output of the time switch 114 at the time slot output position 14-i (Fig. 3 [e]) in an arbitrary channel, and when the same time slot in the next channel is received. The latch data is shifted at a rate of 2 Nb/s up to the point where the latch data is shifted at a rate of 2 Nb/s, and is sequentially outputted from the output 18-1. The output format is shown in (b). The operations of the shift registers 117-1 to 117- are configured such that the phases thereof are shifted by π/$4 from each other. Lap D processors 120-1 to 120-
Similarly, although they are configured to operate in different phases from each other, there is no mutual relationship, so there is no effect. Outputs 18-1 to 18- to shift registers 117-1 to 117-
are input to the Lap D processors 120-1 to 120-k, and the outputs 19-1 to 19-k are shown in FIG. 3(d).
Elastic store 112-1 to 1 in the format
12-k.

With this operation, any elastic stores 111-1 to 111-j and 112-1 to 112-
The D channel information signal input to elastic stores 119-1 to 119-j and 120-1 to 1
It can be connected to any of 20-1 to 120-j.

Information indicating the correspondence between these input sides and output sides is stored in the control memory 115.
is accumulated in

From this we can say the following. First, any time slot of the highway, that is, any subscriber line signal received from any subscriber&l terminal device 10, is received from any Lap D
Processors 120-1 to 120-. k can be connected to any channel. Similarly, any channel of any Lap D processor 120-1 to 120- can be connected to any time slot of the highway output to any subscriber line terminal equipment 10, that is, to any subscriber line signal. can.

Next, any Lap D processor 120-1 to 120
- can be connected to any channel of any Lap[1 processor 120-1 to 120-.

This connection is a T1 stage non-block configuration.

In the illustrated embodiment, the time switch 14 has an 8 MHz, 10
It uses one with 24 time slots and has a one-page structure. Therefore, Lap Il processors 120-1~
The total number of channels that can be processed in 120- is a maximum of 512 channels in both directions.

Converting this into a film, we establish the following relationship between the number of Lap D processors and the number of subscriber signal channels to the number of D channels that they can handle.

That is, the number a of D channels that can be processed by one circuit of the Lap D processor and the switching circuit 11 shown in FIG.
0 switching capacity, there is a switching circuit 1 between the number of subscribers, that is, the number of D channels C, and the number d of Lap D processors.
10 has a bxb non-block configuration, the following relationships are established: d≦b/2a, C≦(d-1)xa, and C≦dxa-2.

Therefore, when a=1, d≦b/2. When c≦d-2a≧2, d≦b/2a, c≦(d-1)xa (1). With this configuration, the Lap D processor has the following characteristics: (1) It has at least one physical spare, and (2) There are at least two free D channels.

Usually, the Lap D processor is used as equipment on the station side.
In order to process pD, it is rare that only a single line is processed, and usually eight or more lines are often handled.

Therefore, according to this embodiment, when any Lap D processor becomes faulty, the connection control information data in the control memory 115 of the time switch 114 is rewritten, and the faulty Lap D processor is rewritten.
p The line housed in the D processor is transferred to an unused La
p can be assigned to the line of the D processor.

According to the above formula (1), the processing capacity of all Lap D processors is dxa, the number of lines used is (d-1)xa, and the failure La
Since the maximum number of lines handled by the pD processor is a, it is possible to process all subscriber line signals.

One failed Lap D processor is replaced with a normal one. Since there are at least two free lines including itself, these free lines can be used to conduct a test on the other side. In the worst case scenario, testing may occur between different channels in one's own Lap D processor. However, in order to avoid this situation and ensure that a test is performed with another LapD processor, equation (1) may be changed to c = (d-1)xa-1. These make the signal processing section highly reliable.

By the way, if c=axd, from the number of fits per Lap D processor circuit Fs, the failure rate per line FA
FA=Fsxdx(1/d)=Fs.

c=(d-1)xa+0 or c=(d-1)xa-
If it is set to 1, a failure will not occur unless a double failure occurs, so the failure rate FB is: FB=dC2x(1/d)xMTTRxFs/10. However, MTTR is 1 failure rate, which is the average time required to recover the Lap D processor. The ratio of FB and FA is: FB/FA = (d-1) x (1/2) x MTTR x Fs
xlO−”: 0, which is a negligible value.

In the case of a system in which the number of D channels C does not satisfy equation (1), the exchange capacity may be increased or the number may be divided so as to satisfy equation (1). In general, as the switching capacity increases, the proportion of common parts of the devices tends to increase, so it is better to install multiple signal processing devices with appropriate capacities than to increase the switching capacity of one switching circuit. This is preferable from the viewpoint of system reliability.

Therefore, in a system with such a configuration, the following test system can be constructed.

First, in a test between Lap D processors, LapD
If the processor supports LapD and
If the processors are connected to each other, they can communicate with each other using Lap D. Since the switching circuit 110 constitutes a single-sided switching system, as described above, any Lap
Connections are available between D processor time slots. This allows any Lap D processor to be tested using a free Lap D processor line.

In addition, for testing between a Lap D processor and a terminal, the switching circuit 110 can connect a vacant Lap D processor line to any D channel of any subscriber line terminal equipment 10, making it possible to test any terminal. It is.

By the way, in order to prevent potential failures in the backup circuit, when the number of D channels a is 2 or more, all Lap D processors are used to distribute the load, and when the number of D channels is 1, the load is distributed. , it is advantageous to perform periodic testing between free Lap D processors.

As described above, in this embodiment, the connection between the signal processing circuit unit that processes Lap D, that is, the Lap D processor, and the subscriber line signal, that is, the D channel, is changeable, that is, programmable, and the signal processing circuit unit Accordingly, an n+1 or n+2 backup method can be physically adopted. Therefore, the reliability of the signal processing device can be improved, and any L.
AP D processors and terminals can be tested.

(Effects of the Invention) As described above, according to the present invention, the signal processing circuit section physically takes the n+1 or n+2 backup system, thereby improving the reliability of the entire signal processing device.

Furthermore, any Lap D processor or terminal can be tested at any time using the spare Lap D processor line. Therefore, system reliability and maintainability are improved.

[Brief explanation of drawings]

FIG. 1 is an overall block diagram showing an embodiment of a switching system to which the I5IIN subscriber line signal processing device according to the present invention is applied, and FIG. 2 is a specific configuration of the subscriber line signal processing device shown in FIG. 1. FIG. 3 is a functional block diagram showing an example, and FIG. 3 is a format diagram showing the format of signals appearing in each part of the device in FIG. 2. FIG. 4 is a functional block diagram showing an example of a conventional ISDN subscriber line signal processing device. It is a similar overall block diagram. Explanation of symbols of main parts 10, , , , subscriber line terminal equipment 40, , , , processor 100, , , - subscriber line signal processing device 111.119
．． , Elastic store 114, , , Time switch 115, , , Control memory 117, , , Shift register 120, , Lap D processor Overall configuration of an exchange system to which the present invention is applied FIG.

Claims (1)

[Claims] 1. A subscriber line signal processing device applied to the ISDN switching system, which includes: input means for receiving and multiplexing D channels of subscriber line signals; a plurality of signal processing circuit means for processing LapD of the subscriber line signal; an output means for transmitting the subscriber line signal processed by the signal processing circuit means; and a subscriber line signal from the input means and the plurality of signals. switching means for connecting the plurality of subscriber line signals to the plurality of signal processing circuit means, the switching means being capable of changing the connection between the subscriber line signals and the plurality of signal processing circuit means; An ISDN subscriber line signal processing device characterized in that at least one of the signal processing means is provided as a backup, and at least two lines are available in the D channel. 2. In the apparatus according to claim 1, the exchange means includes a time switch means having a non-block single-page configuration, and exchange information specifying connection between the subscriber line signal and a plurality of signal processing circuit means. 1. An ISDN subscriber line signal processing device comprising: rewritable first storage means for storing . 3. The apparatus according to claim 2, wherein the input means includes a first input means for multiplexing D channels of subscriber line signals.
a second storage means having an elastic function for temporarily storing the multiplexed D channel signal; and a second storage means for multiplexing the output of the second storage means and outputting the multiplexed signal to the time switch means. An ISDN subscriber line signal processing device comprising: multiplexing means. 4. The apparatus according to claim 3, wherein the input means has a plurality of corresponding third circuits having an elastic function for temporarily accumulating subscriber line signals output from the plurality of signal processing circuit means. An ISDN subscriber line signal processing device comprising storage means.