JPH0750907B2 - ISDN subscriber line signal processor - Google Patents

Description

TECHNICAL FIELD The present invention relates to an ISDN exchange, and more particularly to a subscriber line signal processing device thereof.

(Prior Art) Regarding the ISDN exchange method, CCITT Recommendation I series has been approved and its practicality is being advanced. The subscriber line signal processing device used in the ISDN switch is conventionally published by Nakamura et al., "Prototype and Evaluation of ISDN Subscriber Line Signal Processing Device (Part 1)" IEICE Exchange Research Group Paper SE85-25. In the system described in this document, the correspondence between the subscriber line signal and the signal processing device is unique.

More specifically, in the layer 2, the D channels are multiplexed by a multiplexing circuit as a concentrating stage, and the multiplexed D channel signal is handled by a Lap D processor as the layer 2 processing unit and interfaces with the layer 3. Has been taken. In ISDN exchanges, all signals are transmitted and received in frames. Therefore, each call is not connected to a different signal device, or the subscriber signal lines are not concentrated to n: 1. Therefore, each subscriber line always maintains a connection with the signal processing device.

(Problems to be Solved by the Invention) However, in such a fixed configuration, there were the following problems in system reliability and maintainability. One is that since the subscriber line and the signal processing device are directly connected to each other, if the signal processing device fails, all the subscribers included in the operation unit are cut off. This becomes especially important in a configuration in which the signal processing device performs multiple processing. The other is that the signal processing device does not have a preliminary circuit configuration, and therefore it cannot be autonomously tested.

SUMMARY OF THE INVENTION It is an object of the present invention to solve the above drawbacks of the prior art and to provide an ISDN subscriber line signal processing device with improved system reliability and maintainability.

(Means for Solving Problems) In order to solve the above-mentioned problems, the present invention provides a signal processing device in which the signal processing circuit unit is physically n + 1 or n.
With a +2 backup configuration, the connection between the subscriber line and the signal processor is programmable.

(Operation) According to the present invention, when one Lap D processor in the signal processing circuit unit fails, the connection between the subscriber line and the Lap D processor is changed to accommodate the line accommodated in the failed Lap D processor. To other unused Lap D processor lines. The test between the Lap D processors can be performed in a time slot of an arbitrary Lap D processor in a one-sided switching circuit, whereby an empty Lap D processor line is used. Further, the test between the Lap D processor and the terminal is performed by connecting an empty Lap D processor line to an arbitrary D channel by a switching circuit.

(Embodiment) Prior to the description of an embodiment of the present invention, an example of a conventional ISDN subscriber line signal processing device will be described with reference to FIG. Although this is also described in the above-mentioned document, a large number of D channels (Dch) are multiplexed in the multiplexing circuit 210 in the layer 2. The multiplexing circuit 210 functions as a concentrating stage, and the multiplexed D channel signal is a Lap as a layer 2 processing unit.
Handled by the D processor (SIG) 212. These are provided in n (n is a natural number) circuits. The signal processed by the Lap D processor 212 is interfaced with the layer 3 by the L2-L3, M interface unit 214. The signal is transmitted and received in frame units.

In this conventional example, connection to a different signal device for each call is not performed, and subscriber signal lines are not concentrated to n: 1. Therefore, each subscriber line always maintains a connection with the signal processing device.

Next, an embodiment of the ISDN subscriber line signal processing apparatus according to the present invention will be described in detail.

Referring to FIG. 1, a subscriber line terminal equipment (SLT) 10 is provided in the embodiment of the present invention. It has a function of accommodating eight subscribers at the same time and separating communication information signals and subscriber line signals. The communication information signal is multiplexed for each speed and output to the communication information signal line 11 at 2 Mb / s to 8 Mb / s highway (HW). The subscriber line signal is multiplexed 8 times and output to the subscriber line signal line 12 at 2 Mb / s. A plurality of subscriber line terminal devices 10 are added according to the number of subscribers.

The communication information signal line 11 of the subscriber line terminal device 10 is a network
Connected to the ingress side of 20, the network 20 exchanges information signals. The output side of the network 20 is connected to a trunk line terminal equipment (DST) 30.

The subscriber signal line 12 of the subscriber line terminal device 10 is connected to the subscriber line signal processing device 100. Subscriber line signal processor 1
00 has a function of performing call processing according to a signal input from the subscriber line signal line 12 together with the processor 40, and executing a call path connection of the network 20. This call processing is controlled by a processor (CC) 40 having a layer 3 function.

As shown in FIG. 1, the subscriber line signal processing device 100 basically includes a switching circuit (MPX) 110 having a single plane structure and a k circuit (kX).
Is a natural number) Lap D processor (SIG) 120-1 to 120-k
And an interface control circuit (IFC) 130. FIG. 2 shows a specific configuration example thereof.

Subscriber line signal lines 12-1 to 12-j from the subscriber terminal device 10
From each elastic store (ES) 111-1 to 111-j
A highway of 2 Mb / s in which eight D channels are multiplexed is input to (j is a natural number). The highway format is as shown in FIG.

In addition to the elastic stores 111-1 to 111-j, in this embodiment, k (natural number) elastic stores 112-1 are stored.
.About.112-k are provided. Elastic Store 111
256 each with elastic function and 112
Bit storage device. The outputs 13-1 to 13-j, 14
In -1 to 14-k, highway data is read at 8 MHz from each elastic store. The format is as shown in FIG. 3 (c). Therefore, 8-MHz 8-bit information appears on the signal line 15, and its format is as shown in FIG. 3 (d).

The signal line 15 is connected to a serial / parallel conversion circuit (S / P) 113. The serial-parallel conversion circuit 113 is a conversion circuit that outputs 8 MHz 8-bit parallel information to its output 16 and has the format shown in FIG. 3 (e). In this embodiment, eight sets of such elastic stores 111-1 to 111-j and 112-1 to 112-k are provided on the input side of the serial-parallel conversion circuit 113.
It is configured to be able to accommodate groups.

The output 16 of the serial-parallel conversion circuit 113 is the time switch (TSW) 114.
It is connected to the. The time switch 114 is a time exchange switch for exchanging 8-bit information with each other for 1024 time slots, and the connection control information data indicating which time slot a specific time slot is exchanged with,
It is stored in the control memory (SCM) 115.

The output 122 of the time switch 114 is the parallel-serial conversion circuit (P / S) 1
Another 16 elastic stores 119-1 to 1 through 16
19-j. The parallel-serial conversion circuit 116 converts the 8-bit parallel information from the time switch 114 into a serial signal and inputs it to the corresponding elastic stores 119.1 to 119-j. These elastic stores 119-1 to 119
-J is also a 256-bit storage device having an elastic function similarly to the elastic stores 111-1 to 111-j, and in the present embodiment, a maximum of eight groups of elastic stores 119-1 to 119-8,119-. 9 ~ 119-16, ..., 119-57 ~
It is divided into 11964. From these outputs 17-1 to 17-j, a highway of 2 Mb / s is output to the subscriber line terminal device 10. The output format is as shown in FIG.

The output 122 of the time switch 114 is also connected to the 8-bit parallel inputs of the k 8-bit shift registers (SFT) 117-1 to 117-k. Each shift register 117-1 to 117
From the outputs 18-1 to 18-k of -k, signals of the format as shown in FIG.
Output to 120-k. Lap D processor 120-1 to 120-
k has outputs 19-1 to 19-k, and from them, signals of the format shown in (b) are output to the elastic stores 112-1 to 112-k. Lap D Processor 120-1
~ 120-k are also interfaced with processor 40 via interface control circuit 130.

The subscriber line terminal device 10 separates the subscriber line signal received from the subscriber line into a communication information signal and D channel information, the former as the communication information signal line 11 and the latter as the subscriber line signal line 12 Output to. The D channel information is multiplexed and is shown in FIG.
Each elastic store 111-1 in the format shown in
~ 111-j. See also Elastic Store 112
-1 to 112-k includes Lap D processors 120-1 to 120-k
The signals of the format shown in FIG. 3 (b) are input from the corresponding outputs 19-1 to 19-k of the. Signals in these formats are continuously input to the elastic stores 112-1 to 112-j and 112-1 to 112-k at a speed of 2 Mb / s. In this embodiment, the elastic store 11
The number of effective time slots of the highways input to 1-1 to 111-k is 8, and the elastic stores 112-1 to 1
The number of effective highway slots input to 12-k is 16.

For example, the output 13-1 of the elastic store 111-1 is read out at 8 Mb / s by 8 bits in discrete bursts in accordance with the timing 13-1 in FIG. 3 (c).
Elastic store 111-2 to 111-4
The D channel information is read from the memory, and then the elastic stores 112-2 to 112-4 similarly perform 8M for each 8 bits.
Reading is performed at b / s. In this way, the signals are multiplexed on the 8 Mb / s highway 15 of the format shown in FIG. 3 (d) and input to the serial / parallel conversion circuit 113. As a result, the eight circuits of the elastic stores 111-1 to 112-8 and the same 112-1
The outputs from the four circuits 112 to 112-4 are combined to obtain eight 8 Mb / s, 128 time slot highways in the format shown in FIG. 11D, which are input to the serial-parallel conversion circuit 113.

The serial-parallel conversion circuit 113 converts this input signal into an 8-bit parallel information signal string in the format shown in (e),
Input to output 16. This information signal sequence is the time switch 11
Data is sequentially stored in a sequential format in a series of 4 storage locations, for example, storage locations from 0 to 1023.

In the time switch 114, this information signal sequence is read in a random read format in accordance with the connection control information stored in the control memory 115. As a result, the information signal sequence is exchanged with an arbitrary time slot in the 1024 time slots, and time exchange is performed.

The time-exchanged information signal sequence is expanded by the serial-parallel conversion circuit 116 into eight highways of 8 MHz and 128 time slots on the one hand, and k shift registers 11 on the other hand.
It is input to 7-1 to 117-k. In the present embodiment, the output of the parallel-serial conversion circuit 116 is a maximum of eight groups of elastic stores 119-1 to 119-8, 119-9 to 119-16, ..., 119-57 to 11.
9-64 divided and connected. The output format is as shown in FIG. 3 (d).

8 elastic stores within each group, eg 119-1
The write operation to ~ 119-8, is performed in 8 MHz, 8-bit discrete bursts, and the phase of the write operation is shifted by π / 64 between the elastic stores. This write timing is shown in FIG. 3 (c).
It matches that of 13-i (i is arbitrary).

From the elastic stores 119-1 to 119-j, the respective outputs 17-1 to 17-j are read at a constant speed of 2 MHz. The signal format is as shown in FIG. 3 (a), and the read timings are in the same phase with each other.

The output 122 of the time switch 114 is also the shift register 117.
It is also input to -1 to 117-k. Any shift register 1
The 17-i latches the 8-bit output of the time switch 114 at the time slot output position 14-i (FIG. 3 (e)) on any channel, and latches the latched data until the reception of the same time slot on the next channel. Shift at 2Mb / s,
This is sequentially output from the output 18-i. The output format is as shown in FIG. Each shift register 11
The operations of 7-1 to 117-k are configured so that their phases are shifted from each other by π / 64. Lap D Processor 120-1 ~ 12
Similarly, 0-k is also configured to operate in different phases, but since it has no mutual relationship, it has no effect. The outputs 18-1 to 18-k of the shift registers 117-1 to 117-k are La
Input to pD processor 120-1 to 120-k and output 1
Input is made from 9-1 to 19-k to the elastic stores 112-1 to 112-k in the format shown in FIG. 3 (d).

By this kind of operation, any Elastic Store 11
D input to 1-1 to 111-j and 112-1 to 112-k
Channel information signals are stored in elastic stores 119-1 to 1
It can be connected to any of 19-j and 120-1 to 120-1 to 120-j. Information indicating the correspondence between the input side and the output side is stored in the control memory 115.

The following can be said from now on. First, any time slot of the highway received from any subscriber line terminal device 10,
That is, any subscriber line signal can be connected to any channel of any Lap D processor 120-1 to 120-k. Similarly, any channel of any Lap D processor 120-1 to 120-k is connected to any time slot of a highway output to any subscriber line terminal device 10, that is, any subscriber line signal. it can.

Next, any channel of any of the Lap D processors 120-1 to 120-k is connected to any of the Lap D processors 120-1 to 120-k.
Any channel of k can be connected. This connection has a T1 stage non-blocking configuration.

In the illustrated embodiment, the time switch 114 has 8 MHz and 1024 time slots, and has a single-sided structure. Therefore, the total number of D channels that can be processed by the Lap D processors 120-1 to 120-k is a maximum of 512 channels in both directions.

Generalizing this, the following relationship is defined between the number of Lap D processors and the number of subscriber signal channels with respect to the number of D channels that can be handled. That is, the number a of D channels that can be processed by one circuit of the Lap D processor, the exchange capacity b of the exchange circuit 110 shown in FIG. 1, the number of subscribers or D channels, and the number d of Lap D processors. If the exchange circuit 110 has a non-block structure of bxb, the relations of d ≦ b / 2a c ≦ (d−1) xa and c ≦ dxa−2 are defined between the two and.

Therefore, when a = 1, d ≦ b / 2, c ≦ d−2 When a ≧ 2, d ≦ b / 2a, c ≦ (d−1) xa (1) With this configuration, the Lap D processor is characterized by at least (1) physically having one or more spares, and (2) having at least two vacant lines in the number of D channels.

Normally, as the equipment on the station side, the Lap D processor rarely processes only a single line to process Lap D, and usually handles more than 8 lines. Therefore, according to the present embodiment, when one of the Lap D processors fails, the connection control information data in the control memory 115 of the time switch 114 is rewritten, and the line accommodated in the affected Lap D processor is not used. Can be assigned to the Lap D processor line.

According to the above equation (1), the processing capacity of all the Lap D processors is dxa, the number of used lines is (d-1) xa, and the number of lines handled by the faulty Lap D processor is a at the maximum. The power line signal can be processed.

The failed Lap D processor replaces it with a normal one. Since there are at least two or more free lines including itself, it is possible to perform a test on the opposite side using these free lines. In the worst case, a test may be performed between different channels in its own Lap D processor. However, in order to avoid this situation and always carry out the test with another Lap D processor, the equation (1) should be set to c = (d-1) xa-1. These improve the reliability of the signal processing unit.

By the way, when c = axd, the failure rate FA per line becomes FA = Fsxdx (1 / d) = Fs from the number of fits Fs per circuit of the Lap D processor.

If c = (d−1) xa + 0 or c = (d−1) xa−1, then no failure occurs unless a double failure occurs, so the failure rate FB is FB = _d C ₂ x (1 / d) xMTTRxFs is ^{2/10 9.} However, MTTR is the average time required to recover a failed Lap D processor. The ratio of both failure rates FB and FA is FB / FA = (d-1) x (1/2) xMTTRxFsx10 ^-9 0, which is a negligible value.

In the case of a system in which the number of D channels c does not satisfy the equation (1), the exchange capacity b may be increased or the division may be performed so as to satisfy the equation (1). In general, when the exchange capacity b is increased, the ratio of the common parts of the devices tends to increase. Therefore, rather than increasing the exchange capacity of one exchange circuit, it is better to install a plurality of signal processing devices of appropriate capacities.
It is preferable in terms of system reliability.

Therefore, in the system having such a configuration, the following test system can be constructed.

First, in the test between the Lap D processors, the Lap D processors support Lap D, and if the Lap D processors are connected to each other, the Lap D communication is possible with each other.
Since the exchange circuit 110 constitutes a one-sided exchange system,
As mentioned above, connections can be made between the time slots of any Lap D processor. By this, the empty Lap D
You can use the processor line to test any Lap D processor.

Also, for the test between the Lap D processor and the terminal,
Since the switching circuit 110 can connect the idle Lap D processor line to any D channel of any subscriber line terminal device 10, any terminal can be tested.

By the way, in order to prevent the potential failure of the backup circuit, when the D channel a is 2 or more, the load distribution is performed using all the Lap D processors, and the number of D channels is 1.
In that case, it is effective to perform a regular test between free Lap D processors.

As described above, in the present embodiment, the connection between the signal processing circuit unit that processes Lap D, that is, the Lap D processor and the subscriber line signal, that is, the D channel is changeable, that is, programmable, and the signal processing circuit unit Can physically take the n + 1 to n + 2 standby scheme. Therefore, the reliability of the signal processing device can be improved, and the backup Lap D
The processor line can be used to test any Lap D processor or terminal at any time.

(Effect of the Invention) As described above, according to the present invention, the signal processing circuit unit physically adopts the n + 1 to n + 2 standby system, and thereby the reliability of the entire signal processing apparatus is improved. Also a spare Lap
You can test any Lap D processor or terminal at any time using the D processor line. Therefore,
System reliability and maintainability are improved.

[Brief description of drawings]

FIG. 1 is an overall block diagram showing an embodiment of a switching system to which an ISDN subscriber line signal processing device according to the present invention is applied, and FIG. 2 is a concrete configuration example of the subscriber line signal processing device shown in FIG. FIG. 3 is a functional block diagram showing the format of a signal appearing in each part of the apparatus of FIG. 2, and FIG. 4 is the same as FIG. 1 showing an example of a conventional ISDN subscriber line signal processing apparatus. FIG. Explanation of symbols of main parts 10 ... subscriber line terminal device 40 ... processor 100 ... subscriber line signal processing device 111, 119 ... elastic store 114 ... time switch 115 ... control memory 117 ... shift register 120 ...... Lap D processor

Claims (1)

[Claims] 1. A subscriber line signal processing apparatus applied to an ISDN switching system, wherein the apparatus includes input means for receiving and multiplexing a D channel of a subscriber line signal, and the multiplexed subscriber line signal. A plurality of signal processing circuit means for processing Lap D and a processing means for controlling call processing in the subscriber line signal processing device, and sends the subscriber line signal processed by the signal processing circuit means, Input / output means for sending a control signal from the processing means, and a switch for connecting the subscriber line signal output from the input means to any of the plurality of signal processing circuit means based on the control signal. Means and output means for outputting the subscriber line signal exchanged by the exchange means and processed by the signal processing means, wherein the input means temporarily stores the D channel of the subscriber line signal. And output to the exchange means A first accumulating means having a rustic function, and a second accumulating means having an elastic function for temporarily storing the D channel of the subscriber line signal output from the plurality of signal processing circuit means and outputting the D channel to the exchanging means. And means,
The D channels of the subscriber line signals output from the first accumulating means and the second accumulating means are multiplexed and supplied to the exchanging means, and the exchanging means includes the first accumulating means and the second accumulating means. An ISDN subscriber line signal processing device, characterized in that the subscriber line signal output from the storage means is time-exchanged and connected to an arbitrary channel of the output means and the plurality of signal processing circuit means.