JPS62131347A - Hold time monitor circuit - Google Patents

Abstract

PURPOSE:To prevent a main processor from being in the hold state for a long time to break down a system by monitoring the hold time of the main processor by a timer which generates a time-up signal after a prescribed time. CONSTITUTION:A timer means 103 discriminates the hold start of a main processor 101 in accordance with the output of AND between a hold request signal from a subprocessor 102 to the main processor 101 and a hold response signal, which is outputted from the main processor 101 to the subprocessor 102 in response to the hold request signal, to start measuring the hold time, and the time-up signal is generated and is supplied to a reset signal generating means 104 when a prescribed hole monitor time elapses. The reset signal generating means 104 resets the subprocessor, which issues the hold request signal, on a basis of this time-up signal.

Description

[Detailed Description of the Invention] [Summary] In a system in which a main processor and a sub-processor are connected via a common path, a timer is provided to monitor the duration of a hold request from the sub-processor to the main processor. A time-up signal is generated when a predetermined time period is exceeded, and based on this signal, the sub-processor is reset to terminate the hold request, thereby preventing the main processor from being held continuously for a long period of time, resulting in system down. At the same time, an interrupt signal is supplied to the main processor to notify the main processor of the occurrence of an abnormality based on the time-up of the hold time.

[Industrial application field]

The present invention relates to a circuit for monitoring the time of a hold request to a processor, and more particularly to a hold time monitoring circuit in a system that transfers the right to use a common path between a plurality of processors using a hold request/response method.

In a system where multiple processors are connected to a common path and share information resources such as input/output devices and storage devices connected to this path, there is a method of giving and receiving the right to use the common path using the hold request/response method. However, in this case, the hold request by the requesting processor is not released, so it is desirable to be able to prevent the main processor from being held for a long time.

FIG. 5 shows an example of the configuration of a conventional hold time monitoring circuit. In the figure, 1 is a common path, 2 is a main processor (MPU), 3 is a sub processor (SPU),
4 is a storage device, 5 is an input/output device, and 6 is a watchdog tire (VDT).

In FIG. 5, when 5PU3 requests permission to use a certain shared resource, it issues a hold request signal S1 to MPU2. MPU2 that received the hold request signal S1
returns the hold response signal S2 and enters the hold state. Thereafter, the 5PU5 that has issued the hold request uses the shared resource via the common path. After use, 5PU3 cancels the hold request signal S1, so that the MPU
2 continues the operation before the hold. VDT6 is MPU
2, it is reset by WDT reset a number S6 that occurs within a certain period of time, but within this time the VDT
When the Ij set signal is not generated, a VDT time-up signal S4 is generated to interrupt the MPU2.

In the system shown in Figure 5, for some reason now S
If it becomes impossible to release the hold request, such as when PU 5 stops during a hold request, fJ & 6
As shown in the time chart in the figure, the VDT 6 monitors whether a reset operation has been performed within a certain WDT monitoring time and generates an interrupt to the MPU 2 in the event of an abnormality. This prevents the risk of system failure due to continuous hold.

[Problems to be Solved by the Invention] In the conventional hold time monitoring circuit shown in FIG.
Protection is provided by monitoring the reset operation of the PU2 and generating an interrupt when an abnormality occurs. However, if the MPUZ itself is in a hold state, the interrupt process itself cannot be executed, and a system failure is inevitable. Also, is the occurrence of an interrupt caused by WDT 6 caused by a runaway of MPU2?
Alternatively, since it is necessary to determine whether the problem is caused by a long-time hold by the 5PU3, there are problems such as an increase in the overhead of interrupt processing.

The lead time monitoring circuit is connected to the main block 9-(101).
A system in which a subprocessor (102) and a subprocessor (102) are connected via a common path has the following basic configuration.

Reference numeral 106 denotes a timer means that starts measuring the hold time based on the AND signal of a hold request signal from the sub-processor to the main processor and a hold response signal from the main processor to the sub-processor in response to the hold request signal, and measures the hold time for a predetermined period of time. Outputs a time-up signal when elapsed.

Reference numeral 104 denotes a reset signal generating means, which generates a signal for forcibly resetting the sub-processor that issued the hold request signal in response to the generation of the time-up signal.

Reference numeral 105 denotes an interrupt signal generating means, which supplies an interrupt signal to the main processor by generating a time-up signal.

[Effect]

It determines whether the main processor has started holding based on the output of the logical product of the hold request signal and the hold response signal, starts measuring the hold time, and generates a time-up signal when a predetermined hold monitoring time has elapsed. Since the sub-processor that issued the hold request signal is reset, continuous holding of the main processor for a long time is prevented. Furthermore, since the main processor is interrupted by the time-up signal to notify the occurrence of an abnormality, the main processor can distinguish it from a system abnormality detected by the operation of the watchdog timer.

〔Example〕

FIG. 2 shows one embodiment of the present invention.
The same parts as in the figure are indicated by the same numbers, 7 is an AND circuit, 8 is a hold time monitoring timer ('rIM89 is a 79-tube 70-7 (FF) for recessing, and 10 is a 7-lip flop (FF) for resetting. ).

In FIG. 2, the hold request signal S1 of 8PU3 is connected to one input of the AND circuit 7 and the reset input of 11M8 (
negative logic) and the hold request input terminal of the MPU2. The hold response signal S2 of the MPU 2 is input to the other input of the AND circuit 7 and the hold response input terminal of the 5PU3. The output of the AND circuit 7 is connected to the activation input terminal of 11M8. Is the hold time time-up signal S5 from 11M8 FF? and the set side input of
It is supplied to the set side input of FF10. The set side output signal of FF9 is supplied to interrupt input terminal lNT1 of MPU2 as interrupt signal S6. FFID glue set side output signal is 5P as sub processor reset signal S8
Each is supplied to the reset input terminal (negative logic) of U3. The interrupt signal reset signal S7 is supplied from the MPU2 to the reset side input of Ft'9, and the subprocessor reset release signal S9 is supplied to the reset side input of F'F10.
Supplied from U2. WDT from MPU2 to VDT6
A reset signal S3 is supplied. Furthermore, the time-up signal S4 of the WDT6 is sent to another interrupt input terminal IN of the MPU2.
Supplied to T2.

5 and 4 are timing charts for explaining the operation of the embodiment shown in FIG. 2. FIG. 3 shows the case when the hold time has expired, and FIG. Each case of processor runaway is shown.

In FIG. 2, when MPU2 holds the path usage right to use the information resource (not shown) that is connected to common path 1, and 5PU3 has not issued the hold request signal S1, 11M8 It is in a reset state and is not performing any operations such as time measurement.

In this state, MPU2 will perform MA as long as it is normal.
The WDT 6 is reset at intervals within a certain period of time using the T reset signal S3, and operates according to the program.

When 5PU3 tries to obtain the right to use common path 1,
A hold request signal S1 is issued. In this case, MPU2
returns the hold response signal S2 according to its internal timing and enters the hold state.

11M8 has been released from the reset state by the hold request signal S1, so it starts measuring the hold time in response to the AND signal of the hold request signal S1 added and seen from the AND circuit 7 and the hold response signal S2.

When the use of the common path 1 by 5PU3 ends within the monitoring time range preset in 11M8, the hold request signal S1 becomes ``0#'' and the 11M
8 returns to the reset state again and ends the measurement of the hold time, and at the same time, the MPU 2 exits the hold state and continues the normal operation before the hold.

The timing chart in FIG. 3 shows the operation when the use of common path 1 by SPU S does not end within the monitoring time set in 11M8.

That is, in this case, by outputting the hold time time-up signal S5 from 11M8, both the 7-rip 70-tube FF9 for interrupt and the 7-rip flop FF10 for reset are set. As a result, the interrupt signal S6 from FF9 is sent to the interrupt input terminal l of MPU2.
A sub-processor reset signal S8 is supplied from the FF10 to the reset input terminal of the 5PU3. The MPU2 attempts to execute the interrupt processing program corresponding to the input from the terminal lNT1 in response to the interrupt signal S6, but as long as the hold request signal S1 from the 5PU3 is 11'', the MPU2 is kept in the hold state, and the common path 1 5PU3 cannot have usage rights and therefore cannot execute interrupt processing.On the other hand, 5PU3 is put into a reset state by subprocessor reset signal S8, and hold signal S1
is set to 10''. As a result, the MPU 2 is released from hold and starts executing the interrupt processing program.

In the interrupt processing corresponding to the terminal lNTl input in this case, it is known that the cause of the interrupt is based on the time-up of TIM8, so the MPU 2 can immediately perform the processing to recover from the abnormal state.

In this case, the interrupt processing includes resetting the interrupt FF9 using the interrupt signal reset signal S7, and if the abnormality of the 5PU3 is minor and continuous use is possible.
5P performed using subprocessor reset release signal S9
This includes canceling the reset of U3, etc.

The timing chart in FIG. 4 shows the operation when the WDT 6 protects the MPU 2 from running out of control.

As mentioned above, the WDT 6 monitors the operating state in which the MPU 2 is reset within a certain period of time, and generates the WDT time-up signal S4 when the interval between reset operations of the MPU 2 is extended beyond a specified value due to a cause such as runaway. Then, M
It is supplied to the interrupt input terminal INT2 of PU2. As a result, the MPU 2 executes the interrupt processing program corresponding to the input from the terminal INT2. In this case, the WDT monitoring time is
If it is determined from the sum of the execution time of MPU2's own program and the hold time by 5PU3, WD
It can be determined that the time amplifier of T6 is caused by the runaway of the MPU2, and therefore, there is no need to make a determination to distinguish it from the case caused by the above-mentioned hold time of TIM8 being exceeded.

The hold time monitoring timer TIM8 shown in FIG.
Any device may have the function of starting timekeeping by a start signal and outputting a time amplifier signal when a preset time has elapsed, as well as being able to be initialized by a reset signal and prepare for the next timekeeping. A CR circuit that controls charging and discharging of a capacitor using a resistor can be realized using a counter that counts 1 reference clock.

〔Effect of the invention〕

As explained above, according to the hold time monitoring circuit of the present invention, the signal is the AND of the hold request signal to the main processor output from the sub-processor on the common path and the hold response signal from the main processor in response to this signal. It has a timer that generates a time amplifier signal after a predetermined time has elapsed, and this timer monitors the hold time of the main processor, and the time-up signal forcibly resets the sub-processor that issued the hold request signal. Therefore, it is possible to prevent the main processor from being in a hold state continuously for a long period of time and causing the system to go down.

Furthermore, since an interrupt signal is supplied to the main processor in response to the above-mentioned time-up signal, it is possible to identify that the cause of this interrupt is due to an excess of the hold time by the sub-processor, and the watchdog timer Since it can be determined that the detected system abnormality is caused by a runaway of the main processor, the overhead of recovery processing from the abnormality can be reduced.

[Brief explanation of drawings]

Fig. 1 is a diagram showing the basic configuration of the present invention, Fig. 2 is a diagram showing the configuration of an embodiment of the present invention, Fig. 3 is a timing chart explaining the operation when the hold time is exceeded, and Fig. 4 5 is a timing chart illustrating the operation when the main processor runs out of control; FIG. 5 is a diagram illustrating a configuration example of a conventional hold time monitoring circuit; FIG. 6 is a timing chart illustrating the operation of the configuration example shown in FIG. 5. 1... Common path 2... Main processor (MPU) 3...-Sub processor (SPU) 6... Watchdog timer (WDT) 7... AND circuit 8... Hold time monitoring timer 9...・7 lips 70 tubes (FF) 10 for interrupts
...7-lip-flop for reset Patent applicant: Fuji Electric Co., Ltd. Representative: Patent attorney Gobe Tamamushi (2 others) Figure 1 showing the principle structure of the present invention Figure 1 Figure showing an embodiment of the present invention 2 Figure hold request signal s1 J""-
m Hold monitoring time Figure 6 shows the operation when the hold time is exceeded.
88]--[I + Meisof 0 - Shiba Imi/Guchi τ-T showing the operation when Nosa goes out of control Figure 4 Sub processor Main processor Conventional 0
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Claims (1)

[Claims] In a system in which a main processor and a sub-processor are connected via a common path, a hold request signal from the sub-processor to the main processor, and a hold response signal from the main processor to the sub-processor in response to the hold request signal. a timer means that starts measuring a hold time based on a logical product signal and outputs a time-up signal when a predetermined time elapses; 1. A hold time monitoring circuit comprising: means for generating a signal for automatically resetting the time-up signal; and means for supplying an interrupt signal to a main processor upon generation of the time-up signal.