JPS62129822A - Liquid crystal display - Google Patents

Abstract

PURPOSE:To shorten a data write time by setting the gate channel width of a thin film transistor (TR) properly based on a relational equation which contains a voltage for applying data to a gate line respectively, the threshold voltage and overlap length of the thin film TR, and capacity for picture display. CONSTITUTION:A part of a gate line 11 formed on the 1st substrate becomes a gate electrode 11a. Further, a source electrode 65 is made of, for example, Al thin film and connected to a picture element electrode 67 made of a transparent film such as ITO. The gate channel width W of the thin film TR 45 is found from an equation I which contains the voltage VGO applied to the gate line, a voltage VDO applied to a data line, the threshold voltage V1 of the TR 45, the gate overlap length LOV of the TR 45, and the capacity C0 for picture element display. In this case, K1 is a constant represented as K1=163mum<2>/pF.V. Channel width is set according to this relation to shorten the write time of data.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a liquid crystal display device using a thin film transistor as a liquid crystal driving element.

(Prior Art) Conventionally, amorphous silicon (hereinafter referred to as a
-5i) tla) Various liquid crystal display devices using transistors as driving elements have been proposed.

FIG. 5A is a block diagram showing a typical example of such a liquid crystal display device.

In FIG. 5(A), . 13. 15 and 17 are gate lines (hereinafter sometimes referred to as gate lines)
21, 23 and 25 indicate data lines (hereinafter also referred to as data lines 21). Also, 3
1.33. and 35 indicate a pixel (hereinafter sometimes referred to as pixel 31), 41 indicates a gate line drive circuit, and 43 indicates a data line drive circuit, respectively.

FIG. 5(CB) is a diagram showing an electrical equivalent circuit of the pixel 31, and the same components as in FIG. 5(A) are denoted by the same reference numerals.

In FIG. 5(B), 45 indicates a thin film transistor, 47 and 49 each indicate a parasitic capacitance of the thin film transistor, and 51 indicates a liquid crystal, which compensates for the capacitance of CtC. Further, 53 indicates a pixel electrode which is one electrode of the liquid crystal, and 55 indicates a common electrode line which is the other electrode.If the capacitance C of the liquid crystal [c is small, as shown in FIG. 5(C) , a charge holding capacitor 57 having a capacitance CM
may be provided separately. In either case, when using only the liquid crystal capacitor CLC as shown in Fig. 5(C), or when using two capacitors, CLC and charge holding capacitor CM as shown in Fig. 5(C). is the capacity for displaying each pixel, so below, the pixel display capacity CD
It is also sometimes called.

Further, FIG. 6 is a plan view for explaining the structure of a typical thin film transistor 45. Note that the same components as in FIG. 5(A) are indicated with the same reference numerals. The gate line formed on the first substrate (not shown) is made of, for example, a Cr (chromium) thin film, and a portion thereof becomes the gate electrode a.

81 indicates silicon nitride, for example, as a gate insulating film;
Reference numeral 63 indicates an a-Si thin film, and reference numeral 85 indicates a source electrode made of, for example, an Ai (aluminum) thin film.This source electrode 65 is connected to a pixel electrode shown at 67 in the figure and made of a transparent conductive film such as ITO.

Further, the data line 21 extends to a region spaced apart from the source electrode 65 on the a-St thin film 63, and this portion becomes the drain electrode 21a. Here, the drain electrode 21a
The distance separating the source electrode 65 and the source electrode 65 (distance indicated by L in FIG. 6) will be referred to as the gate channel length. In addition, the dimension of the portion of the source electrode 65 facing the gate electrode a across the gate insulating film in the direction parallel to the gate line (the dimension indicated by LOV in FIG. 6) is defined as the gate overlap length Lov. It shall be called. Furthermore, the dimension of the portion of the source electrode 85 facing the gate electrode a in the direction parallel to the data line (the dimension indicated by W in FIG. 6) will be referred to as the gate channel width W.

When displaying on a pixel-by-pixel basis using a liquid crystal display device as shown in FIG. 5(A), gate signals VG as shown in FIG. 7(A) are sequentially applied to gate lines in a line-sequential manner. is applied to temporarily turn on all the thin film transistors on one gate line, and at the same time time-divisionally samples the data signal VD as shown in FIG. 7(B) using the data line 21 according to the position of each pixel. and apply it. As a result, the liquid crystal 51 is driven with alternating current.

By the way, the parasitic capacitance 48 in FIG. 5(B) causes the potential of the pixel electrode 53 in FIG. 5(CB) to decrease when the gate signal VG falls. The value of parasitic capacitance 49 is cGs
When the capacitance of the liquid crystal 51 is CtC and the amplitude of the gate signal VG is VCO, the voltage drop ΔV at the pixel electrode 53 at the falling edge of the gate signal G is as follows: ΔV=CGSXVGO/(CGS+CLC) −(1)
becomes.

In addition, the capacitance CGS of the parasitic capacitance 48 can be calculated as follows (2 ) can be obtained using the formula.

Ccs=Cox e We Lov-” (2) Note that if the voltage drop ΔV mentioned above is large, it will cause deterioration of the quality of image display.

The cause of this will be explained below with reference to FIGS. 7(A) to 7(C) and FIG. 8.

FIG. 7(A) is a waveform diagram showing the gate signal VG, and its amplitude has a VGO1 period of T. Further, FIG. 7(B) is a waveform diagram showing the data signal Vo, which changes at a level of ±VDO centering on the potential VOO every period T in order to turn on the liquid crystal 51. Also, Figure 7 (C) is Figure 6 CB)
The liquid crystal drive signal vS applied to the pixel electrode 53 shown in
FIG.

Gate signal vG becomes H level (V'Go) and writing is performed by data signal VO. After that, when the gate signal VG becomes L level (0), this gate signal VG
At the same time as the fall of the liquid crystal drive signal V due to the influence of the parasitic capacitance 49,
The potential of S decreases by ΔV.

The potential VS until the next gate signal VG becomes H level
hold. However, this potential gradually decreases due to leakage current from the liquid crystal 51 and the thin film transistor 45.

By the way, if the current flowing between the drain and source of the thin film transistor 45 is ios, the current value can be found from the following equation (3-1) when VGS≦VT. Also, Vos≦VGs-Vr >VT or voS≦■GS>
In the case of Vs, it can be found from the following equation (3-2). Furthermore, VDS>VGS-Vr>Vr or VDS>VGS>
In the case of Vl, it can be found from the following equation (3-3).

tos=0・・・・・・・・・・・・・・・・・・
・・・・・・・・・・・・(3-1) ios= [p I
C0X@W ((2Vos (VGs-VT
)-VGs2 ] /2L... (3-2) ios
= (p-・CoxIIW (VGS-Vt)
21/2L・・・・・・・・・・・・・・・・・・
(3-3) However, the tiles indicate electron mobility, COX indicates the capacitance per unit area of the gate insulating film of the thin film transistor, W indicates the gate channel width of the thin film transistor, and L indicates the gate channel length. , VT indicates the threshold voltage for turning on the thin film transistor, VGS indicates the gate-source voltage of the thin film transistor, and its value is CVa - Vs), and VOS indicates the drain-source voltage, and its value is (Vo-Vs)
becomes.

Therefore, when the voltage of ves is lower than the threshold voltage vI, the thin film transistor 45 is turned off, and ios becomes O. Therefore, when the gate signal VC is at L level, that is, when the liquid crystal drive signal VS is held, If the voltage drop ΔV due to the parasitic capacitance ces is smaller than the threshold value Vr, a potential value as shown by the dotted line in FIG. 7(C) should be maintained. However, in reality, as is clear from the measured data of the square root of the drain-source current ins with respect to the gate-source potential VGS shown in FIG.
Even if VGS is smaller than VT, ios does not become O, and ios cannot be set to a sufficiently small value unless VGS is set to a value of 0 volts (V) or less. Therefore, when holding the liquid crystal drive signal VS, if vGe becomes a positive value, leakage current will occur in the thin film transistor 45, so it should be held at the potential at time 1 in FIG. 7(C). The value changes as shown by the dotted line in the figure.

As a result, the effective voltage applied to the liquid crystal becomes a small value, making it impossible to turn on the pixels of the liquid crystal display device sufficiently.

As a countermeasure to solve this drawback, when the gate signal ve is at L level, the gate-source voltage VCS is set to 0 port or less, so when vG is at L level, the potential of the liquid crystal drive signal Vs is A method is used in which the potential is made higher than the potential of the signal VG.

This method will be explained below with reference to FIGS. 9(A) to 9(C). First, as shown in Figure 9(B), the liquid crystal is heated to O.
The center potential of the data signal Vo for entering the N state is increased by 67 potential drops to the value (Voo + ΔV), and the period T
Each time, the level is changed by ±VOO. LCD drive signal Vs
data is written when the data signal Vo is applied when the gate signal VG (see Figure 9 (A)) is at the H level.Next, when the gate signal VG is set to the L level, the falling edge of VG At the same time, the liquid crystal drive signal VS has a parasitic capacitance of 4
9, the potential drops by ΔV. Therefore, the data signal Vo
If the gate signal vG falls when the potential of VD is (ZVoo+ΔV), the potential of the liquid crystal drive signal
S becomes 0 (see FIG. 9(C)).

When the gate signal VG goes to the L level and the liquid crystal drive signal VS is held, the potential of the pixel electrode 53 changes to approach the potential of the common electrode line 53 shown in FIG. 6 (CB) due to the leakage current of the liquid crystal 51. do.

Here, in order to extend the life of the liquid crystal 51, this liquid crystal 51
When the potential of the common electrode line is set to VDO so as to make the DC component applied to the voltage as small as possible.

In the voltage holding state, the potential of the liquid crystal drive signal VS is higher than the potential of the gate signal VG. Therefore, it is possible to prevent leakage current from thin and film transistors.
The liquid crystal drive signal can be held at a desired potential.

(Problems to be Solved by the Invention) However, when writing data in a liquid crystal display device driven by the method described above, the parasitic capacitance shown in FIG. 5(B) is generated in the gate-source voltage of the thin film transistor. 4
9 causes a voltage drop of ΔV. Therefore, since the drain-source current ios becomes smaller in accordance with this voltage drop, the time for writing data to the liquid crystal 51 becomes longer in accordance with the current reduction. Here, if an attempt is made to shorten the data writing time by increasing the gate channel width W of the thin film transistor already explained with reference to FIG. This results in an increase in ΔV. Therefore, there is a problem in that the data writing time may be lengthened.

Furthermore, if the gate-source voltage is further increased in order to increase the current ios, the value of Δ■ will also increase accordingly, causing the same problem as described above.

Another problem is that the device becomes expensive because electronic components with high voltage must be used.

By the way, the inventor of this invention discovered that by setting an appropriate gate channel width W, it is possible to control the gate-source current and parasitic capacitance, thereby shortening the data writing time of a liquid crystal display device. did.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a liquid crystal display device having a large display area, a large number of pixels per unit area, excellent display quality, and short data writing time.

(Means for Solving the Problem) In order to achieve this object, the present invention has a plurality of gate lines and a plurality of data lines orthogonal to these gate lines, and each intersection of the two lines is provided. A first substrate having thin film transistors formed in each region and a transparent pixel electrode connected to the thin film transistors, a second substrate facing the first substrate and having a common electrode, and a second substrate provided between these substrates. In a liquid crystal display device including a liquid crystal and the aforementioned gate line and data line drive circuit, the gate channel width W of the thin film transistor is determined by the voltage VGO applied to the gate line and the voltage VD applied to the data line.
O, the threshold voltage VT of the thin film transistor, the gate overlap length Lov of this thin film transistor,
It is characterized in that the gate channel width is determined from the following equation (I) using the pixel display capacitance Co.

W=K+ IIcD (VGO-2VDO-v+
)/Lov...(I) However, K1 is a constant Kl=163gm2/pF*V.

(Function) A liquid crystal display device manufactured to satisfy the above-mentioned formula CI) has a shorter data writing time than a liquid crystal display device manufactured arbitrarily.

Furthermore, by using formula (I), the desired t”J
J film transistors can be easily designed.

(Embodiments) Hereinafter, embodiments of the present invention will be described with reference to the drawings. Note that the same components as those in the prior art will be described using the same reference numerals.

The thin film transistor used in the liquid crystal display device of the present invention is a thin film transistor having the same structure as the conventional thin film transistor as already explained with reference to FIG. 6, and its drain-source current ios is as described above (3-1) (3-2) and (3
-3) It is designed to satisfy formula. Furthermore, the definitions of the gate channel width W, gate overlap length LOV, etc. are also the same.

In addition, in a liquid crystal display A arrangement as shown in FIG. 5A, in which such a thin film transistor 45 is used as a driving element, the data writing time of the pixel 31 is longer than the pixel electrode 53 (FIG. 5CB).
)) is determined by the rising time τ of the potential.

The present invention aims to provide a liquid crystal display device with a short writing time by optimizing the gate channel width of a thin film transistor.For this purpose, various parameters of the liquid crystal display device are set to certain values, details of which will be described later. do)
, the relationship between the gate channel width W and the rise time τ' of the pixel electrode 53 was determined from a simulation when the equivalent circuit shown in FIG. 5 CB) was driven by the signals shown in FIG. The program used for the simulation was ASTAP (the name of an electrical circuit simulation program manufactured by IBM Corporation in the United States).

Also, gate overlap length Lov and gate channel I
“Capacitance value CGS” of parasitic capacitance 48 by changing IW
can be determined by the above-mentioned equation (2) Ca5=Cox*We LOV.

First, the rise time τr with respect to the gate channel width W when the gate overlap length Lov is taken as a parameter.
Find the characteristics of. The condition is that each LOV value is 1
0.8.6.4 pot m, and gate channel length Lt
−10 μm, and the capacitance C per unit area of the gate insulating film
It is assumed that OX is 1.42×10-'F/m2, the electron transfer path is 0.1 cmz/Yes, and the threshold voltage vf of the thin film transistor is 5 volts. Furthermore, in this case, only the liquid crystal capacitance is used as the pixel display capacitance ft Co , and the liquid crystal capacitance C is set to 0.5 pF, and the gate signal VG
Let the amplitude VG[+ of the data signal yVo be 25 volts, and the amplitude VDO of the data signal yVo be 6 volts.

FIG. 1(A) is a characteristic curve diagram showing the results of simulation under the above-mentioned conditions. The horizontal axis represents the gate channel width W, the vertical axis represents the rise time τ, and τr is plotted against W. In the figure 0, 10
1 is Lov= l OJj, m, then 102 is L
When ov=8 gm, 103 shows the characteristic curve diagram when Loy=6 μm, and 104 shows the characteristic curve diagram when LH7=41Lrc.

FIG. 1(B) shows the gate channel @W1 that can minimize the rise time τr for each gate overlap length LOV obtained from FIG. 1(A), and the rise time at that time. It is a characteristic curve diagram. In the figure, 105 is a characteristic curve diagram showing the relationship between LOV and Wo, and 106 is a characteristic curve diagram showing the relationship between LOV and τr°.

The relational expression shown in the following equation (4) can be obtained from the characteristic curve diagram 105, and the relational expression shown in the following equation (5) can be obtained from the characteristic curve diagram 106.

W0=kn/Lov・・・・・・(4)τ r”=
k 2+ fist Lov= (5) However, kll and ni21 are constants.

Next, the characteristics of the rise time τr with respect to the gate channel width W are determined when the liquid crystal capacitance CLC is used as a parameter. The condition is that the value of CLC is 0.5°1.0.1.5P
F, and the gate overlap length LOV is ioμm, and the other conditions are the same as those when the gate overlap length LOI+ is used as a parameter.

Figure 2 (A) is a characteristic curve diagram showing the results of simulation under the above conditions, where the horizontal axis represents the gate channel @W, the vertical axis represents the rise time τr, and τr is plotted against W. In the diagram 0, 20
If 1 is CLC”0.5PF, 202 is CLC=
1. When set to OFF, 203 is CLC = 1.5PF
Characteristic curve diagrams are shown for each case.

Figure 2 (B) shows each liquid crystal capacitance C obtained from Figure 2 (A).
The gate channel width W8 that can minimize the rise time τ with respect to LC and the rise time τr・
In Figure 0, which is a characteristic curve diagram showing
205 is a characteristic curve diagram showing the relationship between LC and W◆;
is a characteristic curve diagram showing the relationship between CLC and τr°.

The relational expression shown in the following equation (6) can be obtained from the characteristic curve diagram 204, and the relational expression shown in the following equation (7) can be obtained from the characteristic curve diagram 205.

W°=k 12 ・CLc-(6) τr umbrella=K22・・・・・・・・・・・・・・・ (7
) However, k12 and 22 are constants.

Next, the characteristics are determined using the rise time for the gate channel @W when the electron mobility p is used as a parameter.

The condition is that the value of JL is 0.05.0.1.0.2.0
．． 3 cm2-/V*S, and the gate overlap length Lov is 5 μm, and the other conditions are the same as those when the gate overlap length Lol+ is used as a parameter.

FIG. 3(A) is a characteristic curve diagram showing the results of simulation under the above-mentioned conditions, where the horizontal axis represents the gate channel width W, the vertical axis represents the rise time τr, and τr is plotted against W. This is an indication. In the figure, 30
1 is p=0. When O5Cm1/v・S, 302 is g=0. When lCm2/VIIS, 303 is g=
When 0.2cm2/V*S, 304 is g=0.3
Characteristic curve diagrams in the case of 0 m2/v-3 are shown.

FIG. 3(B) shows the gate channel width W' that can minimize the rise time τr for each electric f-mobility end, obtained from FIG. 3(A), and the rise time τr at that time.
FIG. 9 is a characteristic curve diagram showing 9. In the figure, 305 is a characteristic curve diagram showing the relationship between Ru and Wo, and 306 is a characteristic curve diagram showing the relationship between pot and τr.

The relational expression shown in the following equation (8) can be obtained from the characteristic curve diagram 305, and the relational expression shown in the following equation (9) can be obtained from the characteristic curve diagram 30B.

W fist=K+:+・・・・・・・・・・・・・・・(8)
τr”=k23/ru (9) However, k13 and 23 are constants.

Next, the characteristics of the rise time τr with respect to the gate channel width W are determined when the threshold voltage VT of the thin film transistor is used as a parameter. The condition is that the VT value is 8.7
, 6.5.4, and 3 ports (v), and the gate overlap length r-oυ is 5 JLm, and the other conditions are the same as those when the gate overlap length Ll is used as a parameter. do.

FIG. 4(A) is a characteristic curve diagram showing the results of simulation under the above-mentioned conditions, where the horizontal axis represents the gate channel width W, the vertical axis represents the rise time τr, and τr is plotted against W. This is an indication. In the figure, 40
1 is when Vr=8V, 402 HaV+ = 7
In the case of V and I, 403 is 40 when vr=6v
4 is Vl = 5V,! :If you do, 405 HaV
+=4V to I, 406 shows characteristic curve diagrams when V+=3V.

Figure 4 CB) shows the characteristics of the gate channel %lW'' whose rise time τr can be used as a tentacle for each threshold voltage Vt and the rise time τr° obtained from Figure 4 (A). In Figure 0, which is a curve diagram, 4
07 is a characteristic curve diagram showing the relationship between Vr and Wo, and 408 is a characteristic curve diagram showing the relationship between Vl and τ'9.

From the characteristic curve diagram shown in 407, the relational expression shown in the following (lO) formula can be derived, and from the characteristic curve diagram shown in 408, the following (・) can be derived.
We can obtain the relational expression shown in Eq.

Wa=k+a (VGO-2Voo-Vy)...
...(10) cr"= k2a/ (VGo -2Voo -Vl
)...(・) However, 14 and 24 are constants.

From the relational expressions (4) to (・) mentioned earlier, the gate channel 1! that can minimize the rise time of the potential of one pixel electrode! Relational expression (12) for determining WI and relational expression (13) for determining - from the rise time at that time, the respective relational expressions are as follows.

W"=Kl ・CLC(VGO-2Voo-VI)/
LOV・・・・・・・・・・・・・・・(12)(y”
: K2, *Lov/g (VGO-2Voo
-Vl) (13) However, Kl is a constant of +=163gm2/pF.V, and a constant of K24fK2=3.04X10z.

As a specific example, the value of gate overlap length Loυ is 5.
I m, the value of the liquid crystal capacitance is 0.5 pF, the amplitude of the gate signal is 25 V, the amplitude of the data signal is 6 V, and the threshold voltage Vr.
When the value of is 5■, the value of the optimal gate channel #AW· that minimizes the rise time is 130 gm. moreover,
The value of electron mobility is g=0.1cm2/VIIS(7
), the value of the rise time τr° is 19 seconds.

In addition, in the case where the mask alignment accuracy of thin film transistors is relaxed for the purpose of easily manufacturing a large-sized liquid crystal display device1, for example, when the value of the gate overlap length ILov mentioned above is set from 5 lm to 10 lm, It can be seen from equation (12) that the optimal gate channel width is 65 JLm.

Furthermore, in order to obtain the same rise time as when the LOV value is 5 gm, the electron mobility end must be 0.2 cm1/V*S
By doing so, it is possible to create a liquid crystal display device that is easy to manufacture and has a desired data writing time.

In the above-mentioned embodiment, the liquid crystal display device is not provided with a charge retention capacitor.
Of course, the present invention may also be used in a liquid crystal display device provided with a charge retention capacitor 57 having the following characteristics.

When the above-mentioned equation (12) is rewritten into a general equation that takes into account the liquid crystal volume fft Ct c and the capacitance CH of the charge holding capacitor, the following equation (I) is obtained.

W= Kl @ Co (VGO-2Voo-V
r )/Lov・・・・・・・・・・・・・・・(I)
However, Kl is a constant of Kl=163 μm2/pF+1V. In addition, Co indicates the pixel display capacitance, and this C
The value of D is in the case of co=ctc, and in the case of C0=CLC+C,
There are cases where

(Effects of the Invention) As is clear from the above description, according to the liquid crystal display device of the present invention, since the liquid crystal display device is created so as to satisfy the above-mentioned formula (CI), it is possible to Data writing time is shorter than that of a liquid crystal display device.

Furthermore, by using the CI formula, a desired thin film transistor can be easily designed.

Therefore, when manufacturing a liquid crystal display device with a desired data writing time, for example, the accuracy of parameters that would increase manufacturing costs should be relaxed, and the accuracy of parameters that would not affect manufacturing costs but would improve device characteristics should be adjusted. Consideration can be taken, such as making the accuracy of

Therefore, the liquid crystal display device of the present invention has superior reliability and is less expensive than conventional liquid crystal display devices.

Therefore, it is possible to provide a liquid crystal display device with a large display area, a large number of pixels per unit area, excellent display quality, and short data writing time.

[Brief explanation of drawings]

Figure 1 (A) and (B), Figure 2 (A) and (B), Figure 3 (A) and (B), Figure 4 (A) and (B)
is a diagram used to explain the liquid crystal display device of the present invention; FIGS. 5(A) to (C) are diagrams used to explain the conventional and present invention; FIG. 6 is a diagram used to explain a thin film transistor; and FIG. (A) to (C) are diagrams for explaining the prior art, and are drive signal waveform diagrams of a liquid crystal display device. Figure m8 is a diagram for explaining a thin film transistor. FIGS. 9(A) to 9(C) are diagrams for the conventional method and the present invention, and are drive signal waveform diagrams for a liquid crystal display device.・, 13.15.17... Gate line 1la - gate electrode, 21.23.25... Data line 21a...
Drain electrode, 31.33.35...pixel 41.
...Gate line drive circuit, 43...Data line drive circuit 4
5... Thin film transistor, 47.49... Parasitic capacitance 51... Liquid crystal, 53.67... Pixel electrode 55... Common electrode line 57... Charge retention capacitor 81... Gate insulating film 63... Amorphous silicon thin film 85... Source electrode VG... Gate signal, Vo... Data signal VS
...Liquid crystal drive signal, L...Gate channel length LOV...Gate overlap length W...Gate channel width. Patent Applicant: Oki Electric Industry Co., Ltd. Key 1T-Half 77! RLtyv (μm) Kate Overlap' 4 Pairs of Fans Blood Kate Channel RP Characteristic Diagram Figure 1 "-L channel width W (μm) Liquid crystal display lamp most suitable channel width characteristic diagram Figure 2 Gate channel length W (μm) (cm2/V-5) #1ffJ/f maximum Δ1 surname Tochan I tsumu q ragi hand sex β ri Fig. 3 ge°-L chan potato Lrp w(am)shijt+/,
! Voltage Vr (V) Strength of FT
43 Transistor aMl power oH31-35: aJ element Conventional reversal Figure a used in explanation of this invention Fig. 5 4538 Further transistor 5 da Common electrode N 47
4Q: Yori'! 84 VG gate signal sr
:', Yasho VD T-Tai old name f
3 = Gamidenyu Vs Sekaki, Kikinsu) f f7 Charge Imata Special Ki W/ψshita Figure 5 tta: K-Ft, 1a L = Nige-Tochi y>
2-no.J2fa: F'L4-in electric tube w Nigate channel width 61 2-digit F2 Green order 3 Amorphous silicon rumor belly 65 Source Yukikake 67-Recharged electric tree k Lov: Gate overlap long-length transistor explanation Figure 6 and Figure 7 ' 14th of the month

Claims (1)

[Claims] (1) A first circuit having a plurality of gate lines and a plurality of data lines perpendicular to these gate lines, and a thin film transistor formed at each intersection area of both lines, and a transparent pixel electrode connected to the thin film transistor. A liquid crystal display device comprising: a second substrate facing the first substrate and having a common electrode; a liquid crystal provided between these substrates; and a drive circuit for the gate line and data line. The gate channel width W of the thin film transistor is determined by the voltage V_G_O applied to the gate line, the voltage V_D_O applied to the data line, and the threshold voltage V_ of the thin film transistor.
T and the gate overlap length L of the thin film transistor
Using _O_V and pixel display capacitance C_D, the following (
I) A liquid crystal display device characterized by having a gate channel width determined from the formula. W=K_1・C_D(V_G_O-2V_D_O-V_
T)/L_O_V...(I) However, K_1 is a constant of K_1=163 μm^2/pF·V.