JPS62128354A - Starting system for multiprocessor system - Google Patents

Abstract

PURPOSE:To substitute any one faulty processor with a reserved processor by rewriting the address allocated to the reserved processor of correspondent table in the address allocated to an individual bootstrap loader corresponding to the processor in normal use. CONSTITUTION:The bootstrap loader for loading system programs SP1-SPN is divided into a common bootstrap loader CB that is common for all the processors and individual bootstrap loaders B1-BN respectively corresponding to processors in normal service P1-PN. The common bootstrap loader CB is provided with a correspondence table T that shows the relation between the respective processors an the disposition-addresses of the individual bootstrap loaders in an secondary storage device SM. When determining the individual bootstrap loader to be loaded on the memory of the reserved processor P0, the disposition-address part corresponding to reserved processor of the correspondence table is rewritten. As a result, the common bootstrap loader is made able to optionally replace the individual bootstrap loaders to be loaded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention connects at least one standby processor and a plurality of regular processors, and loads a system program into their memories from an auxiliary storage device. Regarding the startup method of a multiprocessor system,
In particular, when the regular processor goes down, a backup processor can be easily activated in place of it.

[Conventional technology]

The conventional startup method for multiprocessor systems is as follows:
The structure shown in FIG. 3 is known.

In the figure, P+''PN is a processor, which has memories M1 to M in which system control programs CP, to CPN are stored in ROM areas, respectively.

The processors P1 to PN are connected to each other via a common lotus C, and are also connected to a common auxiliary storage device SM. This auxiliary storage device SM includes each processor P.
1 to P, individual bootstrap loaders 81 corresponding to
~B, and system programs S P + ~SPN are stored.

Thus, normally, when each processor P1 to P is started, an individual bootstrap loader Bl""BN of the auxiliary storage SM is loaded into their memories M, to M, and
These bootstrap loaders are system program S
The system is started by loading P, -3P, and I from the auxiliary storage SM.

[Problem that the invention seeks to solve]

However, the above conventional multiprocessor system l,
In this startup method, the system control program for each processor loads an individual bootstrap driver/no loader from a predetermined location in the auxiliary storage, and each processor is configured to be able to load only a specific system program. Therefore, by setting up a backup processor and loading the system program of the down processor into the memory of the backup processor, if the regular processor in operation goes down, the system program can be loaded into the backup processor. Even when you need to take over a downed processor,
There is a problem in that the spare processor can only take over when a specific preset processor goes down.

Therefore, the present invention has been made by focusing on the problems of the conventional example, and an object thereof is to provide a startup method for a multiprocessor system in which a backup processor can take over the place of any processor that has gone down. The purpose is

[Means for solving problems]

In order to achieve the above object, the present invention provides at least one
A multiprocessor system in which one spare processor and a plurality of regular processors are connected, and a system program is loaded from an auxiliary storage device into the memory of each processor at startup, the system program being loaded into the auxiliary storage device. A common bootstrap loader common to all processors and individual bootstrap loaders individually corresponding to each regular processor/nosa are provided, and the common bootstrap loader has n in which the individual bootstrap loader is stored; I
A correspondence table showing the correspondence between addresses in the auxiliary storage device and each processor is provided, and when a spare processor is used in place of the regular processor, the address for the spare processor in the correspondence table is used as the correspondence table for the regular processor. By rewriting the address of the individual bootstrap loader corresponding to the address of the individual bootstrap loader corresponding to the regular processor, the individual bootstrap loader corresponding to the regular processor is loaded into the memory of the spare processor.

[Operation] In this invention, the bootstrap loader that loads the system program is divided into a common bootstrap loader that is common to all processors and an individual bootstrap loader that corresponds to each regularly used processor.
In addition, by providing the common bootstrap loader with a correspondence table representing the relationship between each processor and the location address of the individual bootstrap loader in the secondary storage device, the individual bootstrap loader 7 loader to be loaded into the memory of the spare processor can be loaded. At the time of determination, the common bootstrap loader refers to the correspondence table and arbitrarily changes the individual bootstrap loader to be loaded by rewriting the arrangement address part corresponding to the backup processor in the correspondence table. Possible 1
1.

〔Example〕

Embodiments of the present invention will be described below based on the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

In the figure, Po is a backup processor, P and ~P are regular processors, and M0 to MN are each processor P.

~PN memories, each memory M. -M has system control programs CP0 to cp in its ROM M area.
N is stored.

C is a common bus that connects each processor 4, P0 to P, to each other, and SM is connected to the common bus C and each processor P. −
This is an auxiliary storage device accessed from P9.

At least all processors P0 are stored in the auxiliary storage devices S and M.
~Common bootstrap loader CB common to PN
and individual bootstrap loaders B1 to B8 that are individually installed for each of the commonly used processors P1 to P8,
System programs SP, ~SP, loaded by these individual bootstrap loaders B1~BN,
is stored. Here, the common bootstrap loader CB is used for each processor P0 to P0 as shown in FIG.
.

Auxiliary notes for individual bootstrap loaders B0 to BN corresponding to 1. The relationship with the arrangement address in the α device SM is stored as a correspondence table T. In other words, since these are regular processors, the placement addresses of the programs t p and ~PN are stored as A l−A N, and for the program P, this is the predetermined f+i
Since this is a ff processor, the individual bootstrap loader is undefined, and its location address is stored as r NUL L J, indicating that it is undefined.

Next, the operation of the above embodiment will be explained.

It is now assumed that the regular processors P1 to P are in operation and the backup processor P0 is on standby.

In this state, the system programs SP, -SPN corresponding to each processor of the auxiliary storage device SM are stored in the memories M1-MN of the regular processors P1-PM, and these system programs SP.

Each of the processors P1 to P executes a predetermined process based on ~SP.

In this normal state, for example, when the regular processor P1 goes down, one of the other regular processors P+ ( i=2
．． 3...N) detects that the processor P1 is down, the processor P8 detecting the down state causes the backup processor P in the correspondence table T of the common bootstrap loader CB in the auxiliary storage SM to be
The individual bootstrap loader B+ of the processor P, which has downloaded the location address corresponding to 0 from rNULLJ
Supplementary note 4. Rewrite the location address in the a device SM to A1.

Next, a start signal is sent to the standby processor P0 via the common bus C, and the system control program C is activated.
Start Po. When the system control program CP is activated in this way, it causes the auxiliary storage SM
A common bootstrap loader C containing a correspondence table T of
Load B into memory M0 and start its common bootstrap loader CB. As a result, the common bootstrap loader CB refers to the correspondence table T,
The location address corresponding to the spare processor P0 is A
, so the individual bootstrap loader B1 is loaded into the memory M0 and this individual bootstrap loader B is started, thereby loading the system program SP into the memory M0 and starting the system program SP. to start. In the above manner, the spare processor P. A regular processor P that is down,
can take on the role of

Similarly, when another regular processor pt goes down, another regular processor other than the regular processor P that went down causes the location address of the regular processor P that corresponds to the spare processor P0 in the correspondence table T to go down. The system program CP of the regular processor P, which was rewritten to the address and went down as a result.
i is loaded into the memory M0 of the backup processor P0 and activated, and the backup processor Po can take over for any of the regular processors P1 to PH that have gone down.

In the above embodiment, the case where there is one standby processor has been described, but the invention is not limited to this, and a plurality of slave processors can be used and prioritized. It is also possible to take over for a regular processor that has gone down in accordance with the priority order.

〔Effect of the invention〕

As explained above, according to the present invention, a common bootstrap loader and an individual bootstrap loader are provided in an auxiliary storage device, and when a regular processor goes down, each processor and an individual bootstrap loader in the auxiliary storage device are arranged. The location address corresponding to the spare processor in the correspondence table showing the relationship with the address is rewritten to the location address in the auxiliary storage device of the individual bootstrap loader corresponding to the downed regular processor, and in this state, the common bootstrap loader Since the individual bootstrap loader to be loaded into the backup processor is determined by referring to the correspondence table, it is possible to arbitrarily change the individual bootstrap loader to be loaded into the backup processor. It can replace any regular processor and improve the reliability of a multiprocessor system.

In addition, by simply updating the correspondence table, you can freely change the location address of the individual bootstrap loader and system program in the secondary storage device, thereby assisting the individual bootstrap loader and system program of each processor. By arranging them all together within the storage device, effects such as being able to efficiently utilize the auxiliary storage device can be obtained.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is an explanatory diagram showing an example of a correspondence table applicable to the present invention, and FIG. 3 is a block diagram showing a conventional example. In the figure, Po is a spare processor, P1 to PN are regular processors, Mo to M are memories, C is a common bus, SM is an auxiliary storage device, CB is a common bootstrap loader, T is a correspondence table, and 81 to B. is the individual bootstrap loader, SP, ~SP. is a system program.

Claims (1)

[Claims] A multiprocessor system in which at least one spare processor and a plurality of regular processors are connected, and a system program is loaded from an auxiliary storage device into the memory of each processor at startup, the system comprising:
The auxiliary storage device is provided with a common bootstrap loader common to all processors that loads a system program and an individual bootstrap loader that corresponds to each regular processor, and the common bootstrap loader is configured to load a system program by the individual bootstrap loader. A correspondence table showing the correspondence between stored addresses in the auxiliary storage device and each processor is provided, and when a spare processor is used in place of the regular processor, the address for the spare processor in the correspondence table is A method for starting a multiprocessor system, characterized in that an individual bootstrap loader corresponding to a regular processor is loaded into a memory of a spare processor by rewriting the address of the individual bootstrap loader corresponding to the regular processor.