JPS62128180A - Manufacture of mesa type semiconductor device - Google Patents

Abstract

PURPOSE:To form channel stopper regions at the correct positions on the bottoms of the mesa grooves in high concentration and also, in a controlled state as well as to contrive the reduction in the total process time by a method wherein the channel stopper regions are provided in the main surface of the semiconductor substrate on one side at the positions that are to be used as the bottom parts of the mesa grooves, the semiconductor substrate on the other side is bonded to the channel stopper regions and such mesa grooves as expose the channel stoppers on the bottoms of the mesa grooves are formed. CONSTITUTION:A donor impurity is diffused in an N<-> Si substrate 34 to form an N<-> high-concentration layer 33, while an acceptor impurity is selectively diffused in another P-type Si substrate 32 to provide channel stopper P<+> regions 36, and at the same time, an acceptor impurity is diffused from the whole surface of the lower surface as well to provide a contact P<+> region 38. After then, the N<-> region 34 of the first substrate and the side of the channel stopper P<+> regions 36 of the second substrate are bonded in such a way as to come into contact interposing an adhesive surface 37 between them. Lastly, when mesa grooves 35 are dug and are formed in such a way that th P<+> regions 36 are positioned at the bottom parts of the mesa grooves 35, the P<+> regions 36 are turned into channel stoppers.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and more particularly to an improved method for manufacturing a high reverse breakdown voltage mesa type semiconductor device having a channel stopper.

[Technical Background of the Invention] In mesa-type semiconductor devices, the surface of the device is coated with a protective film in order to stabilize the characteristics of the device and improve reliability. One of the methods is to coat the surface with a protective film. There are surface protection methods. The thermal oxide film provides a stable surface and is suitable for mass production, but positive mobile ions exist in the oxide film, which adversely affects reliability, particularly high-temperature reverse bias characteristics.

Conventionally, for example, in a mesa diode having an N''-N--P structure, a P+ region having an acceptor impurity concentration of 1019 cm-3 or more is provided near the bottom of the mesa groove as a channel stopper 6, as shown in FIG. A structure is adopted to prevent the formation of an inversion layer on the surface of the P region 2 due to positive charges in the oxide film 9 when a high temperature reverse bias is applied.
0 is an electrode, and 5 is a P+ region for taking out the electrode.

[Problems with Background Technique] Conventionally, methods for providing the channel stopper P+ region 6 include, for example, the method shown in FIGS. 3(a) to (d) process diagrams and the method shown in FIGS. The method shown in is known.

The method shown in Fig. 3 is to create a mesa groove with a
This is a method of diffusing the Nelstopper P+ region. That is, first, the N-type silicon substrate 1 shown in FIG.
The acceptor impurity is absorbed from the entire lower surface of the figure 1, and the donor impurity is absorbed from the entire upper surface of the figure, both with a surface concentration of 1020.
c "3, respectively, P region 12 and N +
A territory 13 is established (Fig. 3(b)). Next, N
+ territory ii! A hole is dug from the surface on the t13 side to reach P region 12, and N" region 13, N- region Ij!! 14 and P region 1 are formed.
A mesa groove 15 extending over the two is provided (FIG. 3(C)). After that, an acceptor impurity is added to the bottom of the mesa groove 15.
10l9 or more is introduced to form the P+ region 16 of the channel stopper (FIG. 3(d)).

The method shown in FIG. 4 is a method in which a deep P+ region is diffused and then a mesa groove is formed. That is, first, the N-type silicon substrate 21 shown in FIG. 4(a) is taken, and acceptor impurities are applied from the entire surface on the lower surface of the figure and from the position where the mesa groove is provided on the upper surface of the figure, respectively, to a surface concentration of 10" cm. I
Q" cm-3, forming a P region 22 and a P+ region 27 having a concentration of 10" cr-3 or more at the bottom of the mesa groove (FIG. 4(b)). Next, donor impurities are diffused from the upper surface of the figure to form the N+ region 23.
(Fig. 4(C)). After that, a mesa groove 25 is dug and the bottom of the P" region 27 is covered with a channel stopper 26.
4(d), which is the same as that in FIG. 3(d).

Then, an oxide film and an electrode are formed on the substrate on which the regions shown in FIGS. 3(d) and 4(d) are formed, and the substrate is cut into pellets along the center line of the mesa groove 25. A diode having the structure shown in Figure 2 is obtained.

However, in the conventional method shown in FIG. 3, since the P+ region is diffused at the bottom of the mesa groove after it is formed, it is difficult to accurately control the diffusion position.On the other hand, in the conventional method shown in FIG. Since it is necessary to diffuse deeper than the depth of the mesa groove, the diffusion time becomes longer and the P+ concentration of the channel stopper 26 is significantly lower than the diffusion surface concentration, and the P+ concentration is also difficult to control. There is.

[Objective of the Invention] An object of the present invention is to place the channel stopper at the bottom of the mesa groove in a more accurate position, at a higher concentration, and to control the concentration, thereby improving characteristics such as high reverse breakdown voltage. An object of the present invention is to provide a method for manufacturing a mesa-type semiconductor device having the following characteristics.
Another object of the present invention is to provide a method for manufacturing a mesa-type semiconductor device that contributes to shortening the overall process time by shortening the diffusion time of the channel stopper region.

[Summary of the Invention 1 This invention forms a channel stopper region by using a technique of bonding two semiconductor substrates by direct thermocompression bonding without the intervention of a brazing material such as a metal or an organic material or an adhesive. It is something. That is, a channel stopper region is provided on the main surface of one semiconductor substrate at a position that will be the bottom of the mesa groove, and the other semiconductor substrate is bonded to this.
Create a mesa groove in which the channel stopper appears at the bottom of the groove.
This is a method of forming the second semiconductor substrate. The advantage of this method is that the channel stopper can be formed at a precise location at the bottom of the mesa groove, in a controlled high concentration, and in a short time.

[Embodiments of the Invention] The present invention will be specifically explained below with reference to the process diagram of a mesa diode shown in FIG. Fig. 1 (al) to (a2) are steps related to the first semiconductor substrate, Fig. 1 (bl) to (b2)
1C is a step of providing a channel stopper region and the like on the second semiconductor substrate, and FIGS. 1C to 1D are steps of bonding the first and second semiconductor substrates to form a mesa groove.

31 at 6 in Figure 1 (al) has an impurity concentration of 10''
It is a cr3 N-type silicon substrate. Next, Figure 1 (
As shown in a2), a donor impurity is diffused from the entire upper surface of this N- type silicon substrate 31 in the figure to a surface concentration of 102° cm to form an N+ type high a degree layer 3.
form 3.

On the other hand, 32 in FIG. 1 (bl>) has an impurity concentration of 1.
011018a is another P-type silicon substrate.

Next, as shown in FIG. 1(b2), this silicon substrate 32
In the part corresponding to the bottom of the mesa groove on the upper surface of the figure,
Selectively absorb acceptor impurities at a surface concentration of 10”c+n-
At the same time, an acceptor impurity is diffused from the entire lower surface of the silicon substrate 32 to form a contact P+ region 38.

After that, as shown in FIG. 1(C), FIG. 1(a2)
The substrate of FIG. 1(b2) and the substrate of FIG. 1(a2)
The N- region 34 of the substrate and the channel stopper P+ region 36 side of the plate 14 in FIG. For this bonding, after forming a mirror surface on an open substrate, the mirror surface is cleaned, and the silicon substrates are directly pressed together in a clean atmosphere without using a metal or organic brazing material or adhesive. with 400℃
The adhesive is preferably strengthened by heat treatment at 1100° C. for several hours. Due to this adhesion, the N- region 34 and the P region 3
A diode PN junction is formed between the two.

Finally, as shown in FIG. 1(d), a mesa groove 35 is dug from the N+ side surface of the bonded substrate, and a mesa groove 35 is dug from the P+ region 36.
If the P+ region 36 is positioned at the bottom of the mesa groove 35, a structure is formed in which the P+ region 36 serves as a channel stopper.

A mesa diode with a channel stopper can be obtained by forming an oxide film and an electrode on the substrate shown in Fig. 1(d), and then cutting the pellet into a pellet along the dashed line to obtain the structure shown in Fig. 2. can.

In FIG. 2, 9 is the oxide film and 10 is the electrode.

[Effects of the Invention] According to the manufacturing method of the present invention, the channel stopper region is formed by selective diffusion on the flat substrate of the second semiconductor substrate, which is different from the conventional method of forming the channel stopper region at the bottom of the trench after forming the mesa trench. Compared to the method (the method of FIG. 3), the channel stopper region can be provided in a more accurate position.

Further, according to the manufacturing method of the present invention, since the channel stopper region can be diffused shallowly on the second semiconductor substrate, the depth of the channel stopper region is adjusted to the depth of the mesa trench before forming the mesa trench. Compared to the conventional method (method shown in Figure 4), which requires deep diffusion with additional depth, the diffusion time can be significantly shortened, and the highly concentrated region required as a channel stopper can be created in an extremely controlled manner. be able to.

If the channel stopper region can be formed in a controlled manner at a high concentration at the precise position of the groove bottom, a mesa-type semiconductor device with high reverse breakdown voltage can be realized, and
The diffusion time is short, and the entire process time can be significantly shortened.

[Brief explanation of drawings]

FIG. 1 is a process diagram illustrating the main steps of a method for manufacturing a mesa semiconductor device according to an embodiment of the present invention using a cross section of a semiconductor substrate, FIG. 2 is a sectional view of a mesa semiconductor device to which the present invention relates, and FIGS. FIG. 4 is a process diagram illustrating the main steps of the conventional manufacturing method using a cross section of a semiconductor substrate. 31... First semiconductor substrate of one conductivity type, 32... Second semiconductor substrate of opposite conductivity type, 33... High concentration layer of one conductivity type, 34... Low concentration layer of first semiconductor substrate , 35・
... Mesa groove, 36... High concentration layer of opposite conductivity type (channel stopper), 37... Adhesive surface, 9... Oxide film. Patent applicant Toshiba Corporation (al) (bl
)(c)(d
) 35 35Figure 1 LL Figure 2 (a) (a) Figure 3 Figure 4

Claims (1)

[Claims] 1. A step of providing a high concentration layer of the same conductivity type on one main surface of a first semiconductor substrate of one conductivity type, and a step of providing a high concentration layer of the same conductivity type on one main surface of a second semiconductor substrate of an opposite conductivity type at a position that will be the bottom of the mesa groove,
a step of selectively providing a high concentration layer of opposite conductivity type; and the other exposed main surface of the low concentration layer of the first semiconductor substrate and one main surface of the second semiconductor substrate on which the high concentration layer is selectively provided. A mesa-type semiconductor device comprising the steps of: adhering by thermocompression bonding; and providing a mesa groove in the adhered substrate such that the selectively provided high concentration layer of the second semiconductor substrate is located at the bottom of the mesa groove. manufacturing method.