JPS6212702B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a frequency variable tone signal detection circuit for a wireless tone signal paging receiver.

Conventionally, in this type of tone signal detection circuit, an active filter or the like has been used as a filter, and the detection circuit thereof has been constructed of an analog circuit. Since the center frequency of this active filter is determined by the resistance value and capacitance value, these tolerances must be tightened.
It was difficult to convert it into an IC, and since the detection circuit was an analog circuit, it had the disadvantage that manufacturing deviations were large and the number of adjustment steps was large.

An object of the present invention is to provide a frequency variable tone signal detection circuit that eliminates the above-mentioned drawbacks when implementing an active filter and an analog detection circuit into an IC.

The present invention will be described below with reference to the drawings.

First, the functions of each block in FIG. 1 will be explained. 10 is an antenna, and 11 is, for example, a double super-heterodyne receiver including a discriminator section. 12 functions to saturate the output of the discriminator and remove the AM component of noise and the influence of the drift of the discriminator. Reference numeral 13 denotes an N-path forming filter, which has the function of passing only a frequency of 1/N of the clock frequency. This N-way filter responds to a predetermined tone signal and has a predetermined rise and fall time, and includes, for example, a resistor and N capacitors coupled to each of these N capacitors, and is clocked at a clock frequency 26 as described below. It is composed of N switches that are cyclically opened and closed and closed all at once by a reset pulse 32, which will be described later. Since the output of the N-way filter 14 contains harmonic components and has a staircase waveform, if the waveform is directly shaped, the duty will vary depending on the timing. Therefore,
Converts a staircase wave to a waveform close to a positive frequency wave, and passes the highest frequency of the passing tone frequency used, 2010 Hz, but the lowest frequency of the used passing tone frequency, 459 Hz.
This is a low-pass filter that has the function of blocking the clock frequency of 3672Hz. 15 is a waveform shaping circuit having the function of converting a tone frequency close to a square wave into a square wave. Reference numeral 16 denotes a digital detection circuit which has the function of determining whether the currently passing tone is a desired tone based on whether a predetermined clock has been counted at a certain predetermined time, and the function of generating a reset signal 32 upon detection confirmation. It is. This specific circuit, for example, at least uses the output signal of the waveform shaping circuit 15 to control the clock frequency 2, which will be described later.
6; a counter that detects the number of output signals of this gate circuit; and a counter that determines whether the period of the output of this counter is within a preset value of a desired tone. The lever discrimination signal is output to the control circuit 17 and is also output to the N-way filter 13 as a reset pulse 32 to be described later.
It consists of a frequency detection circuit that supplies
17 has the function of setting the next tone frequency by the output of the digital detection circuit, and when the time between the output of the digital detection circuit and the next output exceeds a predetermined time (for example, 45 ms), the tone frequency of the N-way filter is set. The settings are preset to the first tone of a predetermined tone signal train, the function of creating a desired periodic pulse by dividing the frequency of the timing OSC, and the function of preset to the first tone of a predetermined tone signal train. This control circuit also has the function of notifying you with a sound when all signal sequences have been received. 18 is a transistor matrix type PROM in which a diode is connected to the base of the transistor Tr, and is programmed by making this diode conductive or non-conductive.
The base line of the Tr is connected to the tone frequency specification line of the control circuit, and when this line is set to a high voltage, the contents of that column are read out in parallel, and this signal is output in BCD code. This is a frequency specifying circuit that has the function of

Reference numeral 19 denotes a variable frequency divider circuit which sets a frequency division number based on the BCD output of the frequency designation circuit, divides the frequency of the crystal oscillator XTL 20 in use by this frequency division number, and generates a desired clock frequency.
20 is a crystal oscillator. 21 is a transistor
It is a buffer circuit that is composed of transistors, the sound signal output of the control circuit is connected to the base, and has the function of amplifying it. 22 is for creating the original oscillation of the internal timing frequency of the control circuit, for example,
It can be configured with a Twin-T circuit. 23 is a speaker. 24 is a tone designation readout line which is an output of the control circuit, and is connected to the base of the Tr in the next column line of the transistor matrix. 25 is the content of the PROM at that time and is a BCD code.

26 is a clock frequency generated by a frequency dividing circuit. 32 is a reset pulse for resetting the N-way filter. This reset pulse speeds up the fall time of the N-way filter. 33 is a battery. 34 is a power line. 35 is the output of the timing OSC. 36 is the output of the control circuit and is a sound command line. When the antenna 10 receives the radio signal, the tone signal is demodulated by the receiver 11 and connected to the N-way filter 13 through the limiter 12 . Then, initially, a pre-specified tone signal series (first
~ 6th tone and the calling number is N at the clock corresponding to the first tone frequency (for example, 56231X)
The N-way filter 13 and the digital detection circuit 16 are in a standby state, and the frequency corresponding to this frequency and its harmonic components pass through the N-way filter 13 and are passed through the low-pass filter 14 to produce a waveform close to a normal wave. This output is converted into a shaped wave by waveform shaping. This digitized signal is connected to the digital tone detection circuit 16, and when it is confirmed that it is the desired tone, a certain constant (for example, 2 ms) pulse is created using this pulse, and this pulse is controlled as a detection pulse. It is also used as a reset signal for the N-way filter 13. The detection pulse sent to the control circuit advances the counter by one, and the time slot is switched in order to read out the code corresponding to the predetermined tone signal frequency to be received next. With this switching, the contents of the frequency designation circuit 18 are read out.
It is sent to the frequency divider circuit 19 in BCD code. In this frequency dividing circuit 19, the frequency division number is set by this BCD, so a clock corresponding to the desired next tone frequency is created by the frequency division number corresponding to the BCD at this time, and this is passed to the N-way filter 13. and is sent to the digital tone detection circuit 16. In this way, when all of the predetermined signal strings are detected, the control circuit 17 makes a sound to inform the speaker 2 through the buffer circuit 21.
Drive 3. For example, a, b, and c in Figure 2 are 33
mS, 45mS, and 210mS.

FIG. 3 shows another embodiment of the present invention, in which a battery saving function is added to FIG. 1. FIG. 4 shows an example of the signal configuration in the case of FIG.
In FIG. 3, 37 is a battery saving command signal line outputted from the control circuit 43. Reference numeral 38 is a power line for the part where battery saving is applied. Reference numeral 41 denotes a tone designation readout line for a battery saving release signal (group tone signal). 43 is a counter for canceling battery saving (group signal in FIG. 4), a frequency dividing circuit for creating a pulse width of a desired periodicity, a counter for specifying tone selection, and an arbitrary number of predetermined tone signal sequences. A timer that determines whether the time from when one detection pulse is confirmed until the next detection is confirmed is a predetermined time, and a gate function that issues a sound command when all predetermined tone signal sequences are detected. This control circuit also has a gate function for battery saving. 21' is the speaker 23 in response to the signal from the sound command line 36 mentioned above.
In addition to the function of making a sound, it also has a function of turning the output of the power supply 33 on and off using a signal from the battery saving command line 37 as described later. The other blocks have the same functions as those used in Figure 1.

First, the control circuit 43 sets the voltage of the readout line 41 corresponding to the battery saving cancellation signal (group signal, e.g., d=690 mS) to a high state to specify the tone frequency, and the frequency specifying circuit 4
The contents of 2 are read out and connected to the frequency dividing circuit 19 via BCD. This frequency dividing circuit 19 generates a clock frequency with a frequency division number corresponding to the BCD and is connected to the N-way filter 13 and the digital tone detection circuit 16. At this time, power is periodically turned on and off to parts that do not cause problems even if the power supply 33 is turned off during battery saving operation, such as a high frequency part and a limiter. For example, ON time is 32m
S, OFF time is 480mS. When the power is on (32mS) in this state, when one tone signal for battery saving cancellation (group signal) as shown in Figure 4 is detected, the battery saving operation is temporarily canceled and the 32mS timer is started. After that, the power is maintained for 32mS, and when the second one is detected during this time, the 32mS timer is driven in the same way and the power is turned on for 32mS.
If the power is maintained between S and a third battery saving cancellation tone is detected during that time,
At this point, the power supply is held for 512 mS (=32 mS + 480 mS), the battery saving operation is simultaneously canceled, and the tone signal is switched to the first tone signal of the predetermined tone frequency signal sequence 1 as shown in FIG. Furthermore, if the second battery is not detected within 32 mS after the first battery detection, the battery saving cancellation counter (group signal) is reset and the routine shifts to battery saving operation.

Setting to the first tone signal is done by using the readout line 24.
The contents of the frequency designation circuit are read out by the switching, and the clock frequency is switched by commanding the frequency dividing circuit by BCD, and the N-way filter 13 and the digital tone detection circuit 16 are set to the first tone standby state. If detection of the first tone is confirmed within 512 mS under such conditions, the control circuit 43 sets the time slot to the second tone signal and simultaneously starts, for example, a 45 mS timer. Further, the power supply is maintained for 512 mS after the detection of the first tone.
When the second tone signal is thus detected within 45 mS, the control circuit switches the time slot to wait for the third tone signal. In this way, when all predetermined tone signal sequences are detected, the sound gate of the control circuit is opened and the speaker is driven through the buffer circuit.
By the way, when the 45 mS timer times out, the tone setting is set to standby for the first tone. Also, 512m from the first tone standby
If no tone is detected after s has elapsed, the state returns to the battery saving state. Also, even after receiving a predetermined tone signal sequence,
Since the first tone is further set within 512 mS, when this first tone is received, the power is maintained for another 512 mS starting from that first tone. Also, of course, if the first tone is not detected within 512 mS after the battery saving operation is canceled, the routine transitions to the battery saving operation.

FIG. 5 is a modified embodiment of FIG. 3. below,
The operation of FIG. 5 will be explained. In the figure, 44 is a line when the original frequency for timing of the control circuit 43 is taken out from the variable frequency divider circuit 19.
That is, in this circuit, the timing OSC shown in FIG. 3 is replaced with a signal from the variable frequency divider circuit 19. Therefore, although the operation is exactly the same as that shown in FIG. 3, this example is superior in terms of frequency stability.

FIG. 6 is an embodiment in which a DC-DC converter is added to FIG. 3. The operation of FIG. 6 will be explained below. 39 is the output of the DC-DC converter. 4
0 is a circuit for obtaining a target voltage by step-up or step-down depending on the power supply used, such as a DC-DC converter composed of a C-MOS or a transistor, C, and R, and the clock is a control circuit 43. It uses the OSC22 clock for timing. In this example, when using 1.5V for the power supply, the crystal oscillator
XTL20 as a high frequency source (for example 4MHz)
When dividing the frequency by , it is difficult to operate the C-MOS at a low voltage of 1.5V, so the DC-DC converter 40 is used to step up the voltage. At this low voltage of 1.5V, oscillation of only a few tens of kilohertz, for example, can be obtained. The operation in FIG. 6 is the same as in FIG. 3. That is,
Steady state is battery saving operation, and control circuit 4
3 designates a group signal by a readout line 41. Then, the corresponding clock signal is read out by the frequency designation circuit 42 from the BCD.
It is made by a variable frequency dividing circuit 19 with a frequency dividing number corresponding to the code. In this situation, the power
When ON (32mS), when one group signal is detected, the power is held for an additional 32mS, and if a second group signal is detected during that period, the power is maintained for an additional 32mS.
If the mS power is maintained and the third signal is received during that period, battery saving will be canceled even if the group signal detection is confirmed, and the power will be turned on from there to 512m.
At the same time as S is held, the readout line 24 is switched to set the next standby tone frequency to the first tone frequency of a predetermined tone frequency signal sequence. If the first tone is not detected during 512mS, the battery saving operation is resumed, but if the first tone is detected during 512mS, the power is held for 512mS again, and at the same time, the readout 24 is switched to the predetermined state. set to the second tone in the tone signal train, and at the same time
Drive S timer. At this time, if the second tone is not detected within 45 mS, the readout line 24 is switched and reset to the first tone signal standby state, but if the second tone is detected within 45mS, the control circuit starts reading. The line 24 is switched to enter the standby state for the third tone, and at the same time, the 45 mS timer is driven again. When all the predetermined signal sequences are detected in this process, the tone gate is opened to drive the speaker through the buffer circuit, and at the same time, the readout line 24 is switched to set the first tone.
And when the 512mS timer times out,
Return to battery saving operation.

According to the present invention, the active filter and analog detection circuit conventionally used in such a tone signal detection circuit are replaced with an N-way filter and a digital tone detection circuit, respectively, thereby facilitating design and integration into an IC. Further, by applying a battery saving method to a radio receiver including such an N-way filter and a digital tone detection circuit, power consumption can be reduced, and as a result, a highly reliable LSI can be achieved.

[Brief explanation of the drawing]

Figure 1 is a configuration diagram of an embodiment of the wireless tone calling receiver of the present invention, Figure 2 is an example of the tone signal configuration in Figure 1, and Figure 3 is the configuration of Figure 1 with a battery saving function added. Example, FIG. 4 shows an example of the structure of the tone signal in FIG. 3, and FIG. 5 shows the structure of the tone signal in FIG.
An embodiment in which the configuration of FIG. 3 is simplified, and FIG. 6 is an embodiment in which a voltage conversion circuit is added to the configuration of FIG. 3. 10...Antenna, 11...Receiver, 12...
Limiter, 13... N-way filter, 14... Low pass filter, 15... Waveform shaping circuit, 16...
Digital tone detection circuit, 17... Control circuit, 18... Frequency specification circuit, 19... Variable frequency divider circuit, 20... Crystal oscillator, 21, 21'... Buffer circuit, 22... Timing oscillation circuit ,
23...Speaker, 33...Battery, 40...Voltage conversion circuit, 42...Frequency designation circuit with added battery saving cancellation frequency term, 43...
...Control circuit with added function to control battery saving operation.

Claims (1)

[Scope of Claims] 1. In a tone signal detection circuit that sequentially receives and passes a plurality of tone signals, the frequency of a clock signal is N times (N is an integer) the frequency of each tone signal by a plurality of first control signals. a variable frequency dividing circuit that variably controls the tone signal; an N-way filter that selects the tone signal based on the clock signal and has a predetermined rise time and fall time in response to the tone signal; a low-pass filter for removing frequency components of the waveform shaping circuit; a waveform shaping circuit for shaping the tone signal passed through the low-pass filter; and an output of the waveform shaping circuit responsive to the clock signal and the output of the waveform shaping circuit a detection circuit that determines whether or not is a designated tone signal and outputs a determination signal, and sends this determination signal to the N-way filter as a reset signal for accelerating the falling time; a control circuit that outputs a second control signal and detects that the discrimination signal is a predetermined tone signal sequence; and the first control signal that is predetermined for the second control signal. A tone signal detection circuit comprising: a frequency specifying circuit that outputs a frequency specifying circuit; 2. In a tone signal detection circuit that sequentially receives and passes a plurality of tone signals, a clock signal having a frequency N times (N is an integer) the frequency of each tone signal is generated by a power supply, a timing oscillator, and a plurality of first control signals. a variable frequency divider circuit that variably controls the frequency of the
an N-way filter having predetermined rise and fall times that selects and responds to the tone signal based on the clock signal; and a low-pass filter connected to the N-way filter that removes frequency components of the clock signal. , a waveform shaping circuit for shaping the tone signal that has passed through the low-pass filter, and determining whether the output of the waveform shaping circuit is a designated tone signal in response to the clock signal and the output of the waveform shaping circuit; A detection circuit that outputs a discrimination signal and sends this discrimination signal to the N-way filter as a reset signal for accelerating the falling time; and a detection circuit that maintains the power supply of the battery-saving elements based on the output of the timing oscillator. Generates battery saving timing to open and close every cycle, detects a battery saving release signal received prior to a predetermined tone signal sequence when the power supply is closed, and releases the battery saving operation; a control circuit that sequentially outputs a plurality of second control signals based on the discrimination signal and detects that the discrimination signal is a predetermined tone signal sequence; A tone signal detector comprising: a frequency designation circuit that outputs a first control signal. 3. In a tone signal detection circuit that sequentially receives and passes a plurality of tone signals, a clock signal having a frequency N times (N is an integer) the frequency of each tone signal is generated by a power supply, a timing oscillator, and a plurality of first control signals. a variable frequency dividing circuit that variably controls the frequency; an N-way filter having predetermined rise and fall times that selects and responds to the tone signal based on the clock signal; a low-pass filter for removing frequency components of the waveform shaping circuit; a waveform shaping circuit for shaping the tone signal passed through the low-pass filter; and an output of the waveform shaping circuit responsive to the clock signal and the output of the waveform shaping circuit a detection circuit that determines whether or not is a designated tone signal and outputs a determination signal and sends this determination signal to the N-way filter as a reset signal for accelerating the falling time; and a detection circuit that outputs a determination signal based on the output of the timing oscillator. generates timing for battery saving to open and close the power supply of the element capable of battery saving at regular intervals, and detects a battery saving release signal received prior to a predetermined tone signal sequence when the power supply is closed. a control circuit configured to release a battery saving operation by canceling a battery saving operation, sequentially output a plurality of second control signals based on the discrimination signal, and detect that the discrimination signal is a predetermined tone signal sequence; and a voltage conversion circuit that converts the voltage of the power supply and supplies the output to at least the variable frequency divider circuit. Features a tone signal detection circuit.