JPS621259U - - Google Patents
Info
- Publication number
- JPS621259U JPS621259U JP9280285U JP9280285U JPS621259U JP S621259 U JPS621259 U JP S621259U JP 9280285 U JP9280285 U JP 9280285U JP 9280285 U JP9280285 U JP 9280285U JP S621259 U JPS621259 U JP S621259U
- Authority
- JP
- Japan
- Prior art keywords
- detection circuit
- coincidence detection
- register
- system bus
- debugging device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Debugging And Monitoring (AREA)
Description
第１図は本考案によるデバツグ装置の構成ブロ
ツク図、第２図は本考案のデバツグ装置をコンピ
ユータ・システムに内蔵した構成図、第３図は本
考案のデバツグ装置内のコントロール・レジスタ
の内容を示す図、第４図は本考案のデバツグ装置
内の一致検出回路の具体的な構成図である。
１…デバツグ装置、２…ＣＰＵ、３…ＲＯＭ、
４…ＲＡＭ、５…外部記憶部、６…Ｉ／Ｏ、７…
表示制御部、１１…バス・ドライバ・レシーバ、
１２…ＲＯＭ、１３…ＲＡＭ、１４…アドレス・
レジスタ、１５…データ・レジスタ、１６…コン
トロール・レジスタ、１７…一致検出回路、１７
１，１７２，１７３…デイジタル・コンパレータ
、１７４…プリ・アドレス・レジスタ、１７５，
１７６，１７７…デコーダ、１８…オープン・コ
レクタ・ドライバ、ｇ…ゲート回路。
Fig. 1 is a block diagram of the debugging device according to the present invention, Fig. 2 is a block diagram of the debugging device of the present invention built into a computer system, and Fig. 3 shows the contents of the control registers in the debugging device of the present invention. The figure shown in FIG. 4 is a specific configuration diagram of the coincidence detection circuit in the debugging device of the present invention. 1... Debugging device, 2... CPU, 3... ROM,
4...RAM, 5...external storage, 6...I/O, 7...
Display control unit, 11... bus driver receiver,
12...ROM, 13...RAM, 14...Address
Register, 15... Data register, 16... Control register, 17... Coincidence detection circuit, 17
1 , 17 2 , 17 3 ... digital comparator, 17 4 ... pre-address register, 17 5 ,
17 6 , 17 7 ...decoder, 18...open collector driver, g...gate circuit.
Claims (1)
システムのシステム・バスに接続され、少なくと
もプログラム・アドレス情報が設定されるレジス
タと、このレジスタに設定された内容と前記シス
テム・バス内の該当する情報とを比較して一致出
力を行なう一致検出回路とを備え、この一致検出
回路の出力によつてデバツグ・プログラムを起動
させることを特徴としたデバツグ装置。 Computer using microcomputer
A register connected to the system bus of the system and in which at least program address information is set, and a coincidence detection circuit that compares the contents set in this register with the corresponding information in the system bus and outputs a match. A debugging device characterized in that a debugging program is activated by the output of the coincidence detection circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9280285U JPS621259U (en) | 1985-06-19 | 1985-06-19 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9280285U JPS621259U (en) | 1985-06-19 | 1985-06-19 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS621259U true JPS621259U (en) | 1987-01-07 |
Family
ID=30649919
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9280285U Pending JPS621259U (en) | 1985-06-19 | 1985-06-19 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS621259U (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5487145A (en) * | 1977-12-23 | 1979-07-11 | Fujitsu Ltd | Display system for data comparison and agreement |
| JPS59183443A (en) * | 1983-04-01 | 1984-10-18 | Omron Tateisi Electronics Co | Debug device |
-
1985
- 1985-06-19 JP JP9280285U patent/JPS621259U/ja active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5487145A (en) * | 1977-12-23 | 1979-07-11 | Fujitsu Ltd | Display system for data comparison and agreement |
| JPS59183443A (en) * | 1983-04-01 | 1984-10-18 | Omron Tateisi Electronics Co | Debug device |