JPS621257A - Semiconductor device having laminated structure and manufacture thereof - Google Patents

Semiconductor device having laminated structure and manufacture thereof

Info

Publication number
JPS621257A
JPS621257A JP60138913A JP13891385A JPS621257A JP S621257 A JPS621257 A JP S621257A JP 60138913 A JP60138913 A JP 60138913A JP 13891385 A JP13891385 A JP 13891385A JP S621257 A JPS621257 A JP S621257A
Authority
JP
Japan
Prior art keywords
substrates
semiconductor device
laminated structure
substances
magnetic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60138913A
Other languages
Japanese (ja)
Inventor
Kenji Shiya
士屋　賢二
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP60138913A priority Critical patent/JPS621257A/en
Publication of JPS621257A publication Critical patent/JPS621257A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112—Aligning
    • H01L2224/81121—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
    • H01L2224/81122—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors by detecting inherent features of, or outside, the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]

Abstract

PURPOSE:To position first and second substrates easily by burying conductive magnetizing substances having different polarity into through-hole sections formed onto the first and second substrates, using attractive force between the magnetizing substances for positioning the first and second substrates, and shaping a semiconductor device having laminated structure. CONSTITUTION:A magnetic substance 9 is deposited on first and second substrates 1, 2, to which elements are formed, through a sputtering method. The magnetic substances 9 except a through-hole section are removed selectively through etching, the magnetic substances 9, 9' on the first and second substrates 1, 2 are magnetized so that polarity is directed oppositely, the first and second substrates are positioned by using attractive force between the magnetic substances 9, 9', and the first and second substances 1, 2 are laminated, thus preparing a semiconductor device having laminated structure. Accordingly, positioning on bonding can be mechanized easily.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は積層構造の半導体装置及びその製造方法に関す
る。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor device with a stacked structure and a method for manufacturing the same.

〔発明の技術的背景と問題点〕[Technical background and problems of the invention]

平面における素子の高密度化が限界に近づいている現在
において、今後の技術分野として積層構造の素子が非常
に重要にな・てくる。At present, as the density of elements on a plane is approaching its limit, elements with a multilayer structure will become extremely important as a future technological field.

第２図に示すような積層構造の素子の製造技術において
、素子を第１および第２の基板に別々に形成した後、こ
れを接着させて製造する方法がＩＥＤＮ（１９８４）ｂ
ｙ　Ｍ、ＹＡＳＵＭＯＴＯｅｔ　　ａｌ、に開示されて
いる。しかしながら上記方法にあ、では基板を接着する
時に、裏面から素子パターンが見えない為に位置合わせ
における困難が生じる。In the manufacturing technology of elements with a laminated structure as shown in Fig. 2, a method is proposed by IEDN (1984b) in which elements are formed separately on first and second substrates and then bonded together.
y M, YASUMOTO et al. However, in the above method, when the substrates are bonded together, the element pattern cannot be seen from the back surface, which causes difficulty in alignment.

尚、第１図において１，２は第１及び第２の基板、３．
３′はｐ＋領領域４．４′はｎ＋領領域５．５′はケン
ト電極、６，６′はＡＩ配線、７，７′は銀、８，８′
はポリイミドフィルムである。In FIG. 1, 1 and 2 are first and second substrates; 3.
3' is a p+ region 4.4' is an n+ region 5.5' is a Kent electrode, 6, 6' is an AI wiring, 7, 7' is silver, 8, 8'
is a polyimide film.

〔発明の目的〕[Purpose of the invention]

本発明は表面に素子を形成した第１および第２の基板を
接着して積層構造の素子を製造する場合に、裏面から素
子パターンが見えなく・ても位置合わせが容易ならしめ
る半導体装置及びその製造方法を提供するものである。The present invention provides a semiconductor device and a semiconductor device that facilitate alignment even when the element pattern cannot be seen from the back side when manufacturing a layered element by bonding a first and second substrate with elements formed on the front surface. A manufacturing method is provided.

〔発明の概要〕[Summary of the invention]

本発明は第１および！２の基板上に形成されたスルーホ
ール部に極性の相違なる導電性磁化物を埋め込み、第１
および第２の基板の位置合わせに前記磁化物間の引力を
用いて積層構造の半導体装置を形成することを骨子とす
るものである。The present invention is first and! Conductive magnets with different polarities are embedded in the through-hole portions formed on the second substrate.
The main idea is to use the attractive force between the magnetized materials to align the second substrate to form a semiconductor device with a stacked structure.

磁性体としては例えばＫＳ鋼、アルニコなどを挙げるこ
とができる。Examples of the magnetic material include KS steel and alnico.

〔発明の効果〕〔Effect of the invention〕

本発明によれば第１層を形成した基板と第２層を形成し
た基板を接着させて、積層構造の半導体装置を製造する
場合に、裏面から素子パターンが見えなくても接着させ
る時の位置合わせが容易に機械化できる。According to the present invention, when manufacturing a semiconductor device with a stacked structure by bonding a substrate on which a first layer is formed and a substrate on which a second layer is formed, the position for bonding even if the element pattern is not visible from the back side. Fitting can be easily mechanized.

〔発明の実施例〕[Embodiments of the invention]

以下、本発明の実施例を図面を用いて説明する。 Embodiments of the present invention will be described below with reference to the drawings.

第１図（ａ）〜（ｄ）は本発明方法の一実施例を示す工
程図で、第２図と同一部分は同一符号で示しである。FIGS. 1(a) to 1(d) are process diagrams showing an embodiment of the method of the present invention, and the same parts as in FIG. 2 are indicated by the same symbols.

第１図（ａ）に示す如く、素子を形成した第１および第
２の基板１．２に磁性体９を周知のスパッタ法で堆積す
る。次に第１図（ｂ）に示す如く、スルーホール部以外
の磁性体９をエツチングで選択的〈除去する。次に第１
図（Ｃ）に示す如く、Ｍｌと第２の基板１，２上の磁性
体９，９′を極性が反対向きになるように磁化し、第１
図（ｄ）の様に該磁性体９．９′間の引力を用いて位置
合わせを行い、第１と第２の基板１，２を貼り合わせ、
第１図（ｄ）の如く積層構造の本発明の半導体装置を作
成する。As shown in FIG. 1(a), a magnetic material 9 is deposited on the first and second substrates 1.2 on which elements are formed by a well-known sputtering method. Next, as shown in FIG. 1(b), the magnetic material 9 other than the through-hole portions is selectively removed by etching. Then the first
As shown in FIG.
As shown in Figure (d), positioning is performed using the attractive force between the magnetic bodies 9 and 9', and the first and second substrates 1 and 2 are bonded together,
A semiconductor device of the present invention having a stacked structure as shown in FIG. 1(d) is produced.

尚、Ｋｌおよび第２の基板１，２の貼シ合わせる方法に
ついては、例えばＩＥＤＭ（１９８４）ｂｙ−Ｍ、ＹＡ
８ＵＭＯＴＯｅｔ　ａｌ、に示されて込る通りである。The method of bonding Kl and the second substrates 1 and 2 is described in, for example, IEDM (1984) by-M, YA
8UMOTO et al.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の一実施例を製造工程順に示す断面図１
．第２図は第１層と第２層の素子を別々の基板上に形成
した後、これを貼シ合わせて製造した従来の積層構造の
半導体装置の断面図である。 １・・・ｎ型単結晶シリコン基板、２・・・ｐ型単結晶
シリコン基板、３・・・ｐ型ソース及びドレイン領域、
４・・・ｎ型ノース及びドレイン領域、５・・・ゲート
電極、６・・・アルミニウム配線、７・・銀、８１．ポ
リイミドフィルム、９・・・磁性体。 代理人弁理士　　則　近　憲　佑　（ほか１名）＠２図Figure 1 is a sectional view 1 showing an embodiment of the present invention in the order of manufacturing steps.
．． FIG. 2 is a sectional view of a conventional semiconductor device having a laminated structure, which is manufactured by forming first and second layer elements on separate substrates and then bonding them together. 1... N-type single crystal silicon substrate, 2... P-type single crystal silicon substrate, 3... P-type source and drain region,
4... N-type north and drain region, 5... Gate electrode, 6... Aluminum wiring, 7... Silver, 81. Polyimide film, 9...magnetic material. Representative Patent Attorney Noriyuki Chika (and 1 other person) @2 diagram

Claims (2)

【特許請求の範囲】[Claims] （１）第１の素子層と該第１の素子層の上方に位置する
第２の素子層とを電気的に接続する配線が、少なくとも
一部に極性の相異なる２つの導電性磁石を含むことを特
徴とする積層構造の半導体装置。(1) The wiring electrically connecting the first element layer and the second element layer located above the first element layer includes at least a portion of two conductive magnets with different polarities. A semiconductor device with a laminated structure characterized by the following. （２）表面に素子を形成した第１および第２の基板を接
着させ、該２枚の基板間で電気的導通を有する積層構造
の素子を形成する方法において、基板間スルーホール部
にそれぞれ極性を反対向きにした導電性磁性体を埋め込
み、該磁性体間の引力を用いて位置合わせをすることを
特徴とする積層構造の半導体装置の製造方法。(2) In a method of bonding first and second substrates with elements formed on their surfaces to form an element with a laminated structure having electrical continuity between the two substrates, each of the through-holes between the substrates is provided with a polarity. 1. A method of manufacturing a semiconductor device having a laminated structure, characterized in that conductive magnetic materials having opposite directions are embedded, and positioning is performed using the attractive force between the magnetic materials.
JP60138913A 1985-06-27 1985-06-27 Semiconductor device having laminated structure and manufacture thereof Pending JPS621257A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60138913A JPS621257A (en) 1985-06-27 1985-06-27 Semiconductor device having laminated structure and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60138913A JPS621257A (en) 1985-06-27 1985-06-27 Semiconductor device having laminated structure and manufacture thereof

Publications (1)

Publication Number Publication Date
JPS621257A true JPS621257A (en) 1987-01-07

Family

ID=15233069

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60138913A Pending JPS621257A (en) 1985-06-27 1985-06-27 Semiconductor device having laminated structure and manufacture thereof

Country Status (1)

Country Link
JP (1) JPS621257A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7432114B2 (en) 2006-03-30 2008-10-07 Fujitsu Limited Semiconductor device manufacturing method
JP2009004622A (en) * 2007-06-22 2009-01-08 Sony Corp Semiconductor device
JP4472023B1 (en) * 2009-12-11 2010-06-02 有限会社ナプラ SUBSTRATE FOR ELECTRONIC DEVICE, LAMINATE FOR ELECTRONIC DEVICE, ELECTRONIC DEVICE, AND METHOD FOR PRODUCING THEM
JP2010199113A (en) * 2009-02-23 2010-09-09 Nec Corp Three-dimensional semiconductor integrated circuit and method of manufacturing the same

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7432114B2 (en) 2006-03-30 2008-10-07 Fujitsu Limited Semiconductor device manufacturing method
JP2009004622A (en) * 2007-06-22 2009-01-08 Sony Corp Semiconductor device
JP2010199113A (en) * 2009-02-23 2010-09-09 Nec Corp Three-dimensional semiconductor integrated circuit and method of manufacturing the same
JP4472023B1 (en) * 2009-12-11 2010-06-02 有限会社ナプラ SUBSTRATE FOR ELECTRONIC DEVICE, LAMINATE FOR ELECTRONIC DEVICE, ELECTRONIC DEVICE, AND METHOD FOR PRODUCING THEM
JP2011124433A (en) * 2009-12-11 2011-06-23 Napura:Kk Substrate for electronic device, laminate for electronic device, electronic device, and method of manufacturing the same

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