JPS6212391A - Speed controller - Google Patents

Abstract

PURPOSE:To shorten a starting time by reducing a rotating speed by switching an input clock pulse of a counter when a rotating speed exceeds the prescribed range, thereby suppressing the excess rotating speed at starting time. CONSTITUTION:A synchronizing signal generator 15 generates a synchronizing signal synchronized with a rotation detection signal (FG signal). A counter 16 counts an input clock pulse to detect the speed error from the reference speed of a rotor, and outputs accelerating and decelerating pulses (i), (j). A counter clock controller 17 switches the period of the input clock pulse of the counter 16 when the rotating speed of a rotor exceeds from the reference speed in the prescribed range to decelerate the speed of the rotor.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a device for controlling a single rotating body to a constant speed, and in particular aims at shortening the startup time by reducing excessive rotational speed during startup. This invention relates to a speed control device.

[Conventional technology]

2. Description of the Related Art Floppy disk drive circuit devices (FDD) and the like are required to start up a rotating body within a limited time and to control the speed of the rotating body with high precision. As a conventional speed control device of this type, there is one disclosed in, for example, Japanese Unexamined Patent Publication No. 10086/1986.

FIG. 5 is a block diagram showing the circuit configuration of such a conventional speed control device for a rotating body. In the figure, reference numerals 1 and 2 denote an N-ary counter and an N-ary counter ( N.

M is an integer), 3.4 is a falling differential circuit, 5°6 is R
The positive logic output terminal Q of each S flip-flop is connected to the reset terminal π of the counter 1.2. 7
, 8 is a gate circuit for synthesizing acceleration pulses and deceleration pulses for driving the rotating body, and 9゜lO is a gate circuit 7.8 for these gate circuits.
The switch circuit is connected to the discharge type current source 11 and the suction type current source 12 by a switch circuit which is turned on and off depending on the output of the current source 11. 13 is a cumulative capacitor, 14 is a cumulative capacitor 13
This is an output buffer circuit that controls the drive of the rotating body according to the voltage of the rotor.

Next, the operation will be explained. The N-ary counter l is a counter that counts input clock pulses for a certain period of time using the fall of a rotation detection signal (hereinafter referred to as FG multiplication signal) as a trigger signal, which has a period corresponding to the rotation speed of the rotating body to be controlled. be.

The falling differentiation circuit 3 detects the falling edge of the FG multiplied signal and outputs a low level (Low 1evel) detection pulse. Then, when the RS flip-flop 5 is set by this detection pulse, the output of its positive logic terminal Q becomes a high level (High level), and the N-ary counter l enters the counting mode and starts counting clock pulses. . N-ary counter 1 converts clock pulses into N
When counting, the output under the terminal count output terminal changes from high level to low level at that moment. This output terminal is connected to the reset terminal π of the RS flip-flop 5, and the moment the output at the terminal T becomes low level, the output from the terminal Q of the RS flip-flop 5 also becomes low level, and the N-ary counter 1 is reset, enters counting stop mode, and stops.

Further, with the falling timing when the output terminal Q of the RS flip-flop 5 changes from high level to low level as the trigger timing, the M-ary counter 2, the falling differentiation circuit 4, and the RS flip-flop 6 convert into the above-mentioned N-ary counter. It performs an operation similar to that of , and counts clock pulses for a certain period of time.

If the period of the above clock pulse is τ, then the N-ary counter 1
The constant time counted by is Nτ, and the M-ary counter 2
The fixed time counted by is Mt. Here, define a reference period 1/fo, that is, a reference frequency fo, such that 1/fo = Nτ + Mτ (constant), and multiply this frequency fo by the above FG when the rotating body reaches the target rotation speed. shall match the signal frequency. As a result, acceleration pulses and deceleration pulses having pulse widths corresponding to the speed error of the rotating body can be obtained as outputs of the acceleration pulse synthesis gate circuit 7 and the deceleration pulse synthesis gate circuit 8, respectively.

FIG. 6 is a time chart showing the operation of synthesizing the above acceleration pulse and deceleration pulse, and each point (a) in FIG.
-(e) shows signal waveforms.

The acceleration and deceleration pulses synthesized by gate circuits 7 and 8 act on switch circuits 9 and 10, respectively. That is, when the output of the acceleration pulse synthesis gate circuit 7 becomes high level, the switch circuit 9 is closed and a discharge current is applied from the discharge type current source 11 (voltage E) to the accumulation capacitor 13, and its potential is increased. In addition, the deceleration pulse synthesis gate circuit 8
When the output becomes high level, the switch circuit 10 is closed, the suction current of the suction type current source 12 flows out of the accumulation capacitor 13, and its potential decreases. At this time, the absolute values (I) of the amounts of the discharge current and the suction current are made equal.

The speed error information converted into analog voltage information by the cumulative capacitor 13 is given to a motor drive circuit (not shown) via a charge pump output buffer circuit 14 having high input impedance and low output impedance, and The rotation speed of is controlled.

[Problem that the invention seeks to solve]

However, in the conventional speed control device as described above, unless the rotational speed of one rotating body exceeds a preset reference speed and a deceleration pulse is output, the potential of the cumulative capacitor 13 replaces deceleration error information with voltage information. Since the rotational speed does not decrease, there is a problem that it takes a long time to start until the rotational speed reaches the allowable rotational speed error range at startup.

This invention has been made to solve these problems, and provides a speed control device that can minimize the amount of excess rotational speed of the rotating body during startup and start the rotating body in a short startup time. The purpose is to

[Means for solving problems]

A synchronization signal generation circuit that generates a synchronization signal synchronized with a rotation signal having a period corresponding to the rotation speed of the rotating body, and a speed error between the reference speed of the rotating body and the reference speed of the rotating body is detected by counting the input clock pulses with a predetermined period. A speed control device that includes a counter circuit that outputs acceleration/deceleration control pulses, and a voltage control circuit that has a cumulative capacitor that is charged and discharged by the acceleration/deceleration control pulses and controls the drive voltage of the rotating body. A counter clock control circuit is provided that switches the period of the input clock pulse of the counter circuit to reduce the speed of the rotating body when the speed exceeds the reference speed by more than a predetermined range.

[Effect]

The counter circuit outputs an acceleration/deceleration pulse having a pulse width according to the speed error of the rotating body when the rotational speed of the rotating body is slower than the reference speed or near the reference speed, and the voltage control circuit outputs an acceleration/deceleration pulse having a pulse width according to the speed error of the rotating body. Charges or discharges the cumulative capacitor and controls the driving voltage of the rotating body. At that time, the counter clock circuit switches the period of the clock pulse input to the counter circuit when the rotation speed of the rotating body exceeds a certain range and becomes over-rotated, thereby decelerating the object with a pulse width longer than normal. The pulses are combined, the accumulation capacitor is rapidly discharged, and the rotating body is decelerated.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.
In the figure, 15 is a synchronization signal generation circuit that generates a synchronization signal synchronized with the FG multiplied signal, and 16 is a synchronization signal generation circuit that counts input clock pulses to detect a speed error with the reference speed of the rotating body and accelerates and decelerates control pulses (acceleration pulses and deceleration A counter circuit 17 outputs a pulse), and 17 is a counter clock 7 that switches the period of the input clock pulse of the counter circuit 16 to reduce the speed of the rotating body when the rotational speed of the rotating body exceeds the reference speed by more than a predetermined range. This is a control circuit.

The counter circuit 16 includes a falling differentiation circuit 18, R
S flip-flop 19, m-bit binary counter 20,
It is composed of an OR gate circuit 21, an acceleration pulse synthesis gate circuit 22, and a deceleration pulse synthesis gate circuit 23,
The output side of the falling differentiation circuit 18 is connected to the reset terminal R of the RS flip-flop 19 and one input side of the OR gate circuit 21, and the output terminal Q of the RS flip-flop 19 is connected to the other input side of the OR gate circuit 21 and .

It is connected to the input side of the gate circuits 22 and 23, and the output side of the OR gate circuit 21 is connected to the reset terminal R of the binary counter 2o. In addition, the counter clock control circuit 1
7 is a frequency dividing circuit 24 that divides the clock pulse into l/N.
, a rise delay circuit 25, and a clock switching circuit 26 for switching the clock pulse to the m-bit binary counter 20.

Although not shown in the figure, a voltage control circuit having a cumulative capacitor charged and discharged by the acceleration/deceleration control pulses is connected to the subsequent stage of the counter circuit 16, as in the conventional case.
The drive voltage of the rotating body can be controlled.

Next, the operation will be explained with reference to the time chart shown in FIG. In addition, Figure 2 shows each point (a) and (f) in Figure 1.
-(j) shows signal waveforms and waveforms representing analog counts of the m-bit binary counter 20.

The m-bit binary counter 20 starts counting by using the fall of a specific FG multiplication signal as a trigger signal, and stops when a predetermined value is reached, but if the rotational speed of the rotating body is slower than the reference speed or When the speed is near the reference speed,
The time from the start of counting until it stops corresponds to the reference speed. Therefore, the counter circuit 16 can be used to measure the period error of the FG multiplied signal in the interval from the falling point of the FG multiplied signal to the next falling point.

First, the synchronization signal generation circuit 15 generates a signal (f) synchronized with the FG multiplied signal a) based on a clock pulse.

The falling differentiation circuit 18 generates a pulse signal at the falling edge of this signal (f), and the RS flip-flop 1
Reset 9. As a result, m-bit binary counter 2
0 is 0m when the reset state is released and counting operation starts.
When the count value reaches a predetermined value, the bit binary counter 20 outputs a terminal count signal to set the RS flip-flop 19, and at the same time is automatically reset to stop the counting operation.

Further, the 1 frequency divider circuit 24 outputs a signal obtained by dividing the clock pulse into l/N to the clock switching circuit 26, and the rise delay circuit 25 outputs the signal (f) from the synchronizing signal generating circuit 15.
When a signal whose rising edge is delayed by a predetermined time is output and acts on the clock switching circuit 26, the clock signal input to the m-bit binary counter 20 is switched. That is, when the output signal (h) of the rise delay circuit 25 is at a low level, a reference clock pulse is input to the counter 20, and when the signal (h) is at a high level, a clock pulse whose frequency has been divided by 17N is input to the counter 20. Pulse is counter 20
is input.

Here, with a reference clock pulse being input to the m-bit binary counter 20, the time from when the counter 20 starts counting until it stops is calculated when the rotational speed of the rotating body reaches the reference speed. If the above reference clock pulse is set to match the period of the FG multiplied signal a),
The inverted signal of the output signal (f) of the synchronization signal generation circuit 15 and R
By ANDing the output signal (8) of the S flip-flop 19, an acceleration pulse having a pulse width corresponding to the speed error can be synthesized, and by ANDing the above signal (D) and the inverted signal of signal (g), Similarly, a deceleration pulse having a pulse width corresponding to the speed error can be synthesized.

Further, the deceleration signal is generated when the output (f) of the synchronizing signal generating circuit 15 is at a high level and the RS flip-flop 19
Since the output is at a low level, that is, when the m-bit binary counter 20 is in counting operation, the allowable range for the excess rotation speed when the rotating body is near the reference speed is considered. The m-bit binary counter 20 is activated by the signal (h) whose rise time is delayed by the rise delay circuit 25 by a preset time.
clock pulse input from the reference clock pulse
If the clock pulse is switched to a clock pulse whose frequency is divided by N, the counting operation time of the counter 20 will require N times the time after the switching point.

The deceleration pulse is the original pulse radiation (A) as shown in Figure 2.
It has the above extra pulse width (b).

By the way, as can be seen from FIG. 2, in the basic speed error detection circuit configuration shown in FIG. 1, the speed control signal is output once every two periods of the FG double signal.
It has been shown that by suitably pluralizing the output signals of the synchronization signal generation circuit 15 and preparing basic speed error detection circuits corresponding to the number of output signals, it is possible to output a speed control signal for each cycle of the FG multiplied signal. It means. FIG. 3 shows another embodiment of the present invention in which the synchronizing signal generation circuit 15 has two outputs and two sets of the speed error detection circuits are prepared.
The figure is a time chart showing the operation.
The same parts as in FIG. 2 are shown by adding suffixes a and b to numerical numbers, and the same signal names are shown by adding suffixes 1 and 2. Further, 27 and 28 are OR gate circuits. As shown in FIG. 4, by shifting the outputs (fl) and (f2) of the synchronizing signal generation circuit 15 by one cycle of the FG double signal, a speed control signal is output every cycle of the FG double signal. can do. Furthermore, the charge pump 2 having the cumulative capacitor 13 in FIG.
The function of 9 (voltage control circuit) is the same as that explained in the conventional example, so it will be omitted, but the rotation speed of the rotating body is controlled by the analog voltage signal of this charge pump via the motor drive circuit (not shown). can be controlled.

Each embodiment has been described above, and as described above.

The cumulative capacitor can be rapidly discharged to lower the potential during over-rotation, while taking into account the allowable range for excess rotation speed when the rotation speed of the rotating body is around the reference speed.
It becomes possible to reduce the overshoot at startup and shorten the startup time without affecting the steady state characteristics at all.

〔Effect of the invention〕

As explained above, according to the present invention, when the rotational speed of the rotating body exceeds a predetermined range from the reference speed, the input clock pulse of the counter circuit is switched to reduce the speed of the rotating body. It is possible to minimize the excessive amount of rotational speed of the rotating body, and it is possible to achieve the effect that the starting time of the rotating body can be shortened.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a time chart showing signal waveforms at each point in FIG. 1, and FIG.
The figure is a block diagram showing another embodiment of the present invention, FIG. 4 is a time chart showing signal waveforms at each point in FIG. 883, and FIG.
The figure is a block diagram showing the circuit configuration of a conventional speed control device.
FIG. 6 is a time chart showing signal waveforms at each point in FIG. 15... Synchronous signal generation circuit 16... Counter circuit 17... Counter clock control circuit 27...
...Charge pump (voltage control circuit) Note that the same reference numerals in the drawings indicate the same or equivalent parts.

Claims (1)

[Claims] A synchronization signal generation circuit that generates a synchronization signal synchronized with a rotation signal having a period corresponding to the rotation speed of the rotating body, and a speed error between the reference speed of the rotating body and the reference speed of the rotating body is detected by counting the input clock pulses with a predetermined period. A speed control device that is equipped with a counter circuit that outputs acceleration/deceleration control pulses, and a voltage control circuit that has a cumulative capacitor that is charged and discharged by the acceleration/deceleration control pulses and controls the drive voltage of the rotating body. A speed control device comprising a counter clock control circuit that reduces the speed of the rotating body by switching the period of the input clock pulse of the counter circuit when the speed exceeds the reference speed by more than a predetermined range.