JPS6215036B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital motor speed control circuit. Synchronous AC motors, AC servo motors, DC Servo motors, etc. are used, but synchronous AC motors are large in size and the rotation speed is determined by the power supply frequency, so they are not suitable for so-called direct drive motors, which directly connect the motor shaft and drive shaft. It is towards. Furthermore, when comparing AC servo motors and DC servo motors, DC servo motors are more efficient and relatively easier to control, so DC servo motors are increasingly being used for the above applications. Conventionally, the speed control circuit for this DC servo motor has been comprised mostly of analog circuits, requiring external components such as capacitors, fixed resistors, and potentiometers in addition to IC-based semiconductor circuits.

In recent years, digital circuits have become highly integrated, and it has become possible to construct even somewhat complex circuits using a small number of LSIs, so various digital servo control circuits have been devised.

FIG. 5 is a block diagram showing an example of a conventional digital servo control circuit, in which an FG signal a from a frequency generator FG directly connected to a motor M is waveform-shaped into a rising differential signal a' by a clock synchronized differentiating circuit 1. Ru. The speed counter 12 generates a motor speed signal v from the rising differential signal a' and the clock pulse C. On the other hand, the phase counter 15 counts the phase difference between the command pulse CP and the rising differential signal A' using the clock pulse C to generate a phase difference signal.
Output Pe. The subtracter 16 generates the phase difference signal Pe
and the speed signal v is calculated, and the pulse width modulation circuit 17 turns on and off the output transistor 8 at a duty according to the error e to control the motor current. This conventional digital servo control circuit operates in such a way that when the delay time of the rising differential signal a' with respect to the command pulse CP increases, the phase difference signal Pe and the error e increase, the motor current increases, and the delay time is shortened. do. On the other hand, as the motor speed increases, the motor speed signal v increases and the error e decreases, so the motor current also decreases and the motor speed slows down. In this method, stable control is possible because phase feedback and speed feedback are involved, but the speed counter 12, phase counter 15, and pulse width modulation circuit 17 require a somewhat complicated circuit configuration, and currently It has not been put into practical use due to the high cost.

The present invention provides a digital motor speed control circuit which provides phase and speed feedback without impairing stability and has a simplified circuit configuration, and will be described in detail below.

FIG. 1 is a block diagram showing one embodiment of the present invention;
FIG. 2 is a time chart of this block diagram. In FIG. 1, 1 is a clock synchronized differentiating circuit that differentiates the FG signal from a frequency generator FG directly connected to a DC motor M and outputs a rising differential signal a';
2 is a period counter that is preset to "10" by this rising differential signal a' and counts up the number of clocks in one period of the FG signal; 3 is preset to a value K times the count number of period counter 2;
4 is a reference signal generation circuit for dividing the clock pulse C and generating a motor synchronization reference signal; 5 is a phase between the motor synchronization reference signal and the output signal of preset counter 3; phase comparator, which compares
6 is an underspeed detection circuit that generates an underspeed signal when the count number of the period counter 2 exceeds a certain value; 7 is a buffer amplifier; and 8 is an output transistor.

In the above configuration, when the frequency generator FG outputs the FG signal shown in FIG. 2a, the clock synchronized differentiation circuit 1 differentiates this FG signal a to generate a rising differential signal a' shown in FIG. 2b. This differential signal
A' causes the synchronous counter 2, which is an 8-bit preset counter, to be preset to a value of "10", and the clock pulse C continues until the next rising differential signal a'.
Count up the number of. In this embodiment, the clock frequency is set to 240 times the FG signal synchronization frequency. Therefore, the period counter 22 counts up to a value around "250". When the motor rotation speed is low, such as during startup, and the number of clock pulses N in one period of the rising differential signal a' is N≧246.
Then, the count number N' of the period counter 2 exceeds "256" and an overflow signal O is generated to set the underspeed detection circuit 6, reset the phase comparator 5, and output the output transistor 8 via the buffer amplifier 7. is forcibly turned on. This reduces the motor startup time.

FIG. 3 shows a specific example of the underspeed detection circuit, and FIG. 4 shows its time chart. In this embodiment, when the period counter 2 generates an overflow signal O shown in FIG. 4b, the R-S flip-flop 61 is set. This R-S flip-flop 61 is reset by the rising differential signal a' (FIG. 4a) immediately after the overflow signal O, but the shift register 62 holds the underspeed signal until the next rising differential signal a'. The OR gate 63 outputs an underspeed signal U shown in FIG. 4c as a sum signal of the outputs of the R-S flip-flop 61 and the shift register 62.

Further, when N<246, the following operation is performed. First, a value K times the count number N' of the period counter 2 is preset in the 8-bit preset counter 3 by the rising differential signal a'. Bits 9th and above from the bottom are ignored. In this example, K=16,
The lower 4 bits of the output of the period counter 2 are preset inputted into the upper 4 bits of the preset counter 3. Therefore, the multiplier can be omitted. Note that by changing the value of K, the amount of feedback can be changed. When N=230, cycle counter 2
The count number N' is "240", but when expressed in hexadecimal, it becomes _FOH , and the lower 4 bits are 0. When 230≦N≦245, the preset value M of the reset counter 3 becomes M=(N-230)×16, and this value is counted down by the clock pulse C. When the count value of the preset counter 3 reaches 0, a borrow signal b shown in FIG. 2c is generated.

The reference signal generation circuit 4 sets the clock frequency to 1/240.
The motor synchronization reference signal r shown in FIG.
occurs.

The phase comparator 5 is realized by, for example, an R-S flip-flop, and detects a phase difference signal d between the motor synchronization reference signal r and the borrow signal b of the preset counter 3.
(Fig. 2 e) is output. The phase difference signal d is level-converted by the buffer amplifier 7 and switches the output transistor 8. When the phase delay amount of the FG signal a increases with respect to the motor synchronization reference signal r, the operation of the period counter 2 and the preset counter 3 is delayed, and the generation of the borrow signal b is delayed.
The time width of the phase difference signal d is widened, the duty of the motor current is increased, the motor is accelerated, and the phase delay amount is shortened. Furthermore, when the motor rotation speed decreases and the FG signal period increases, the count number N+10 of the period counter 2 increases, and the preset value M of the preset counter 3 increases, so the generation of the borrow signal b is delayed and the motor is stopped. Operates to accelerate. When the motor speed changes by about 0.4% (1/240),
N changes by 1 and M changes by 16. Therefore, the duty of the motor current changes by approximately 6.7% (16/240), and it has strong resilience against motor speed fluctuations.

As explained in detail above, the present invention has the effect of controlling the speed of the motor by performing phase feedback and speed feedback using a simple digital signal circuit.
It also has the advantage that it can be configured with a small number of integrated circuits and output transistors without using external components such as capacitors. Furthermore, if a microprocessor is used, it can be realized without using a special integrated circuit.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention;
FIG. 2 is a time chart thereof, FIG. 3 is a block diagram of an underspeed detection circuit, FIG. 4 is a time chart thereof, and FIG. 5 is a block diagram of a conventional digital servo circuit. DESCRIPTION OF SYMBOLS 1...Clock synchronous differentiation circuit, 2...Period counter, 3...Preset counter, 4...Reference signal generation circuit, 5...Phase comparator, 6...Underspeed detection circuit, 7...Buffer amplifier, 8 …
...Output transistor, 61...R-S flip-flop, 62...Shift register, 63...OR gate.

Claims (1)

[Claims] 1. A period counter that counts the period of the output signal of the frequency generator directly connected to the controlled DC motor, and a period counter that counts the period of the output signal of the frequency generator that is directly connected to the controlled DC motor, and a counter that counts the period of the output signal of the frequency generator that is directly connected to the controlled DC motor, and a counter that counts the period of the output signal of the frequency generator that is directly connected to the controlled DC motor. A preset counter that presets a value and generates an output signal when counting down to a predetermined value, a motor synchronization reference signal generation circuit, and a phase difference signal between the motor synchronization reference signal and the output signal of the preset counter. a phase comparator that outputs, an amplifier that amplifies the phase difference signal to a predetermined level, and a switching element that controls the duty of the motor current according to the output of the amplifier;
A digital motor speed control circuit comprising: an underspeed detection circuit that supplies a signal to the phase comparator to forcibly turn on the switching element when the period counter exceeds a predetermined count value.