JPS62121989A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To speed up the action of a semiconductor integrated circuit including a logical gate circuit such as a decoder circuit by connecting serial FETs forming a logical gate circuit in parallel. CONSTITUTION:A complementary data line and a common complementary data line are selectively connected by NOR gates G2-G5 formed with P-type FETs Q11-Q17, which are series with P-type FETs Q10-Q16 controlled by a NAND gate circuit G1 such as a column decoder circuit and are controlled by a selective output from a predecoder circuit PDCR. These serial FETs Q10, Q11-Q14 and Q15 are connected in parallel. If a gate G2, etc., are selected, not only a current from the power source side FET Q10 of the gate G2 but also currents from the power side FETs of other gates G3-G5 are supplied to the FET Q11 made in an off state, and a drive current is made larger. Thus the action of the semiconductor integrated circuit including the logical gate such as a decoder circuit can be sped up.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a semiconductor integrated circuit device, for example, a CMOS (complementary MO3) such as a semiconductor memory.
The present invention relates to a technique that is effective for use in devices equipped with a decoder circuit.

[Background technology]

Semiconductor storage devices such as RAM (Random Access Memory) and ROM (Read Only Memory) are provided with an address decoder that generates a selection signal to select one memory cell. These address decoders can be constructed of, for example, 2T1 logic gate circuits that receive n-bit address signals. However, if this is done, the number of logic gate circuits becomes enormous, and the logic gate circuits are formed within a relatively narrow pinch of the word lines and data lines (bit lines or digit lines) that constitute the memory array. This becomes difficult.

Therefore, it is conceivable to divide the address decoder into a plurality of parts to reduce the number of elements and achieve a high-density layout on the semiconductor substrate. For example, as shown in FIG. 3, a plurality of selection timing signals φy00 to φyt1 formed by a predecode circuit (not shown) and an address signal a2
The output signal of the unit decoder (NAND gate circuit) circuit G1 that receives at or at is connected to four logic gates (NOR
gate) circuits G2 to G5 to form four selection signals YSO to YS3.

Thereby, the unit decoder circuit G1 can be formed to match the relatively large pitch of the four selection signal lines.

However, the gate circuits G2 to G5 are connected to the selection signal lines YSO to YS arranged in a relatively narrow pinch.
3 etc., so the above logic gate circuit 0
The element size of MO5FETQIO to G13 constituting the second etc. must be made small. As a result, the problem arises that the current drive capability is limited and the operating speed becomes slow.

Regarding the address decoder in the dynamic RAM, see, for example, Japanese Patent Application Laid-Open No. 53-41946.

[Purpose of the invention]

An object of the present invention is to provide a semiconductor integrated circuit device including a logic gate circuit such as a decoder circuit that operates at high speed.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Summary of the invention]

A brief overview of typical embodiments of the invention disclosed in this application is as follows. That is,
Among the multiple MOSFETs arranged in series in the CMO5 logic gate circuit, the M
By supplying a common input signal to the gates of the OS FETs,
The MOS FETs receiving these common input signals are connected in parallel.

〔Example〕

Figure 1 shows a dynamic RA to which this invention is applied.
A circuit diagram of one embodiment of M is shown.

In the RAM shown in the figure, peripheral circuits such as an address buffer and an address decoder are formed by CMOS circuits.

The structure of an integrated circuit can be roughly explained as follows. That is, of the surface portion of a semiconductor substrate made of single crystal P-type silicon and on which an N-type well region is formed, other than the surface portion that is used as an active region, in other words, the semiconductor wiring region, the capacitor formation region, and the N-channel and A relatively thick field insulating film formed by a known selective oxidation method is formed in areas other than the source, drain, and channel forming region (gate forming region) of the P-channel MOSFET. Although the capacitor formation region is not particularly limited, an IN-th polysilicon layer is formed on the capacitor formation region with a relatively thin insulating film (oxide film) interposed therebetween. The first polysilicon layer extends over the field insulating film. A thin oxide film formed by thermal oxidation of the first polysilicon layer is formed on the surface of the first polysilicon layer. A channel is formed on the surface of the semiconductor substrate in the capacitor formation region by forming an N-type region by ion implantation or by supplying a predetermined voltage. As a result, a capacitor consisting of the first polysilicon layer, a thin insulating film, and a channel region is formed. The first polysilicon layer on the field oxide film is regarded as a type of wiring.

A second polysilicon layer to serve as a gate electrode is formed on the channel formation via a thin gate oxide film. This second polysilicon layer extends over the field insulating film and over the first polysilicon layer. Although not particularly limited, word lines and dummy word lines in a memory array, which will be described later, are constructed from a second polysilicon layer.

On the surface of the active region not covered by the field insulating film and the first and second polysilicon layers, source, drain, and semiconductor wiring regions are formed by a known impurity doping technique that uses them as an impurity doping mask. There is.

A relatively thick glabellar insulating film is formed on the surface of the semiconductor substrate including the first and second polysilicon layers, and a conductor layer made of aluminum is formed on this glabellar insulating film. . The conductor layer is electrically coupled to the polysilicon layer and the semiconductor region through a contact hole provided in the insulating film below. A data line in a memory array, which will be described later, is composed of a conductor layer extending on this glabella insulating film, although it is not particularly limited.

The surface of the semiconductor substrate including the top of the glabella insulating film and the top of the conductor layer is covered with a final passivation film made of a silicon nitride film and a phosphosilicade glass film.

A 1-bit memory cell MC, as shown as a representative, has an information storage capacitor Cs and an address selection M
03FETQm, and information on logic "1" and "0" is stored in the form of whether or not there is charge in the capacitor Cs.

To read information, turn on the MO5FETQm, connect the capacitor Cs to the common data line DL, and sense how the potential of the data line DL changes depending on the amount of charge N multiplied by the capacitor Cs. It is done by

The memory cells MC are formed small and the common data line D
Since many memory cells are connected to L to form a highly integrated and large capacity memory matrix, the capacitor Cs and
Ratio Cs of common data line DL to stray capacitance Go (not shown)
/Co becomes a very small value. Therefore, the data line DL due to the amount of charge accumulated in the capacitor Cs
The potential change is a very small signal.

A dummy cell DC is provided as a reference for outputting such a minute signal. This dummy cell DC is made under the same manufacturing conditions and the same design constants as the memory cell MC, except that the capacitance value of the capacitor Cd is half that of the capacitor Cs of the memory cell MC, although there is no particular restriction. .

Capacitor Cd is connected to MO3 prior to addressing.
Charged to ground potential by FETQd'. In this way, since the capacitor Cd is set to have a capacitance value that is approximately half that of the capacitor Cs, it forms a reference voltage that is equal to half the read signal from the memory cell MC.

The number of memory cells coupled to complementary data lines DL, DL is made equal to increase detection accuracy, and one dummy cell is coupled to each of DL, DL. Furthermore, each memory cell MC is coupled between one word line WL and one of the complementary pair data lines. Since each word line WL crosses both data line pairs, even if a noise component generated on the word line WL is transferred to the data line due to capacitive coupling, the noise component will be transmitted to both data line pairs DL, DL. They appear equally and are canceled out by a differential sense amplifier SA, which will be described later. In addressing, complementary data 11tDL,
When a memory cell MC coupled to one of DL is selected, one of a pair of dummy word lines DWL, DWL is selected so that a dummy cell DC is always coupled to the other data line.

The sense amplifier SA is a pair of cross-wired MO3FE
It has TQI and Q2, and due to their positive feedback action, a minute signal appearing on complementary data lines DL and DL is differentially amplified. This positive feedback operation is performed in two stages and starts at the same time as the MO3FET Q7, which has a relatively small conductance, starts to conduct in response to a relatively early timing signal φpal. Based on this, the higher data line potential falls at a slower rate, and the lower one falls at a faster rate, with the difference widening.

At this time, when the voltage difference becomes large to a certain extent, the MOSFET Q
Since B is made conductive by the timing signal φpa2, the potential of the lower data line drops rapidly. By operating the sense amplifier SA in two stages in this manner, the drop in the higher potential is prevented. In this way, when the lower potential drops below the threshold voltage of the cross-coupled MOS FET, the positive feedback operation ends, and the higher potential remains lower than the power supply voltage VCC and higher than the above threshold voltage. At the same time, the lower potential finally reaches the ground potential (OV).

During the above-mentioned addressing, the stored information in the memory cell MC, which is about to be destroyed, is recovered by directly receiving the high-level or low-level potential obtained by this sensing operation. However, as described above, when the high level drops by a certain level or more with respect to the power supply voltage Vcc, a malfunction occurs in which the data is read as a logic "0" while reading and rewriting are repeated several times. An active restore circuit AR is provided to prevent this malfunction. This active restore circuit AR has the function of selectively boosting only high level signals to the potential of power supply voltage Vcc without having any effect on low level signals.

A data line pair DL, which is shown as a representative in the figure,
DL is MOSFETQ that constitutes the column switch CW
3. Common complementary data line pair CDL, CDL via Q4
connected to. Similar MO5FETQ5. It is connected to the common complementary data line pair CDL, CDL via Q6. This common complementary data line pair CDL, CDL is connected to an input terminal of a data output buffer DOB including an output amplifier and an output terminal of a data buffer sofa DIB.

The row address decoder R-DCR and the column address decoder C-DCR are connected to the row address buffer R, which will be described later.
-Addressing of memory cells and dummy cells is performed by forming one word line, dummy word line, and column switch selection signals in response to internal complementary address signals formed by -ADB and column address buffer C-ADH, respectively. That is, the row address buffer R-AD
B takes in the external address signal AXO=AXi in synchronization with the timing signal φar generated by the row address strobe signal RAS, and transmits it to the row decoder R-DCH. The row decoder R-DCR decodes the address signal and also outputs the word line selection timing signal φX.
A predetermined word line and dummy word line selection operation is performed in synchronization with .

In addition, the column address buffer C-ADB takes in external address signals AYO to AYi in synchronization with the timing signal φac generated by the column address strobe signal CAS that is supplied with a delay.
Tell R. Column decoder C-DCR decodes the address signal and selects a data line in synchronization with data line selection timing signal φy.

The column address buffer C-ADB and column address decoder C-DCR are static type CMOS.
Consists of circuits. This provides a continuous access mode (static column mode) function by keeping one word line in a selected state and changing the column address signal to switch the selected data line.

The timing control circuit TC receives address strobe signals RAS, CAS and a write enable signal WE supplied from the outside, and forms various timing signals in addition to the representative timing signals shown above.

FIG. 2 shows a circuit diagram of an embodiment of the column address decoder C-DCH. In the figure, the MOSFET whose channel portion is marked with an arrow is a P-channel MOSFET.

Although not particularly limited, column address decoder C-DC
R is divided into two parts. That is, the predecoder circuit POCR receives complementary address signals aQ and 11 consisting of 2 bits and a data line selection timing signal φy, and forms four types of data line selection timing signals φyOO to φyu. For example, a non-inverted address signal aO
If and al are both low level, the signal φyOO is the non-inverted address signal, and if the non-inverted address signal aO is high level and al is the low level, the signal φy01 is the non-inverted address signal aO, and if the non-inverted address signal aO is low level and al is high level, the signal φlO is the non-inverted address signal. Signals aO and al are both high level and young signal φyll
are set to low level in synchronization with the rising of word line selection timing signal ψy to high level. Here, the complementary address signals aO and 11 represent the non-inverted address signals aQ, a1 and the inverted address signals ao, al.

The remaining address signals a2 to ai are converted into NAND signals (NA) constituting a unit decoder circuit according to a predetermined combination.
ND) is supplied to the gate circuit G1. This unit circuit G1
The output signal of the predecoder circuit PDCR and the four signals φy00 to φyll of the predecoder circuit PDCR are connected to four NORs (NO
R) It is supplied to gate circuits G2 to G5, and four types of decoded output signals YSO to YS3 are formed.

The NOR gate circuits G2 to G5 are constituted by the following circuit elements, as shown in the concrete circuits of NOR gate circuits G2 and G5. Noah gate circuit G
2 is an N-channel MOSFET Q1 in series configuration.
N-channel MOSFE configured in parallel with 0 and Qll
TG12. Consists of G13. MO of the above series type
Of SFETQIO and Qll, a Nant gate circuit G as a decoder circuit of the above unit is connected to the gate of MO3FETQIO whose source is connected to the power supply voltage terminal Vcc.
1 output signal is provided. The above Nant gate circuit G1
The output signal of one of the parallel MOSFEs is
Also supplied to the gate of TQI 2. The NOR gate circuit G5 shown as another representative is also a MOSFET similar to the above.
Consists of ETQI 4 to G17. The series MOSFET QI4 in this NOR gate circuit G5.
Of G15, the output signal of the Nant gate circuit G1 as the unit decoder circuit is supplied to the gate of MOSFET QI4 whose source is connected to the power supply voltage terminal Vcc. The output signal of the Nant gate circuit G1 is also supplied to the gate of one of the parallel MOSFETs QI6.

The remaining NOR gate circuits G3 and G4 are also composed of circuits similar to those described above, and the gate of the MOSFET placed on the power supply voltage side among the series type MOSFETs and the gate of one of the parallel type MOSFETs. , the output signals of the Nant gate circuit G1 are commonly supplied.

A signal φy00 formed by the predecoder circuit PDCR is supplied to the gates of MOSFET QI1 and G12, which serve as other input terminals in the NOR gate circuit G2. Similarly, the other input terminals of the NOR gate circuits G3 to G5 are connected to predecoder circuits PDC.
R output signal (data line selection timing signal) φyO
1, φylO and φyll are supplied.

By forming four data line selection timing signals φy00 to φyll according to such address signals ao and al, four data line selection signals YSO to YS3 are formed by the output of the one unit circuit G1. I can do it. As a result, the memory array MARY shown in FIG. 1 has a relatively wide occupied area by being composed of complementary data lines DL, DL arranged at a relatively narrow pitch and a relatively large number of MOSFETs. The pitch of the unit circuits G1 etc. can be matched. Therefore, the memory array MARY and its address decoder can be arranged at high density on the semiconductor substrate.

In this embodiment, there are four NOR gate circuits G2 to G5.
Focusing on the fact that the output signal of the unit decoder circuit G1 is commonly received, the series configuration (7) is used as described above.
MOS FET Q 10 , Q 11 and G14. Among G15 etc., MO3FETQ on the power supply voltage side
The output signal of the decoder circuit G1 of the above unit is supplied to IO, G14, etc. Since these are always turned on and off at the same time, they are connected in parallel. That is, the MOSFE in the NOR gate circuit G2
The connection point between TQI O and Qll is connected to another NOR gate circuit G.
Similar series configuration MOSFETQ in 3 to G5
This is a common connection between interconnects such as I4 and G15.

As a result, for example, when the output signal of the unit decoder circuit Gl forms a low-level selection signal 7, each NOR gate circuit G2 or the P-channel MO3FETs QIO, G14, etc. on the power supply voltage side of G5 are all activated. N-channel MO turned on and supported
SFETQI 2°G16 etc. are turned off. After that, when one data line selection timing signal φyoO is set to low level by the predecoder circuit PDCR in synchronization with the rise of the data line selection timing signal φy, the P-channel MO3FET of the NOR gate circuit G2
QI 1 is on, N-channel MO3FETQi
3 is turned off, the data line selection signal YSO rises to high level, and the column switch MOS
l? Turn on E T and connect complementary data lines DL and D.
Connect L to the common complementary data lines CDL and CDL.

In this selection operation, the above-mentioned MOSF
ETQI 1 includes MOSFETQIO as well as MO5 on the power supply voltage side in other NOR gate circuits G3 to G5.
Since current is also supplied from the FET, a relatively large drive current flows.

In other words, the P-channel MOSF on the power supply voltage side
Since the combined conductance of the ET can be increased by the four P-channel MOSFETs arranged in parallel, the combined conductance seen from the output terminal of the NOR gate circuit G2 that forms the selection signal YSO can be increased.

In addition, in other NOR gate circuits G3 to G5,
Since the P-channel MO3FET on the output terminal side is turned off by the high level of the output signals φy01 and φyll of the corresponding predecoder circuits PDCH, the voltages f! All of the current flowing through the all-overwhelming P-channel MOSFETs flows to the NOR gate circuit 02 that forms the selection signal.

As a result, a relatively small M formed in accordance with the relatively narrow pitch of the selection signal lines YSO to Y83, etc.
A NOR gate circuit consisting of an OSFET can also increase its current drive capability.

In this way, the column selection operation can be performed at high speed by improving the current drive capability. In particular, it is possible to speed up the continuous access mode in which the word line is selected and the column address signals are switched one after another.

〔effect〕

(11CM OSAM) Out of multiple MOS FETs arranged in series in a gate circuit, a common input signal is supplied to the gate of the MOSFET placed on the operating voltage terminal side, and the MOS receives these common input signals. F
By connecting the ETs in parallel to each other, when forming an output signal of one level through the series-type MOS FETs, the on-state of the other CMOS logic gate circuit forming the output signal of the other level is A MOSFET that is turned on can be used to form an output signal of one of the levels. This provides the effect that an output signal of one of the above levels can be formed at -C1 high speed.

(2) According to (11) above, it is possible to achieve the effect of increasing the speed of the static column mode in which continuous access operations are performed by switching column address signals.

(3) According to (1) above, the selection signal can be formed by also using the series MO3FET in the unit circuit that forms the non-selection output signal, so the desired signal transfer characteristics can be achieved with a relatively small element size. Since it is possible to obtain an output signal using the same method, it is possible to achieve the effect of achieving high integration.

Although the invention made by the present inventor has been specifically explained based on Examples above, this invention is not limited to the above Examples, and it is possible to make various changes without departing from the gist of the invention. For example, the number of signals configured by the predecoder circuit can take various embodiments. A signal formed by another predecoder circuit may also be supplied to the input side of the unit decoder circuit.

Further, the circuit receiving the common input signal and the alternatively formed input signal may have P-channel MOSFETs arranged in parallel and N-channel MOSFETs arranged in series. .

In this case, the common input signal may be supplied to the gate of the MOSFET provided on the ground potential side of the circuit among the series MOSFETs, so that these MOSFETs are arranged in parallel with each other. Note that, similarly to FIG. 2, the positive power supply voltage Vcc
is used to convert a high level such as the power supply voltage Vcc to logic “1”.
”, the CMOS logic gate circuit with the above configuration has a Nant gate configuration. When such a Nant gate circuit is used, only the one whose input signals are at high level can be used. forms a low level output signal.

In addition, the reference voltage required for the read operation of the memory cell of the dynamic RAM uses a dummy cell-less method that uses a Vcc/2 precharge voltage formed by shorting the high level and low level of the complementary data line. It may be something.

The specific circuit configuration of the other peripheral circuits that constitute the dynamic RAM can take various embodiments. For example, the address signals may be supplied from independent external terminals.

[Application field]

This invention is applicable not only to dynamic RAMs but also to static RAMSROMs, including various decoding circuits that receive and decode multiple bit input signals, and multiple decoding circuits that receive a common input signal and alternative input signals. C consisting of
It can be widely used in semiconductor integrated circuit devices equipped with MOS 3M gate circuits.

[Brief explanation of drawings]

Figure 1 shows a dynamic RAM to which this invention is applied.
FIG. 2 is a circuit diagram showing an embodiment of the decoder circuit. FIG. 3 is a circuit diagram showing an example of a decoder circuit considered prior to the present invention. MARY...Memory array, MC...Memory cell, DC
・・Dummy cell, CW・・Column switch, SA・・Sense amplifier, AR・・Active restore circuit, R-D
CR...Row address decoder, C-DCR...Column address decoder, R-ADH...Row address decoder, C-ADB...Column address buffer, DoB...
・Data output cover sofa, DIB・・Data input buffer TC・・Timing control circuit, PDCR・・Predecoder circuit, G1・・Unit circuit (Nant gate circuit), 02
~G5...Noah gate circuit AYO~^Y1

Claims (1)

[Claims] 1. A common input signal is supplied to the gates of MOSFETs arranged on the operating voltage terminal side among a plurality of MOSFETs arranged in series in a CMOS logic gate circuit,
A semiconductor integrated circuit device comprising a plurality of logic gate circuits in which MOSFETs receiving this input signal are arranged in parallel. 2. The semiconductor integrated circuit device constitutes a semiconductor memory,
The plurality of logic gate circuits described above receive a common address decoder output signal and a plurality of operation timing signals formed by the predecoder circuit, and form a memory cell selection signal. A semiconductor integrated circuit device according to claim 1.